Data Sheet

PCU9654
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Rev. 1 — 2 July 2012
Product data sheet
1. General description
The PCU9654 is a UFm I2C-bus controlled 8-bit LED driver optimized for voltage switch
dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output
has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that
operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the
LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps)
group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency
between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %
to 99.6 % that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9654 operates with
a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow
voltages up to 40 V for LED supply.
The PCU9654 is one of the first LED controller devices in a new Ultra Fast-mode (UFm)
family. UFm devices offer higher frequency (up to 5 MHz).
The active LOW Output Enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices need to be dimmed
or blinked together without using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9654 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time, thus minimizing I2C-bus
commands. Six hardware address pins allow up to 64 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCU9654
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
2. Features and benefits
 8 LED drivers. Each output programmable at:
 Off
 On
 Programmable LED brightness
 Programmable group dimming/blinking mixed with individual LED brightness
 5 MHz Ultra Fast-mode I2C-bus interface
 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 97 kHz PWM signal
 256-step group brightness control allows general dimming (using a 190 Hz PWM
signal) from fully off to maximum brightness (default)
 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and duty
cycle from 0 % to 99.6 %
 Eight open-drain outputs can sink between 0 mA to 100 mA and are tolerant to a
maximum off state voltage of 40 V. No input function.
 Output state change programmable on the Acknowledge (bit 9, this bit is always set
to 1 by UFm I2C-bus master) or the STOP Command to update outputs byte-by-byte
or all at the same time (default to ‘Change on STOP’).
 Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of
the LEDs when LED driver output state is fully ON (LDRx = 01 in LEDOUT0/1
registers)
 Six hardware address pins allow 64 PCU9654 devices to be connected to the same
UFm I2C-bus and to be individually programmed
 4 software programmable UFm I2C-bus addresses (one LED Group Call address and
three LED Sub Call addresses) allow groups of devices to be addressed at the same
time in any combination (for example, one register used for ‘All Call’ so that all the
PCU9654s on the I2C-bus can be addressed at the same time and the second register
used for three different addresses so that 1⁄3 of all devices on the bus can be
addressed at the same time in a group). Software enable and disable for I2C-bus
address.
 Software Reset feature (SWRST Call) allows the device to be reset through the UFm
I2C-bus
 25 MHz internal oscillator requires no external components
 Internal power-on reset
 Noise filter on USDA/USCL inputs
 Glitch free LED outputs on power-up
 Supports hot insertion
 Low standby current
 Operating power supply voltage (VDD) range of 2.3 V to 5.5 V
 5.5 V tolerant inputs on non-LED pins
 40 C to +85 C operation
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: TSSOP24
PCU9654
Product data sheet
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Rev. 1 — 2 July 2012
© NXP B.V. 2012. All rights reserved.
2 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
3. Applications





RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Type number
Topside mark
PCU9654PW
PCU9654
PCU9654
Product data sheet
Package
Name
Description
Version
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
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Rev. 1 — 2 July 2012
© NXP B.V. 2012. All rights reserved.
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PCU9654
USCL
NXP Semiconductors
5. Block diagram
PCU9654
Product data sheet
A0 A1 A2 A3 A4 A5
INPUT FILTER
USDA
UFm I2C-BUS
CONTROL
POWER-ON
RESET
VSS
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
97 kHz
25 MHz
OSCILLATOR
24.3 kHz
LED1
FET
DRIVER
GRPFREQ
REGISTER
MUX/
CONTROL
GRPPWM
REGISTER
LED0
190 Hz
'0' – permanently OFF
'1' – permanently ON
OE
002aag320
Block diagram of PCU9654
PCU9654
4 of 36
© NXP B.V. 2012. All rights reserved.
Fig 1.
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Rev. 1 — 2 July 2012
All information provided in this document is subject to legal disclaimers.
LED7
VDD
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
6. Pinning information
6.1 Pinning
VSS
1
24 VDD
A0
2
23 USDA
A1
3
22 USCL
A2
4
21 n.c.
A3
5
20 A5
A4
6
VSS
7
LED0
8
17 LED7
LED1
9
16 LED6
LED2 10
15 LED5
LED3 11
14 LED4
PCU9654PW
19 OE
18 VSS
13 VSS
VSS 12
002aag321
Fig 2.
Pin configuration for TSSOP24
6.2 Pin description
Table 2.
PCU9654
Product data sheet
Pin description
Symbol
Pin
Type
Description
VSS
1, 7, 12, 13, 18
power supply
supply ground
A0
2
I
address input 0
A1
3
I
address input 1
A2
4
I
address input 2
A3
5
I
address input 3
A4
6
I
address input 4
LED0
8
O
LED driver 0
LED1
9
O
LED driver 1
LED2
10
O
LED driver 2
LED3
11
O
LED driver 3
LED4
14
O
LED driver 4
LED5
15
O
LED driver 5
LED6
16
O
LED driver 6
LED7
17
O
LED driver 7
OE
19
I
active LOW output enable for LEDs
A5
20
I
address input 5
n.c.
21
I
do not connect; reserved input
USCL
22
I
UFm serial clock line
USDA
23
I
UFm serial data line
VDD
24
power supply
supply voltage
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Rev. 1 — 2 July 2012
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5 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCU9654”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 64 possible programmable addresses using the six hardware
address pins. One of these addresses cannot be used as it is reserved for Software Reset
(SWRST), leaving a maximum of 63 addresses. Using other reserved addresses can
reduce the total number of possible addresses even further.
7.1.1 Regular UFm I2C-bus slave address
The UFm I2C-bus slave address of the PCU9654 is shown in Figure 3. To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable address
pins and they must be pulled HIGH or LOW.
Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if
the devices are on the bus and/or the bus will be open to other I2C-bus systems at some
later date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCU9654 treats them like any other address. The
LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
• PCU9654 LED All Call address (1110 000) and Software Reset (0000 0110) which are
active on start-up
• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
•
•
•
•
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
W (write only)
slave address
0
A5
A4
A3
A2
A1
A0
hardware selectable
Fig 3.
0
002aag322
Slave address
The last bit of the address byte defines the operation to be performed. For UFm I2C-bus,
there is only write operation in slave device.
PCU9654
Product data sheet
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Rev. 1 — 2 July 2012
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6 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.1.2 LED All Call UFm I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled.
See Section 7.3.8 “ALLCALLADR, LED All Call UFm I2C-bus address” for more detail.
Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as
a regular I2C-bus slave address since this address is enabled at power-up. All the
PCU9654s on the I2C-bus will respond to the address if sent by the I2C-bus master.
7.1.3 LED Sub Call UFm I2C-bus addresses
• 3 different UFm I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: E2h or 1110 001
– SUBADR2 register: E4h or 1110 010
– SUBADR3 register: E8h or 1110 100
• Programmable through I2C-bus (volatile programming)
• At power-up, Sub Call I2C-bus addresses are disabled.
See Section 7.3.7 “SUBADR1 to SUBADR3, UFm I2C-bus subaddress 1 to 3” for more
detail.
7.1.4 Software Reset UFm I2C-bus address
The address shown in Figure 4 is used when a reset of the PCU9654 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
W = logic 0. If W = logic 1, the PCU9654 does not recognize the SWRST. See Section 7.6
“Software reset” for more detail.
W (write only)
0
0
0
0
0
1
1
0
002aag323
Fig 4.
Software Reset address
Remark: The Software Reset UFm I2C-bus address is a reserved address and cannot be
used as a regular UFm I2C-bus slave address or as an LED All Call or LED Sub Call
address.
PCU9654
Product data sheet
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Rev. 1 — 2 July 2012
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7 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.2 Control register
Following the successful recognition of the slave address, LED All Call address or LED
Sub Call address, the bus master will send a byte to the PCU9654, which will be stored in
the Control register.
The lowest 5 bits are used as a pointer to determine which register will be accessed
(D[4:0]). The highest 3 bits are used as Auto-Increment Flag (AIF) and Auto-Increment
options (AI[1:0]).
register address
AIF AI1 AI0
D4
D3
D2
D1
D0
002aag324
Auto-Increment options
Auto-Increment Flag
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 5.
Control register
When the Auto-Increment Flag is set (AIF = logic 1), the five low order bits of the Control
register are automatically incremented after a write. This allows the user to program the
registers sequentially. Four different types of Auto-Increment are possible, depending on
AI1 and AI0 values.
Table 3.
Auto-Increment options
AIF
AI1
AI0
Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for all registers. D[4:0] roll over to 00h after the last
register (11h) is accessed.
1
0
1
Auto-Increment for individual brightness registers only. D[4:0] roll over to
02h after the last register (09h) is accessed.
1
1
0
Auto-Increment for global control registers only. D[4:0] roll over to 0Ah’
after the last register (0Bh) is accessed.
1
1
1
Auto-Increment for individual and global control registers only. D[4:0] roll
over to 02h after the last register (0Bh) is accessed.
Remark: Other combinations not shown in Table 3 (AIF + AI[1:0] = 001b, 010b, and 011b)
are reserved and must not be used for proper device operation.
AIF + AI[1:0] = 000b is used when the same register must be accessed several times
during a single I2C-bus communication, for example, changes the brightness of a single
LED. Data is overwritten each time the register is accessed during a write operation.
AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for
example, power-up programming.
AIF + AI[1:0] = 101b is used when the eight LED drivers must be individually programmed
with different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
PCU9654
Product data sheet
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8 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
AIF + AI[1:0] = 110b is used when the LED drivers must be globally programmed with
different settings during the same I2C-bus communication, for example, global brightness
or blinking change.
AIF + AI[1:0] = 111b is used when individual and global changes must be performed
during the same I2C-bus communication, for example, changing a color and global
brightness at the same time.
Only the 5 least significant bits D[4:0] are affected by the AIF, AI1 and AI0 bits.
When the Control register is written, the register entry point determined by D[4:0] is the
first register that will be addressed (write operation), and can be anywhere between
0 0000 and 1 0001 (as defined in Table 4). When AIF = 1, the Auto-Increment flag is set
and the rollover value at which the register increment stops and goes to the next one is
determined by AI[1:0]. See Table 3 for rollover values. For example, if the Control register
= 1110 0100 (E4h), then the register addressing sequence will be (in hex):
04  …  0B  02  …  0B  02  …  0B  02  …  0B  02  … as long
as the master keeps sending data.
7.3 Register definitions
Table 4.
Register summary[1]
Register number (hex) D4
D3
D2
D1
D0
Name
Type
Function
00
0
0
0
0
0
MODE1
write only
Mode register 1
01
0
0
0
0
1
MODE2
write only
Mode register 2
02
0
0
0
1
0
PWM0
write only
brightness control LED0
03
0
0
0
1
1
PWM1
write only
brightness control LED1
04
0
0
1
0
0
PWM2
write only
brightness control LED2
05
0
0
1
0
1
PWM3
write only
brightness control LED3
06
0
0
1
1
0
PWM4
write only
brightness control LED4
07
0
0
1
1
1
PWM5
write only
brightness control LED5
08
0
1
0
0
0
PWM6
write only
brightness control LED6
09
0
1
0
0
1
PWM7
write only
brightness control LED7
0A
0
1
0
1
0
GRPPWM
write only
group duty cycle control
0B
0
1
0
1
1
GRPFREQ
write only
group frequency
0C
0
1
1
0
0
LEDOUT0
write only
LED output state 0
0D
0
1
1
0
1
LEDOUT1
write only
LED output state 1
0E
0
1
1
1
0
SUBADR1
write only
I2C-bus subaddress 1
0F
0
1
1
1
1
SUBADR2
write only
I2C-bus subaddress 2
10
1
0
0
0
0
SUBADR3
write only
I2C-bus subaddress 3
11
1
0
0
0
1
ALLCALLADR
write only
LED All Call I2C-bus address
[1]
Only D[4:0] = 0 0000 to 1 0001 are allowed and will be recognized. D[4:0] = 1 0010 to 1 1111 are reserved and will not be recognized.
PCU9654
Product data sheet
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PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.3.1 Mode register 1, MODE1
Table 5.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AIF
not user
programmable
0
Register Auto-Increment disabled.
1*
Register Auto-Increment enabled.
Remark: set by Control register (Figure 5) in bit 7.
6
AI1
not user
programmable
0*
Auto-Increment bit 1 = 0.
1
Auto-Increment bit 1 = 1.
Remark: set by Control register (Figure 5) in bit 6.
5
AI0
not user
programmable
0*
Auto-Increment bit 0 = 0.
1
Auto-Increment bit 0 = 1.
Remark: set by Control register (Figure 5) in bit 5.
4
3
2
1
0
SLEEP
SUB1
SUB2
SUB3
ALLCALL
W
W
W
W
W
0
Normal mode[1].
1*
Low power mode. Oscillator off[2].
0*
PCU9654 does not respond to I2C-bus
subaddress 1.
1
PCU9654 responds to I2C-bus subaddress 1.
0*
PCU9654 does not respond to I2C-bus
subaddress 2.
1
PCU9654 responds to I2C-bus subaddress 2.
0*
PCU9654 does not respond to I2C-bus
subaddress 3.
1
PCU9654 responds to I2C-bus subaddress 3.
0
PCU9654 does not respond to LED All Call I2C-bus
address.
1*
PCU9654 responds to LED All Call I2C-bus address.
[1]
It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings
on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the
500 s window.
[2]
No blinking or dimming is possible when the oscillator is off.
7.3.2 Mode register 2, MODE2
Table 6.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
PCU9654
Product data sheet
Bit
Symbol
Access
Value
Description
7
-
not user
programmable
0*
reserved, write must always be a logic 0
6
-
not user
programmable
0*
reserved, write must always be a logic 0
5
DMBLNK
W
0*
group control = dimming.
1
group control = blinking.
4
-
W
0*
reserved; write must always be a logic 0
3
OCH
W
0*
outputs change on STOP command[1]
1
outputs change on ninth clock cycle (USCL)
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PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Table 6.
MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit
Symbol
Access
Value
Description
2
-
W
1*
reserved; write must always be a logic 1[2]
1
-
W
0*
reserved; write must always be a logic 0[2]
0
-
W
1*
reserved; write must always be a logic 1[2]
[1]
Change of the outputs at the STOP command allows synchronizing outputs of more than one PCU9654.
Applicable to registers from 02h (PWM0) to 0Dh (LEDOUT1) only.
[2]
Remark: If you change these bits from their default values, the device will not perform as expected.
7.3.3 PWM0 to PWM7, individual brightness control
Table 7.
PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
02h
PWM0
7:0
IDC0[7:0]
W
0000 0000* PWM0 Individual Duty Cycle
03h
PWM1
7:0
IDC1[7:0]
W
0000 0000* PWM1 Individual Duty Cycle
04h
PWM2
7:0
IDC2[7:0]
W
0000 0000* PWM2 Individual Duty Cycle
05h
PWM3
7:0
IDC3[7:0]
W
0000 0000* PWM3 Individual Duty Cycle
06h
PWM4
7:0
IDC4[7:0]
W
0000 0000* PWM4 Individual Duty Cycle
07h
PWM5
7:0
IDC5[7:0]
W
0000 0000* PWM5 Individual Duty Cycle
08h
PWM6
7:0
IDC6[7:0]
W
0000 0000* PWM6 Individual Duty Cycle
09h
PWM7
7:0
IDC7[7:0]
W
0000 0000* PWM7 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT1 registers).
 7:0 
duty cycle = IDCx
--------------------------256
(1)
7.3.4 GRPPWM, group duty cycle control
Table 8.
GRPPWM - Group brightness control register (address 0Ah) bit description
Legend: * default value
Address
Register
Bit
Symbol
Access
Value
Description
0Ah
GRPPWM
7:0
GDC[7:0]
W
1111 1111*
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the eight outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT1
registers).
PCU9654
Product data sheet
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11 of 36
PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC  7:0 
duty cycle = -------------------------256
(2)
7.3.5 GRPFREQ, group frequency
Table 9.
GRPFREQ - Group Frequency register (address 0Bh) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
0Bh
GRPFREQ
7:0
GFRQ[7:0]
W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT1
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
GFRQ  7:0  + 1
global blinking period = ----------------------------------------  s 
24
(3)
7.3.6 LEDOUT0 and LEDOUT1, LED driver output state
Table 10.
LEDOUT0 to LEDOUT1 - LED driver output state register (address 0Ch to 0Dh)
bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
0Ch
LEDOUT0
7:6
LDR3
W
00*
LED3 output state control
5:4
LDR2
W
00*
LED2 output state control
3:2
LDR1
W
00*
LED1 output state control
1:0
LDR0
W
00*
LED0 output state control
7:6
LDR7
W
00*
LED7 output state control
5:4
LDR6
W
00*
LED6 output state control
3:2
LDR5
W
00*
LED5 output state control
1:0
LDR4
W
00*
LED4 output state control
0Dh
LEDOUT1
LDRx = 00 — LED driver x is off (default power-up state, x = 0 to 7).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled). The OE pin can be used as external dimming/blinking control in this state.
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx registers, the GRPPWM registers and the GRPFREQ
register.
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PCU9654
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.3.7 SUBADR1 to SUBADR3, UFm I2C-bus subaddress 1 to 3
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 0Eh to
10h) bit description
Legend: * default value.
Table 11.
Address
Register
Bit
Symbol
Access Value
Description
0Eh
SUBADR1
7:1
A1[7:1]
W
1110 001*
I2C-bus subaddress 1
0
A1[0]
W only
0*
reserved (must write 0)
A2[7:1]
W
1110 010*
I2C-bus subaddress 2
0Fh
SUBADR2
7:1
0
A2[0]
W only
0*
reserved (must write 0)
10h
SUBADR3
7:1
A3[7:1]
W
1110 100*
I2C-bus subaddress 3
0
A3[0]
W only
0*
reserved (must write 0)
Subaddresses are programmable through the UFm I2C-bus. Default power-up values are
E2h, E4h, E8h, and the device(s) will not respond to these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to logic 1 in order to have the device respond to these addresses (MODE1 register).
Only the seven MSBs representing the UFm I2C-bus subaddress are valid. The LSB in
SUBADRx register is a reserved bit and must write logic 0.
When SUBx is set to logic 1 in MODE1 register, the corresponding UFm I2C-bus
subaddress can be used during a UFm I2C-bus write sequence.
7.3.8 ALLCALLADR, LED All Call UFm I2C-bus address
ALLCALLADR - LED All Call UFm I2C-bus address register (address 11h)
bit description
Legend: * default value.
Table 12.
Address
Register
Bit
Symbol
Access Value
Description
11h
ALLCALLADR
7:1
AC[7:1]
W
1110 000*
ALLCALL I2C-bus
address register
0
AC[0]
W only
0*
reserved (must write 0)
The LED All Call I2C-bus address allows all the PCU9654s on the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default
state)). This address is programmable through the I2C-bus and can be used during an
I2C-bus write sequence. The register address can also be programmed as a Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a reserved bit and must write logic 0.
If ALLCALL bit = 0 in the MODE1 register, the device does not respond to the address
programmed in register ALLCALLADR.
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time, so user can drive all the LED outputs to OFF state by setting the OE pin to
HIGH.
• When a LOW level is applied to OE pin, all the LED outputs are enabled.
• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCU9654
devices at the same time. When LED driver output state is set fully ON (LDRx = 01 in
LEDOUTx register) in these devices. This requires an external clock reference that
provides blinking period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated.
Consider disabling LED outputs using HIGH level applied to OE pin.
7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCU9654 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCU9654 registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
7.6 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the UFm I2C-bus to be
reset to the power-up state value through a specific formatted I2C-bus command.
The SWRST Call function is defined as the following:
1. A START command is sent by the UFm I2C-bus master.
2. The reserved SWRST I2C-bus address ‘0000 011’ with the W bit set to ‘0’ (write) is
sent by the I2C-bus master.
3. The PCU9654 device(s) is(are) recognized after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the W bit is set to ‘1’, no action is taken in PCU9654.
4. Once the SWRST Call address has been sent, the master sends 2 bytes with two
specific values (SWRST data byte 1 and byte 2): Byte 1 = A5h, Byte 2 = 5Ah.
If more than 2 bytes of data are sent, they will be ignored by the PCU9654.
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent, the
master sends a STOP command to end the SWRST Call: the PCU9654 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time (tBUF).
Remark: The reset stage is also the standby state with the internal oscillator turned off.
It takes 500 s for the oscillator to be up and running once the SLEEP bit has been set to
a logic 1. PWM registers should not be accessed within the 500 s window.
7.7 Individual brightness control with group dimming/blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 8 LED outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 40 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 2 × 40 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 40 ns = 10.24 μs
(97.6 kHz)
Group Dimming signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aab417
Minimum pulse width for LEDn Brightness Control is 40 ns.
Minimum pulse width for Group Dimming is 20.48 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of
the LED Brightness Control signal (pulse width = N  40 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).
Fig 6.
Brightness + Group Dimming signals
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
8. Characteristics of the UFm I2C-bus
The PCU9654 LED controller uses the new Ultra Fast-mode (UFm) I2C-bus to
communicate with the UFm I2C-bus capable host controller. It uses two lines for
communication. They are a serial data line (USDA) and a serial clock line (USCL). The
UFm is a unidirectional bus that is capable of higher frequency (up to 5 MHz). The UFm
I2C-bus slave devices operate in receive-only mode. That is, only I2C writes to PCU9654
are supported.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the USDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 7).
USDA
USCL
data line
stable;
data valid
Fig 7.
change
of data
allowed
002aaf113
Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8).
USDA
USCL
S
P
START condition
STOP condition
002aaf114
Fig 8.
PCU9654
Product data sheet
Definition of START and STOP conditions
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9).
USDA
MASTER UFm
TRANSMITTER
USCL
SLAVE UFm
RECEIVER
SLAVE UFm
RECEIVER
SLAVE UFm
RECEIVER
002aaf100
Fig 9.
System configuration
8.3 Data transfer
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one bit that is
always set to 1. The master generates an extra related clock pulse.
USDA data output by
master UFm transmitter
Master drives the line HIGH on the 9th clock cycle.
Slave never drives the USDA line.
USCL clock from master
1
2
8
9
S
START
condition
002aag325
Fig 10. Data transfer
PCU9654
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
9. Bus transactions
slave address
S
control register
0 A5 A4 A3 A2 A1 A0 0
START condition
1
W
this bit
always = 1
0
0
data for register D[7:0]
0 D4 D3 D2 D1 D0 1
Autoregister
Increment
address(1)
options
Auto-Increment flag
1
this bit
always = 1
P
this bit
always = 1
STOP
condition
002aag326
(1) See Table 4 for register definition.
Fig 11. Write to a specific register
slave address
S
control register
0 A5 A4 A3 A2 A1 A0 0
1
1
0
0
0
0
W
Auto-Increment
on all registers
this bit
always = 1
Auto-Increment on
START condition
SUBADR3 register
0
MODE1 register
0
0
MODE1
register
selection
MODE2 register
1
this bit
always = 1
1
1
this bit
always = 1
this bit
always = 1
(cont.)
ALLCALLADR register
(cont.)
1
1
this bit
always = 1
this bit
always = 1
P
STOP
condition
002aag327
Fig 12. Write to all registers using the Auto-Increment feature
slave address
S
control register
0 A5 A4 A3 A2 A1 A0 0
START condition
1
W
this bit
always = 1
1
0
1
0
0
increment
on Individual
brightness
registers only
0
PWM0 register
1
0
PWM0
register
selection
PWM1 register
1
this bit
always = 1
1
1
this bit
always = 1
this bit
always = 1
(cont.)
Auto-Increment on
PWM6 register
(cont.)
PWM7 register
PWM0 register
PWMx register
1
1
1
1
this bit
always = 1
this bit
always = 1
this bit
always = 1
this bit
always = 1
P
STOP
condition
002aag328
Fig 13. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
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NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
slave address(1)
sequence (A) S
new LED All Call I2C address(2)
control register
0 A5 A4 A3 A2 A1 A0 0
START condition
1
1
0
0
1
0
0
0
1
ALLCALLADR
register selection
W
this bit
always = 1
1
1
0
1
0
1
0
this bit
always = 1
1
0
1
P
this bit
always = 1
Auto-Increment on
STOP
condition
the LED[3:0] bits are ON at the ninth bit(3)
LED All Call I2C address
sequence (B) S
1
0
1
0
START condition
1
0
1
control register
0
1
1
0
W
this bit
always = 1
0
0
1
1
LEDOUT0 register (LED fully ON)
0
0
LEDOUT0
register selection
1
0
1
0
1
0
1
this bit
always = 1
0
1
1
P
this bit
always = 1
STOP
condition
002aag329
(1) In this example, several PCU9654s are used and the same sequence (A) (above) is sent to each of them.
(2) ALLCALL bit in MODE1 register is equal to 1 for this example.
(3) OCH bit in MODE2 register is equal to 1 for this example.
Fig 14. LED All Call UFm I2C-bus address programming and LED All Call sequence example
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NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
10. Application design-in information
up to 40 V
up to 40 V
VDD = 2.5 V, 3.3 V or 5.0 V
UFm I2C-BUS/
SMBus MASTER
10 kΩ(1)
VDD
USDA
USDA
LED0
USCL
USCL
LED1
LED2
OE
OE
LED3
PCU9654
A0
A1
A2
A3
A4
LED4
A5
LED5
LED6
VSS
LED7
VSS
002aag330
(1) OE requires pull-up resistor if control signal from the master is open-drain.
I2C-bus address = 0010 101x.
Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs
using HIGH level applied to OE pin.
Fig 15. Typical application
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
10.1 Junction temperature calculation
A device junction temperature can be calculated when the ambient temperature or the
case temperature is known.
When the ambient temperature is known, the junction temperature is calculated using
Equation 4 and the ambient temperature, junction to ambient thermal resistance and
power dissipation.
T j = T amb + R th  j-a   P tot
(4)
where:
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = junction to ambient thermal resistance
Ptot = (device) total power dissipation
When the case temperature is known, the junction temperature is calculated using
Equation 5 and the case temperature, junction to case thermal resistance and power
dissipation.
T j = T case + R th  j-c   P tot
(5)
where:
Tj = junction temperature
Tcase = case temperature
Rth(j-c) = junction to case thermal resistance
Ptot = (device) total power dissipation
Here are two examples regarding how to calculate the junction temperature using junction
to case and junction to ambient thermal resistance. In the first example (Section 10.1.1),
given the operating condition and the junction to ambient thermal resistance, the junction
temperature of PCU9654PW, in the TSSOP24 package, is calculated for a system
operating condition in 50 C1 ambient temperature. In the second example
(Section 10.1.2), based on a specific customer application requirement where only the
case temperature is known, applying the junction to case thermal resistance equation, the
junction temperature of the PCU9654, in the TSSOP24 package, is calculated.
1.
50 C is a typical temperature inside an enclosed system. The designers should feel free, as needed, to perform their own
calculation using the examples.
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PCU9654
NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
10.1.1 Example 1: Tj calculation of PCU9654PW, in TSSOP24 package, when Tamb
is known
Rth(j-a) = 108 C/W
Tamb = 50 C
LED output low voltage (LED VOL) = 0.5 V
LED output current per channel = 80 mA
Number of outputs = 8
IDD(max) = 10 mA
VDD(max) = 5.5 V
1. Find Ptot (device total power dissipation):
– output total power = 80 mA  8  0.5 V = 320 mW
– chip core power consumption = 10 mA  5.5 V = 55 mW
Ptot = (320 + 55) mW = 375 mW
2. Find Tj (junction temperature):
Tj = (Tamb + Rth(j-a)  Ptot) = (50 C + 108 C/W  375 mW) = 90.5 C
10.1.2 Example 2: Tj calculation where only Tcase is known
This example uses a customer’s specific application of the PCU9654, 8-channel LED
controller in the TSSOP24 package, where only the case temperature (Tcase) is known.
Tj = Tcase + Rth(j-c)  Ptot, where:
Rth(j-c) = 30 C/W
Tcase (measured) = 94.6 C
VOL of LED ~ 0.5 V
IDD(max) = 10 mA
VDD(max) = 5.5 V
LED output voltage LOW = 0.5 V
LED output current per channel = 80 mA
1. Find Ptot (device total power dissipation)
– Output total power = 80 mA  8  0.5 V = 320 mW
– chip core power consumption = 10 mA  5.5 V = 55 mW
Ptot (device total power dissipation) = 375 mW
2. Find Tj (junction temperature):
Tj = Tcase + Rth(j-a)  Ptot = 94.6 C + 30 C/W  375 mW = 105.85 C
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NXP Semiconductors
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
11. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS  0.5
5.5
V
Vdrv(LED)
LED driver voltage
VSS  0.5
40
V
IO(LEDn)
output current on pin LEDn
-
100
mA
800
-
mA
[1]
IOL(tot)
total LOW-level output current
LED driver outputs;
VOL = 0.5 V
ISS
ground supply current
per VSS pin
-
800
mA
Ptot
total power dissipation
Tamb = 25 C
-
1.8
W
Tamb = 85 C
-
0.72
W
Tamb = 25 C
-
100
mW
Tamb = 85 C
-
45
mW
-
+125
C
65
+150
C
40
+85
C
P/ch
power dissipation per channel
Tj
junction temperature
Tstg
storage temperature
Tamb
ambient temperature
[2]
operating
[1]
Each bit must be limited to a maximum of 100 mA and the total package limited to 800 mA due to internal
busing limits. The pull-up (current limiting) resistor must be of sufficient size (W) and value () to guarantee
that the 100 mA limit is not exceeded on any output.
[2]
Refer to Section 10.1 for calculation.
Table 14.
TSSOP24 power dissipation and output current capability
Measurement
TSSOP24
Tamb = 25 C
maximum power dissipation (chip + output drivers)
926 mW
maximum power dissipation (output drivers only)
851 mW
maximum drive current per channel
851 mW
 -------------------------------- = 212.75 mA [1]
8-bit  0.5 V
Tamb = 60 C
maximum power dissipation (chip + output drivers)
602 mW
maximum power dissipation (output drivers only)
527 mW
maximum drive current per channel
527 mW
 -------------------------------- = 131.8 mA [1]
8-bit  0.5 V
Tamb = 80 C
maximum power dissipation (chip + output drivers)
417 mW
maximum power dissipation (output drivers only)
342 mW
maximum drive current per channel
[1]
PCU9654
Product data sheet
342 mW
 -------------------------------- = 85.5 mA
8-bit  0.5 V
This value signifies package’s ability to handle more than 100 mA per output driver. The device’s maximum
current rating per output is 100 mA.
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
12. Thermal characteristics
Table 15.
Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
[1]
Parameter
Conditions
thermal resistance from junction to ambient
thermal resistance from junction to case
Typ
Unit
TSSOP24
[1]
108
C/W
TSSOP24
[1]
30
C/W
Calculated in accordance with JESD 51-7.
13. Static characteristics
Table 16. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply
VDD
supply voltage
2.3
-
5.5
V
IDD
supply current
on pin VDD; operating mode; no load;
fUSCL = 5 MHz; VDD = 5.5 V
-
5.5
10
mA
Istb
standby current
on pin VDD; no load; fUSCL = 0 Hz;
I/O = inputs; VI = VDD; VDD = 5.5 V
-
2.1
7
A
power-on reset voltage
no load; VI = VDD or VSS
-
1.70
2.0
V
0.5
-
+0.3VDD
V
VPOR
UFm
I2C-bus
[1]
inputs USCL and USDA
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
6
10
pF
LED driver outputs LED[7:0]
Vdrv(LED)
LED driver voltage
IOL
LOW-level output current
VOL = 0.5 V
ILOH
HIGH-level output leakage
current
Vdrv(LED) = 5 V
Vdrv(LED) = 40 V
[3]
output capacitance
Co
[2]
0
-
40
V
100
-
-
mA
-
-
1
A
-
1
15
A
-
15
40
pF
OE input
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
0.5
-
+0.3VDD
V
Address inputs A[5:0]
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
[1]
VDD must be lowered to 0.2 V in order to reset part.
[2]
Each bit must be limited to a maximum of 100 mA and the total package limited to 800 mA due to internal busing limits.
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
[3]
Tested with outputs off.
002aae510
0.35
VDD = 5.5 V
4.5 V
3.0 V
2.3 V
IOL
(A)
0.25
002aae511
0.25
VDD = 5.5 V
4.5 V
3.0 V
2.3 V
IOL
(A)
0.15
0.15
0.05
0.05
−0.05
−0.05
0.15
0.35
−0.05
−0.05
0.55
VOL (V)
a. Tamb = 40 C
0.15
0.35
0.55
VOL (V)
b. Tamb = 25 C
002aae512
0.25
IOL
(A)
VDD = 5.5 V
4.5 V
3.0 V
2.3 V
0.15
0.05
−0.05
−0.05
0.15
0.35
0.55
VOL (V)
c. Tamb = 85 C
Fig 16. VOL versus IOL
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14. Dynamic characteristics
Table 17.
Dynamic characteristics
Symbol
Parameter
fUSCL
Conditions
Min
Typ
Max
Unit
USCL clock frequency
-
-
5
MHz
tBUF
bus free time between a STOP and
START condition
0.08
-
-
s
tHD;STA
hold time (repeated) START condition
0.05
-
-
s
tSU;STA
set-up time for a repeated START
condition
0.05
-
-
s
tSU;STO
set-up time for STOP condition
0.05
-
-
s
tHD;DAT
data hold time
10
-
-
ns
tSU;DAT
data set-up time
30
-
-
ns
tLOW
LOW period of the USCL clock
0.05
-
-
s
tHIGH
HIGH period of the USCL clock
0.05
-
-
s
tf
fall time of both USDA and USCL signals
-
-
50
ns
tr
rise time of both USDA and USCL signals
-
-
50
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
-
10
ns
Output propagation delay
tPLH
LOW to HIGH propagation delay
OE to LEDn;
MODE2[1:0] = 01
-
-
150
ns
tPHL
HIGH to LOW propagation delay
OE to LEDn;
MODE2[1:0] = 01
-
-
150
ns
Output port timing[1][2]
td(USCL-Q)
delay time from USCL to data output
USCL to LEDn;
MODE2[3] = 1;
LEDOUTx = 01;
outputs change on
ninth clock cycle (USCL)
-
-
450
ns
td(USDA-Q)
delay time from USDA to data output
USDA to LEDn;
MODE2[3] = 0;
LEDOUTx = 01;
outputs change on
STOP condition
-
-
450
ns
[1]
From LED off to fully on, LED fully on to off, or LED individual brightness control to off.
[2]
For LED off state to on with individual brightness control or for changes in the individual brightness control value, there is a
synchronization that may take up to 15 s for the change to take effect.
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8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
0.7 × VDD
USDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
USCL
0.3 × VDD
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aag331
Fig 17. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
tLOW
bit 1
(D1)
bit 6
tHIGH
STOP
condition
(P)
(always set
to 1
by master)
bit 0
(D0)
9th
clock
1 / fUSCL
0.7 × VDD
0.3 × VDD
USCL
tBUF
tf
tr
tSU;STO
0.7 × VDD
0.3 × VDD
USDA
td(USCL-Q)
tHD;STA
tSU;DAT
tHD;DAT
output data
LED[0:7]
td(USDA-Q)
output data
LED[0:7]
002aag615
Rise and fall times refer to VIL and VIH.
Fig 18. UFm I2C-bus timing and output timing diagram
OE
tPLH
tPHL
output data
002aag604
Fig 19. Output propagation delay
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15. Test information
VDD
PULSE
GENERATOR
VI
VO
RL
500 Ω
VDD
open
GND
DUT
RT
CL
50 pF
002aab284
RL = Load resistor for LEDn.
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 20. Test circuitry for switching times
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16. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 21. Package outline SOT355-1 (TSSOP24)
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17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 18 and 19
Table 18.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 19.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Abbreviations
Table 20.
PCU9654
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
NMOS
Negative-channel Metal-Oxide Semiconductor
NPN
bipolar transistor with N-type emitter and collector and a P-type base
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal-Oxide Semiconductor
PNP
bipolar transistor with P-type emitter and collector and an N-type base
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
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20. Revision history
Table 21.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCU9654 v.1
20120702
Product data sheet
-
-
PCU9654
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21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCU9654
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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23. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 6
Regular UFm I2C-bus slave address . . . . . . . . 6
LED All Call UFm I2C-bus address. . . . . . . . . . 7
LED Sub Call UFm I2C-bus addresses. . . . . . . 7
Software Reset UFm I2C-bus address . . . . . . . 7
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register definitions . . . . . . . . . . . . . . . . . . . . . . 9
Mode register 1, MODE1 . . . . . . . . . . . . . . . . 10
Mode register 2, MODE2 . . . . . . . . . . . . . . . . 10
PWM0 to PWM7, individual brightness
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.3.4
GRPPWM, group duty cycle control . . . . . . . . 11
7.3.5
GRPFREQ, group frequency . . . . . . . . . . . . . 12
7.3.6
LEDOUT0 and LEDOUT1, LED driver
output state . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.3.7
SUBADR1 to SUBADR3, UFm I2C-bus
subaddress 1 to 3 . . . . . . . . . . . . . . . . . . . . . . 13
7.3.8
ALLCALLADR, LED All Call UFm I2C-bus
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.4
Active LOW output enable input . . . . . . . . . . . 14
7.5
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14
7.6
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 14
7.7
Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 15
8
Characteristics of the UFm I2C-bus . . . . . . . . 16
8.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1.1
START and STOP conditions . . . . . . . . . . . . . 16
8.2
System configuration . . . . . . . . . . . . . . . . . . . 17
8.3
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 18
10
Application design-in information . . . . . . . . . 20
10.1
Junction temperature calculation . . . . . . . . . . 21
10.1.1
Example 1: Tj calculation of PCU9654PW, in
TSSOP24 package, when Tamb is known . . . . 22
10.1.2
Example 2: Tj calculation where only Tcase is
known . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 23
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
21
21.1
21.2
21.3
21.4
22
23
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
26
28
29
30
30
30
30
30
31
32
33
34
34
34
34
35
35
36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 July 2012
Document identifier: PCU9654
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