AN1051

Application Note 1051
Design Consideration with AP3409/A
Prepared by Yong Wang
System Engineering Dept.
1. Introduction
programmable from 300kHz to 4MHz, which allows
small-sized components, such as capacitors and
inductors. A standard series of inductors from several
different manufacturers are available. This feature
greatly simplifies the design of switch-mode power
supplies.
The AP3409/A is a current mode, PWM synchronous
buck DC/DC converter, capable of driving a 3A load
with high efficiency, excellent line and load
regulation. It operates in continuous PWM mode.
The AP3409/A integrates synchronous P-channel and
N-channel power MOSFET switches with low
on-resistance. The reference voltage of the AP3409/A
is 0.8V. It is ideal for portable applications powered
from a single Li-ion battery. 100% duty cycle and
low on-resistance P-channel internal power MOSFET
can maximize the battery life.
2. Operation
The AP3409/A consists of a reference voltage
module, slope compensation circuit, error amplifier,
PWM comparator, current limit circuit, P-channel
and N-channel MOSFETs (used as a main switch and
synchronous switch respectively), etc. (Refer to
Figure 1 and Figure 2 for detailed information).
The switching frequency of AP3409/A can be
SHDN/RT
1
6, 7
CS
SD
COMP
Oscillator
10
PVDD
SUM
0.8V
EA
Driver
FB
9
Clamp
PWM
SS
OCP
3, 4
SW
Control
Logic
5
0.4V
PGND
DC
8
VDD
VREF
2
UVLO
OTP
GND
Figure 1. Functional Block Diagram of AP3409
Dec. 2010
Rev. 1. 2
BCD Semiconductor Manufacturing Limited
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Application Note 1051
SHDN/RT
1
6
CS
SD
COMP
SUM
Oscillator
10
PVDD
0.8V
FB
9
EA
Clamp
0.4V
SS
PWM
3, 4
OCP
SW
Control
Logic
0.725V
0.9V
5
PGND
DC
PGOOD
8
VREF
2
UVLO OTP
GND
7
VDD
Figure 2. Functional Block Diagram of AP3409A
When output short to ground, the system enters
HICCUP mode, shutting down the P-channel and
N-channel MOSFETs for a period about 2000T
(T=1/f). After that period, the AP3409/A will
implement softstart again. And this repeats until
released from short circuit status. After released from
short circuit status, the AP3409/A recovers into
normal operation.
2.1 Main Loop Control
At the beginning of each cycle initiated by the clock
signal (generated from the internal oscillator), the
P-channel MOSFET switch is turned on, and the
inductor current ramps up until the comparator
tripped and control logic turns off the switch. The
current limit comparator also turns off the switch in
case the current limit of the P-channel MOSFET is
exceeded. Then the N-channel synchronous switch is
turned on with the inductor current ramping down.
The next cycle is initiated by the clock signal again,
turning off the N-channel synchronous switch and
turning on P-channel switch (Refer to Figure 3, 4.).
2.3 Soft Start
The AP3409/A integrates an internal soft start circuit
to limit the inrush current during start-up. This
feature allows the output to smoothly climb up to the
rated output voltage, thus reducing start-up stresses
and current surges.
2.2 Short Circuit Protection
Dec. 2010
Rev. 1. 2
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Application Note 1051
AP3409
rd
Figure 3. Typical Application of AP3409
Figure 4. Typical Application of AP3409A
Dec. 2010
Rev. 1. 2
BCD Semiconductor Manufacturing Limited
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Application Note 1051
2.4 UVLO
If the UVLO threshold is not met, all functions of the
AP3409/A will be disabled, preventing the device
from damage by mis-operation at low input voltage.
It prevents the converter from turning on the main
switch and synchronous switch under undefined
condition.
3.1 Input Capacitor
Due to the discontinuous input current of the buck
converter, a bulk capacitor is required to keep the
input voltage constant. To ensure a stable operation,
the input capacitor should be placed as close to the
PVDD pin as possible, and its value varies according
to different load and different characteristics of input
impedance. With a typical value about 22µF for the
input capacitor, the X5R or X7R ceramic capacitor
are recommended due to their best temperature and
voltage characteristics.
2.5 Operation Frequency
The Operation frequency selection should be a
tradeoff between efficiency and component size.
High frequency allows the use of small-sized
inductor and small-valued capacitor while the low
frequency improves efficiency, however, requires
larger-valued inductor and/or capacitor to maintain
low output ripple voltage. The operation frequency of
AP3409/A can be determined via an external resistor,
connected between the RT pin and GND. The
operation frequency ranges from 0.3MHz to 4MHz
(Refer to Figure 5).
3.2 Output Capacitor
As a most critical component of a switching regulator,
the output capacitor is used for output filtering and
keeping the loop stable, and its typical value is
2×22µF. Two primary parameters of the output
capacitor are known as the voltage rating and the
Equivalent Series Resistance (ESR). The higher the
voltage rating, the smaller the ESR value will be. To
keep a small output voltage ripple, lower ESR value
should be selected. The output ripple can be
expressed as the following:
4.5
4.0
ROSC= 50kΩ for 4MHz
Frequency (MHz)
3.5
3.0
∆VOUT ≈ ∆I L × ( ESR +
2.5
ROSC= 330kΩ for 1MHz
2.0
1
)
8 × f × COUT
1.5
1.0
Where f is the switching frequency, COUT is the value
of output capacitor and ∆IL is the ripple current inside
the inductor.
ROSC= 1.2MΩ for 0.28MHz
0.5
0.0
0
200
400
600
800
1000
1200
ROSC (kΩ)
3.3 Inductor
The inductor is used to supply smooth current to the
output when driven by a switching voltage. The
higher the inductance, the lower the peak-to-peak
ripple current will be. As higher inductance usually
means larger inductor size, so some trade-offs should
be made when selecting an inductor. The AP3409/A
is a synchronous buck converter, and it always works
in Continuous Current Mode (CCM). The inductor
value can be expressed as the following:
Figure 5. Frequency vs. ROSC
2.6 Thermal Protection
If ≥ 160ºC junction temperature sensed by the
thermal protection circuit, the main switch and
synchronous switch will be turned off to prevent the
device from damaging. The thermal protection and
shutdown circuit has a 20ºC of system hysteresis,
which can prevent the converter from thermal
damage under some unexpected condition.
L = VOUT ×
2.7 Power Good Output Voltage Monitoring (Only
for AP3409A)
The PGOOD pin is open-drain logic output that is
pulled to ground when the output voltage is not
within ±12.5% of regulation point.
Where VOUT is the output voltage, VIN is the input
voltage, IOUT is the output current and k is the ripple
current coefficient, which is 20% to 40% typically.
Another important parameter is the current rating.
Exceeding an inductor's maximum current rating may
cause saturation and overheating to the inductor. If
3. Components Selection
Dec. 2010
VIN − VOUT
f × VIN × I OUT × k
Rev. 1. 2
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Application Note 1051
the
the output capacitor and the load resistor. These poles
are located at:
the inductor value is determined, peak inductor
current can be expressed as the following:
I PEAK = I OUT + VOUT
f P1 =
V −V OUT
× IN
2 × f × VIN × L
f P2 =
It should be ensured that the current rating of the
selected inductor is 1.5 times of IPEAK.
G EA
2π × C COMP × AVEA
1
2π × C OUT × RLOAD
3.4 Loop Compensation
The AP3409/A employs current mode control for
easy compensation and fast transient response. The
system stability and transient response are controlled
through COMP pin. The COMP is the output of the
internal transconductance error amplifier. A series
capacitor-resistor combination sets a pole-zero
combination to govern the characteristics of the
control system.
Where GEA is the error amplifier transconductance.
The system has one zero of importance, due to the
and
the
compensation
capacitor
(CCOMP)
compensation resistor (RCOMP). This zero is located
at:
Optimal loop compensation depends on the output
capacitor, inductor, load, compensation network and
also the device itself. For a stable system, the values
for the compensation network is shown in Table 1.
The system may have another zero of importance, if
the output capacitor has a large capacitance and/or a
high ESR value. The zero, due to the ESR and
capacitance of the output capacitor, is located at:
VIN/VOUT
(V)
3.3/2.5
5/2.5
3.3/1.8
5/1.8
3.3/1.2
R1
(kΩ)
510
510
300
300
120
RCOMP
(kΩ)
30
30
25
20
5
f Z1 =
CCOMP
(nF)
1
1
1
1
2.2
1
2π × C OUT × RESR
The goal of compensation design is to shape the
converter transfer function to get a desired loop gain.
The system crossover frequency where the feedback
loop has the unity gain is important. Lower crossover
frequencies result in slower line and load transient
responses, while higher crossover frequencies could
cause system instability. A good standard is to set the
crossover frequency below one-tenth of the switching
frequency.
If the VIN/VOUT value of desired solution are not
found from the table above, the loop transfer function
should be analyzed to optimize the loop
compensation.
To optimize the compensation components, the
following procedure can be used.
The DC gain of the voltage feedback loop is given
by:
1) Choose the compensation resistor (RCOMP) to set
the desired crossover frequency. A good standard is
to set the crossover frequency below one-tenth of the
switching frequency.
VFB
VOUT
Where VFB is the feedback voltage (0.8V), AVEA is
the error amplifier voltage gain, GCS is the current
sense transconductance and RLOAD is the load resistor
value.
Determine RCOMP by the following equation:
RCOMP <
The system has two poles of importance. One is due
to the compensation capacitor (CCOMP) and the output
resistor of the error amplifier, and the other is due to
Dec. 2010
2π × C COMP × RCOMP
f ESR =
Table 1. Compensation Value R-C Combination
AVDC = RLOAD × GCS × AVEA ×
1
2π × C OUT × 0.1 × f S × VOUT
G EA × GCS × VFB
Where fS is switch frequency.
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Application Note 1051
placed as close as possible to PVDD and PGND pin
respectively
2) Choose the compensation capacitor (CCOMP) to
achieve the desired phase margin. For applications
with typical inductor values, setting the compensation
zero (fZ1) below one-forth of the crossover frequency
provides sufficient phase margin.
The external feedback resistors shall be placed next
to the FB pin. The exposed pad on the bottom of the
IC must be connected to PGND and GND. The SW
node is with high frequency voltage swing and should
be kept within a small area. All sensitive small-signal
nodes, especially the FB pin, should be kept far away
from the SW node. An example of PCB layout is
illustrated in Figure 6.
Determine CCOMP by the following equation:
C COMP >
4
2π × RCOMP × f C
Where fC is crossover frequency.
3.5 Feedforward
A feedforward capacitor C1 must be added into the
circuit for better loop stability, and its typical value is
22pF. This capacitor adds a zero point to the loop to
increase its phase margin.
4. Layout Consideration
PCB layout is of great importance to the AP3409/A
performance. The high-current paths should be
placed close to the AP3409/A with copper or short,
direct and wide traces. Input capacitors should be
placed
Dec. 2010
Figure 6. AP3409 PCB Layout (Example)
Rev. 1. 2
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