Application Note 1074 Application Notes for AP3771 System Solution Prepared by Zhao Jing Jing System Engineering Dept. Regulation (PSR). AP3771 has the special technique to suppress the audio noise, internal line compensation to reduce the number of system components, fixed cable compensation to compensate the voltage drop on different output cable for achieving good CV regulation. 1. Introduction The AP3771 uses Pulse Frequency Modulation (PFM) method to realize Discontinuous Conduction Mode (DCM) operation for FLYBACK power supplies. The principle of PFM is different with that of Pulse Width Modulation (PWM), so the design of transformer is also different. The AP3771 can achieve low standby power less than 30mW. The AP3771 can provide accurate constant voltage, constant current (CV/CC) regulation by using Primary Side D2 T1 + C1 RST1 + R5 C2 D1 C3 Np + Ns D3 RST2 VCC CS Q1 GATE VO + C4 RDUMMY VO- Na RFB1 AP3771 C5 FB CPC GND RFB2 RLINE Rcs Figure 1. Typical Application Circuit of AP3771 for Adapter Figure 1 is AP3771 typical application circuit, which is a FLYBACK converter controlled by AP3771 with a 3-winding transformer---Primary winding (Np), Secondary winding (Ns) and Auxiliary winding (Na). The AP3771 senses the auxiliary winding feedback voltage at FB pin and obtains power supply at VCC pin. VSEC---The transient voltage of secondary VS---the sum of VO and forward voltage of rectification diode Ip---The primary side current Is ---The secondary side current IPK---Peak current of primary side IPKS---Peak current of secondary side tSW---The period of switching frequency tONP ---The time of primary side “ON” tONS ---The time of secondary side “ON” tOFF ---The discontinuous time tOFFS --- The time of secondary side “Off” Figure 2 is the typical operation waveforms of PFM controller. In this figure, a series of relative ideal operation waveforms are given to illustrate some parameters used in following design steps. And the nomenclature of the parameters in Figure 2 is illustrated. Vdri---A simplified driving signal of primary MOSFET Mar. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 1 Application Note 1074 tONP Vdri tSW IPK IP IPKS IS tONS VS VSEC tOFFS tOFF Figure 2. Operation Waveforms In order to achieve low standby power, AP3771 decreases the minimum operating voltage. In order to achieve the lower power loss performance, the startup resistor RST1+RST2 should be as high as possible on the premise of meeting turn on delay time requirement. The selection of dummy load resistor is a tradeoff between standby power and I-V Curve. 2. Five Aspects for System Design 1. 2. 3. 4. 5. Low Standby Power Design Switching Frequency Design Transformer and Power Devices Design Feedback Resistors Design Line Compensation Design 2.1 Low Standby Power Design 2.2 Switching Frequency Design VH=0.5V VCS_REF 1.4V VCPC fSW fSW 47.6kHz 20kHz IO 42%IO Figure 3. Relationship Between VCPC, fSW and IO at Constant Peak Current Mode Mar. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 2 Application Note 1074 Where, the fSW is the switching frequency. η is the efficiency of the system. When the peak current IPK is constant, the output power depends on the switching frequency fSW. fSW is linearly increased with load increasing. When the constant peak current is adopted, the voltage of CPC pin is increased linearly with load increasing. The maximum value of VCPC is equal to tONS 4 ⋅ VDD = ⋅ 3.5V = 1.75V t SW 8 (1) In AP3771, two-segmented peak current is used to realize audio noise suppression. The peak current is about 0.5V when IO>42%IOmax, and the peak current is about 0.5V/1.5 when IO<42%IOmax. The primary current ip(t), as shown in Figure 2, is sensed by a current sense resistor RCS. The power transferring from input to output is given by: PO = 1 2 ⋅ LP ⋅ I pk ⋅ f SW ⋅ η 2 (2) VLOAD VCPC VH=0.5V VCS_REF VL=0.5V/1.5 0.42хIO_MAX IO_MAX fSW 55kHz 52kHz fSW 23.1kHz 20kHz 3.85kHz 0.42хIO_MAX IO_MAX ISOURCE 2/3×I SOURCE 0.42хIO_MAX IO_MAX Figure 4. Relationship Between VCPC, fSW and IO at Variable Peak Current Mode So, the voltage of CPC pin (VCPC) and switching frequency (fSW) has a leap at about 42% of load. At the leap point, if the peak current is changed from 0.5V( high IPK) to 0.33V(low IPK), the voltage of CPC pin at low IPK will be increased to 1.5 times of VCPC at high IPK, and the switching frequency fSW at low IPK will be increased to 2.25 times of fSW at high IPK. So the range of load working in the audio frequency is suppressed. VCS_REF VH=0.5V VL=0.5V/1.5 39%IO 42%IO IO Figure 5. Hysteresis at Conversion Between Low IPK and High IPK Mar. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 3 Application Note 1074 For the primary side current, In order to avoid oscillation, a hysteresis is added at the conversion between low IPK and high IPK. Considering the relationship between audio noise and flux density of transformer, deltaB≤2500 gauss is better for audio noise suppression. t ONP = I pk ⋅ Lp (8) Vindc Where LP is the inductance of primary winding. Vindc is the rectified DC voltage of input. When Vindc is the minimum value, the maximum tONP can be obtained. So, The low limitation of maximum switching frequency is given by audio noise suppression. And the upper limit of the AP3771 can be up to 120kHz. But this is only the limit of the IC; the finally designed maximum switching frequency is determined by the tradeoff between the efficiency, mechanical dimensions and thermal performance. t ONP_MAX = I pk ⋅ Lp Vindc _ min (9) For the secondary side current, 2.3 Transformer and Power Devices Design In Constant Current operation of AP3771, the CC loop control function of AP3771 will keep a fixed proportion between D1 (in Figure 1) on-time tONS and D1 off-time tOFFS (in Figure 2) by discharging or charging a capacitor embedded in the IC. The fixed proportion is tONS 4 = tOFFS 4 t ONS = I pks ⋅ VS = VO + Vd , Vd is the forward voltage of secondary diode. For (10), in CV regulation, the VS is a constant voltage, so tONS is a constant value with different input voltage. (3) t ONS 1 ⋅ I pks ⋅ 2 t ONS + t OFFS In FLYBACK converter, when the primary transistor turns ON, the energy stored in the magnetizing inductance Lp. So the power transferring from the input to the output is given by, (4) NP ⋅ I pk NS tONS 1 NP 1 N ⋅ ⋅ I pk ⋅ = ⋅ P ⋅ I pk 2 NS tONS + tOFFS 4 N S (12) Here, Pin ' is input power of transformer, not including all of the power loss at primary side (Rectifier, RCD snubber, BJT and so on). (5) ηin is definition to the input efficiency of system, which is about 0.9. (6) Then, t SW = The maximum turn ratio of XFMR should be designed first, which is to ensure that the system should work in DCM in all working conditions, especially at the min. input voltage and full load. 2 L p ⋅ I pk (13) 2 ⋅ Pin ⋅ η in tSW, tONP and tONS in (7) are replaced with (13), (9) and (10), 2 Lp ⋅ I pk 2 ⋅ Pin ⋅ ηin As we know, if the system can meet equation (7) at minimum input voltage and full load, it can work in DCM under all working conditions. Mar. 2012 1 2 ⋅ L p ⋅ I pk ⋅ f SW 2 ' 2.3.1 Calculate the Max. turn ratio of XFMR (NMAX) tSW ≥ tONP + tONS (11) Pin = Thus the output constant-current is given by: IO = Pin = Pin ⋅ηin = Vin ⋅ I in ⋅ηin ' At the instant of D1 turn-on, the primary current transfers to the secondary at an amplitude of: I pks = (10) In (10), LS is the inductance of secondary winding. The relationship between the output constant-current and secondary peak current IPKS is given by: IO = LS VS ≥ I pks ⋅ Lp Ls + I pk ⋅ Vs Vindc_min (14) Because the peak current and inductance of primary side and secondary side have the following relationship, I pks = N ⋅ I pk ⋅ η i (7) Rev. 1. 0 (15) BCD Semiconductor Manufacturing Limited 4 Application Note 1074 Ls = using 1% tolerance resistors for RCS. After RCS is selected, IPK should be modified based on the selected RCS. Lp N 2 (16) From formula (23), the turn ratio of primary and secondary side N can be re-calculated. Here, N is the turn ratio of primary and secondary sides. ηi = 0.95 , which is the efficiency of IPK and IPKS. N= With (14), (15) and (16), then, I pk 1 ηi ≥ + 2 ⋅ Pin ⋅ηin VS ⋅ N Vin (17) VO ⋅ I O η The primary side inductance LP determines the stored energy. LP should be big enough to store enough energy, so that PO_Max can be obtained first, from the system version. (18) From formula (18), the output power can be given by, η is the system efficiency from input to output. PO = At full load, the system will work in the boundary of CC regulation. IO can be given by, IO = 1 t ONS ⋅ ⋅ I pks 2 t SW (19) LP = Np = The following can be obtained, k ⋅η ηi ) − 2 ⋅ VO ⋅ ηin ⋅ ηi VO + Vd (27) The turns of primary winding, (21) N ≤ N max = Vindc_min ⋅ ( 2 ⋅ PO ηin ⋅ I ⋅ f SW η 2 PK 2.3.4 Calculate the turns of primary, secondary and auxiliary In the design of AP3771, 2 ⋅ t SW =4 tONS LP ⋅ I PK LP ⋅ I PK ≥ Ae ⋅ ∆B Ae ⋅ B max As we know, 2.3.2 Calculate the peak current of primary side and current sensed resistor (IPK & RCS) NS = IPK can be calculated by the output current. And the turns of auxiliary winding, I pks N = k ⋅ IO N NA = (23) In AP3771, 0.5V is an internal reference voltage. If the sensed voltage VCS reaches 0.5V, the power MOSFET will be shut down and tONP will be ended. 0.5V I pk NP N N S ⋅ VA VS (29) (30) Where, VS is equal to VO+Vd. VA=VCC+ Vda, VCC is the set IC supply voltage and Vda is the voltage drop of the auxiliary diode. Here, k=4, η i = 0.9 , which is the efficiency of IPK and IPKS. RCS = (28) First, the reasonable core-type and ∆B should be selected. Ae can be gotten automatically after core-type is selected. (22) Then N is fixed as less than or equal to NMAX. I pk ⋅η i = (26) Then, LP can be gotten by, (20) I pks = k ⋅ I O 1 η ⋅ L p ⋅ I 2pk ⋅ f SW ⋅ 2 η in Where fSW was set by the user based on definite requirement. Then, IPKS can be defined, k= (25) 2.3.3 Calculate the inductance of primary side---LP Because, Pin = k ⋅ IO (k = 4 ) I pk ⋅ η i For AP3771, the typical value of UVLO is decreased to 6.5V, so the supply voltage of IC，VCC can be set to a typical value---13V. (24) 2.3.5 Check the maximum duty cycle of primary side So RCS can be obtained from (24) and selected with a real value from the standard resistor series. We recommend Mar. 2012 After turn ratio of primary side and secondary side is Rev. 1. 0 BCD Semiconductor Manufacturing Limited 5 Application Note 1074 ηi k ⋅η − ) = 13.96 2 ⋅ VO ⋅ ηin ⋅ η i VO + Vd designed, the maximum duty cycle of primary side at low line voltage can be calculated again. N MAX = Vindc_min ⋅ ( Considering the Volt-second balance between magnetizing and de-magnetizing, the formula of duty cycle is Vindc_min = Vinac_min ⋅ 2 − 40 , We choose N=11 (V + V ) ⋅ N ⋅ 0.5 D= O d Vindc (31) 2) Calculate the peak current of primary side and current sense resistor (IPK & RCS) 2.3.6 Select diodes of secondary and auxiliary sides Maximum reverse voltage of secondary side， Vdr = VS + Vindc_max ⋅ N S I pk = (32) NP RCS = Maximum reverse voltage of auxiliary side, Vdar = V A + Vindc_max ⋅ N A I pks N ⋅ηi = Vcs _ ref I pk k ⋅ IO = 0.638 N ⋅ηi (36) (37) = 0.846 We choose (33) NP R CS = 0.85Ω, (38) (39) In (32) and (33), the maximum DC input voltage should be used. I PK = 0.64A, 2.3.7 Select the primary side MOSFET 3) Calculate the inductance of primary side---LP Vdc_max = Vdc_spike + Vindc_max + (35) VS ⋅ N P NS (34) LP = 2 ⋅ PO ηin ⋅ = 1.15mH I ⋅ f SW η 2 PK (40) Be careful that the value of Vdc_spike will be different with different snubber circuit. We choose Lp=1.15mH Design Example 1 (for 12V/1A Adapter Application) 4) Calculate the turns of primary, secondary and auxiliary sides (NP, NS, NA) Specification: Input voltage: 90VAC to 264VAC Output voltage @ cable: VO_CABLE=12V Output current: IO=1A Output voltage @ PCB, VO=12.3V (with 1.8m AWG24 cable) k=2* TSW/TONS=4 Efficiency: ηi = 0.9 Np = LP ⋅ I PK LP ⋅ I PK ≥ = 109.43 Ae ⋅ ∆B Ae ⋅ B max N p = 110 Ns = NA = Other setting by users: Switching frequency: fSW=60kHz Forward voltage of secondary diode: Vd=0.4V Forward voltage of auxiliary diode: Vda=1.1V VCC voltage: VCC=18V Core_type: EE19/16 (Ae=22.4mm2), Bmax<3000GS Vdc_SPIKE =50V (with snubber circuit) = 10 (42) N S ⋅V A = 15 VS (43) N 5) Check the maximum duty cycle of primary side The maximum duty cycle of primary side is calculated as following, D= Design Steps: (VO + Vd ) ⋅ N ⋅ 0.4 = 0.55 Vindc (44) 6) Select diodes of secondary and auxiliary sides Maximum reverse voltage of secondary and auxiliary side， 1) Calculate the maximum turn ratio of XFMR Mar. 2012 Np (41) Rev. 1. 0 BCD Semiconductor Manufacturing Limited 6 Application Note 1074 Vdr = VS + Vindc_max ⋅ N S (45) NP Vindc_m ax = 265V ⋅ 2 Vdr = VS + Vindc_max ⋅ N S NP Vdar = V A + NP = 70V (48) 7) Select primary side MOSFET (46) = 47V Vindc_max ⋅ N A Vds_mos = Vdc_spike + Vindc_max + (47) VS ⋅ N P = 564V NS (49) Design Results Summary: 1.Calculate the maximum peak current of primary side and RCS IPK= 640 mA Peak current of primary side RCS= 0.85 Current sensed resistor Ω 2.Design transformer LP= 1.15 mH Inductance of primary side N= 11 Turn ratio of primary and secondary NP= 110 T Turns of primary side NS= 10 T Turns of secondary side N A= 15 T Turns of auxiliary side DMAX 0.55 Maximum duty cycle of primary side at VINDC=80V 3. Select diode and primary transistor Vdr= 47 V Maximum reverse voltage of secondary diode Vdar= 70 V Maximum reverse voltage of auxiliary diode VdcMax= 564 V Voltage stress of primary transistor ηi k ⋅η − ) = 14.05 2 ⋅ VO ⋅ ηin ⋅ ηi VO + Vd Design Example 2 (for 12V/1.5A Adapter Application) N MAX = Vindc_min ⋅ ( Specification: Input voltage: 90VAC to 264VAC Output voltage @ cable: VO_CABLE=12V Output current: IO=1.5A Output voltage @ PCB, VO=12.24V (with 1.5m AWG22 cable) k=2*TSW/TONS=4 Efficiency: η = 0.75 , ηin = 0.9 , ηi = 0.9 Vindc_min = Vinac_min ⋅ 2 − 40 , We choose N=10 2) Calculate the peak current of primary side and current sense resistor (IPK & RCS) I pk = Other setting by users: Switching frequency: fSW=50kHz Forward voltage of secondary diode: Vd=0.4V Forward voltage of auxiliary diode: Vda=1.1V VCC voltage: VCC=14V Core_type: EE20 (Ae=31mm2), Bmax<3000GS Vdc_SPIKE=50V (with snubber circuit) RCS = I pks N ⋅ηi = Vcs _ ref I pk k ⋅ IO = 0.97 N ⋅ηi = 0.56 We choose R CS = 0.56Ω, (53) I PK = 0.97A, (54) 3) Calculate the inductance of primary side---LP Calculate the maximum turn ratio of XFMR Mar. 2012 (51) (52) Design Steps: 1) (50) Rev. 1. 0 BCD Semiconductor Manufacturing Limited 7 Application Note 1074 LP = 2 ⋅ PO ηin ⋅ = 0.89mH I ⋅ f SW η (55) 2 PK D= (VO + Vd ) ⋅ N ⋅ 0.4 = 0.48 Vindc We choose Lp=0.9mH. 6) Select diodes of secondary and auxiliary sides 4) Calculate the turns of primary, secondary and auxiliary sides (NP, NS, NA) Vdr = VS + LP ⋅ I PK LP ⋅ I PK ≥ = 92.9 Ae ⋅ ∆B Ae ⋅ B max N p = 100 (56) Vindc_max = 265V ⋅ 2 (57) Vdr = VS + (58) Vdar = V A + Np = Ns = NA = Np N = 10 N S ⋅VA = 12 VS 5) Check the maximum duty cycle of primary side Vindc_max ⋅ N S (60) NP Vindc_max ⋅ N S NP Vindc_max ⋅ N A NP (59) (61) = 50V = 60V (62) (63) 7) Select primary side MOSFET The maximum duty cycle of primary side is calculated as following, Vds_mos = Vdc_spike + Vindc_max + VS ⋅ N P = 550V NS (64) Design Results Summary: 1.Calculate the maximum peak current of primary side and RCS IPK= 970 mA Peak current of primary side RCS= 0.56 Current sensed resistor Ω 2.Design transformer LP= 0.9 mH Inductance of primary side N= 10 Turn ratio of primary and secondary NP= 100 T Turns of primary side NS= 10 T Turns of secondary side N A= 12 T Turns of auxiliary side DMAX 0.48 Maximum duty cycle of primary side at VINDC=80V 3. Select diode and primary transistor Vdr= 50 V Maximum reverse voltage of secondary diode Vdar= 60 V Maximum reverse voltage of auxiliary diode VdcMax= 550 V Voltage stress of primary transistor Mar. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 8 Application Note 1074 2.4 Feedback Resistors Design Figure 6. Feedback Resistors Circuit From above Figure 6, (R + RFB 2 ) N S Vo = VFB ⋅ FB1 ⋅ − VD RFB 2 NA 2.5 Line Compensation Design The internal line compensation function in AP3771 is shown in Figure 7. S1 is closed when the primary switch is “ON”. The line voltage can be detected from the FB pin. The detected voltage internally compensates the peak current. So the line compensation is determined by RLINE. In different application, the value of RLINE is different. (65) Through adjusting RFB1 and R FB2, a suitable output voltage can be achieved. The recommended values of RFB1 and R FB2 are within 5kΩ to 50kΩ. Figure 7. Line Compensation Circuit Mar. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 9 Application Note 1074 tSW FB tONP t VN tOFF Figure 8. Waveform of FB Pin So, RLINE can be adjusted to achieve excellent line regulation of output current. The negative voltage VN of FB pin (in Figure 8) is linear to line voltage. The AP3771 samples VN to realize the line compensation. N RFB 2 VN = ⋅ a ⋅ Vindc RFB1 + RFB 2 N p 3. Summary In order to get good performance of AP3771, it’s important to design transformer, line compensation and feedback resistance correctly. This application only gives a preliminary design guideline about these aspects and considers ideal conditions, so some parameters need to be adjusted slightly on the basis of the calculated results. (66) The compensated voltage of line compensation (VCS_LINE) can be calculated by the following formula, 1 ⋅ VN 670k N RFB 2 1 = Rline ⋅ 0.8 ⋅ ⋅ ⋅ a ⋅ Vindc 670k RFB1 + RFB 2 N p Vcs _ line = Rline ⋅ K ⋅ Mar. 2012 (67) Rev. 1. 0 BCD Semiconductor Manufacturing Limited 10

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