AN1088

Application Note 1088
Application Notes for AP3775 System Solution
Prepared by Ding Xuezheng
System Engineering Dept.
1. Introduction
compensation and cable compensation to reduce the
number of external system components. Fixed cable
compensation is used in different IC versions to adapt the
different voltage drop on output cable and good CV
regulation is achieved. Besides, audio noise is reduced by
the creative audio suppression technique.
The AP3775 is an innovative Sub-5mW standby power
solution from BCD semiconductor. Combined with the
AP4341, the AP3775 power solution can achieve the less
5mW standby power, tight constant voltage regulation and
good dynamic performance.
The AP3775 is designed for driving bipolar transistor in
Flyback converter, which uses Pulse Frequency
Modulation (PFM) method to realize Discontinuous
Conduction Mode (DCM) operation for Flyback power
supplies.
As to BCD zero Watt standby power solution, there is a
secondary controller the AP4341 (IC2) to keep the light
load voltage regulation and improve dynamic performance.
The AP3775 solution can apply into 5.0V output voltage
Charger/Adapter system which has ultra low standby
power requirement.
The AP3775 can provide accurate constant voltage (CV),
constant current (CC) regulation with Primary Side
Regulation (PSR) structure. It uses internal line
Figure 1. Typical Application Circuit of AP3775
Figure 1 is the typical application circuit of the AP3775,
which is a conventional Flyback converter with a
3-winding transformer---primary winding (NP), secondary
winding (NS) and auxiliary winding (NA). The auxiliary
winding is used for providing VCC supply voltage for IC
and sensing the output voltage feedback signal to FB pin.
Nov. 2012
Figure 2 shows the typical waveforms which demonstrate
the basic operating principle of AP3775 application. And
the parameters are defined as following.
Idri---The driving signal of primary power switch
Ip---The primary side current
Is ---The secondary side current
IPK---Peak value of primary side current
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Application Note 1088
IPKS---Peak value of secondary side current
VSEC---The transient voltage at secondary winding
VS---The stable voltage at secondary winding when
rectification diode is in conducting status, which equals the
sum of output voltage VOUT and the forward voltage drop
of diode
VAUX---The transient voltage at auxiliary winding
VA---The stable voltage at auxiliary winding when
rectification diode is in conducting status, which equals the
sum of voltage VCC and the forward voltage drop of
auxiliary diode
tSW ---The period of switching frequency
tONP---The conduction time when primary side switch is
“ON”
tONS---The conduction time when secondary side diode is
“ON”
tOFF---The dead time when neither primary side switch nor
secondary side diode is “ON”
tOFFS---The time when secondary side diode is “OFF”
tSW
I dri
IPK
IP
IPKS
tOFFS
IS
VA
VAUX
VS
VSEC
tONP
tONS
tOFF
Figure 2. Operation Waveforms of Flyback PSR Control System
LL Mode Operation at Light Load
At no load and light load, the AP3775 works in Low Light
mode (LL mode) and the output voltage is detected by
AP4341. In order to achieve ultra low standby power, in
LL mode, the static current (ICC_NL) of the AP3775 is
reduced from 250µA to 100µA, current reference VCS is
high to reduce switching frequency.
•
The conditions of exiting LL mode---VCPC ≥90mV or
tOFF<tDELAY+30µs.
•
The conditions of entering LL mode---VCPC<60mV
and tOFF≥tDELAY+30µs.
In LL mode, when the AP4341 detects the output voltage is
lower than its trigger voltage, the AP4341 OUT pin emits a
periodical pulse current. This pulse current will generate a
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pulse voltage on feedback winding through the transformer
coupling. When the AP3775 detects this VPULSE (>100mV
is valid), primary switch immediately turns on to provide
one energy pulse to supply output terminal and primary
VCC.
To achieve low standby power, the lower switching
frequency is necessary. But if the off time is too long, the
VCC voltage will reduce to very low level. To avoid VCC
being lower than UVLO, a minimum switching frequency
is specified by the AP4341 (tDIS). If VO can’t be lower than
trigger voltage within tDIS, AP4341 OUT pin will emit the
periodical pulse current and let the primary switch turn on.
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Application Note 1088
No Load Operation Mode 1
When the transferred energy of one switching pulse can
charge the output voltage VO≥VDIS, the AP4341 will enable
a 1mA current to discharge the output voltage, and the
power system switching period will be the discharge time
of the AP4341. Because the discharge current at no load is
very small, the output voltage decreases from VDIS to VTRI
very slowly. As the above mentioned, if VO doesn’t
decrease to VTRI within TDIS, the primary switch will turn
on again. The detailed operation waveform is shown in
Figure 3.
Figure 3. No Load Operation Waveforms Mode 1
No Load Operation Mode 2
When the transferred energy of one switching pulse can’t
charge the output voltage VO≥VDIS, then the 1mA discharge
current will not be enabled. The output voltage will be
discharge to be lower than the trigger voltage of the
AP4341 within the discharge time. That means the off time
will be smaller than the discharge time tDIS of the AP4341,
as shown in Figure 4.
VO
VDIS
VTRI
VFB
tSW<tDIS
IDIS
0mA
Figure 4. No Load Operation Waveforms Mode 2
Dynamic Response Function_Undershoot
When output load changes from light load to heavy load,
the output voltage will decrease. Once the AP4341 detects
VO is lower than VTRI, a pulse current IPULSE will generate.
And VPULSE is generated on feedback winding through the
transformer coupling due to IPULSE. When the AP3775
detects VPULSE (>90mV is valid), primary switch is “ON”.
VPULSE will be valid again after a delay time (tD), which is
determined by the AP3775.
AP3775
working
Figure 5. Undershoot Response Waveform
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Dynamic Response Function_Overshoot
When output load changes from heavy load to light load,
the output voltage will rise. When the AP4341 detects VO
is higher than VOVP, and the off time of the AP3775 (tOFF)
is longer than 2ms, a 60mA discharge current will be
enabled from VCC pin of the AP4341. Thus the output
voltage will fall fast. Once the voltage is lower than VOVP,
the 60mA discharge current will stop. Then output voltage
falls slowly. When tOFF≥80ms and VO≥VDIS, 1mA is used
to discharge the output voltage.
Figure 6. Overshoot Response Waveform
2. Guideline of System Design
1. Low Standby Power Design
2. Switching Frequency Design
3. Transformer and Power Devices Design
4. Feedback Resistors Design
5. Line Compensation Design
6. Cable Compensation Design
The AP4341 (IC2) is used to detect the output voltage and
decide the no load operating frequency. Thus, the output
voltage regulation will keep within ±5% at the whole of
line and load condition. The power loss of this secondary
controller is,
(3)
PU 2 = V o × I IC 2
2.1 Low Standby Power Design
In order to achieve low standby power, the AP3775
decreases the minimum operating frequency and operating
current ICC_NL. The power loss of the AP3775 is,
PU 1 = V CC × I CC
Where VO is output voltage and is used as the supplier of
the AP4341; IIC2 is operating current of the AP4341.
2.2 Switching Frequency Design
(1)
_ NL
As we know, in DCM Flyback converter, the stored energy
of primary side will be transferred to secondary side at the
time when the primary switch is turned off. And assume
the current transfer efficiency from primary to secondary
is ηi , then
Generally, the resistor startup circuit takes the considerable
power loss at no load condition since of the lower startup
resistance to guarantee the shorter startup time. The
AP3775 solution uses the innovative zero power
dissipation startup circuit. The AP3775 uses BJT Q1’s
current amplifying function, which the startup current will
be amplified to over ten times, so that the startup resistors
R3+R4 value can be increased to high enough. The loss of
startup resistors is,
PSTART = (Vindc _ nor − VTH _ ST ) /( R3 + R 4)
2
Ipks = Ipk ⋅ N PS ⋅ ηi
Here, NPS is the turn ratio of primary winding to secondary
winding.
It is obvious that the output current IO is the average
current of secondary side IS,
(2)
Where VTH_ST is the Startup Threshold of VCC, Vindc_nor is
the rectified DC voltage from the nominal AC input
voltage.
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(4)
Io =
Rev. 1. 0
t
1
Ipks ⋅ ONS
2
t SW
(5)
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Application Note 1088
Then,
Io =
PO = VO ⋅ I O =
t
1
Ipk ⋅ N PS ⋅ η i ⋅ ONS
2
t SW
(6)
t ONS
t SW
(9)
Where, fSW is the switching frequency. So,
f SW
2 ⋅ VO
=
2
IO
LP ⋅ I pk ⋅ηT
Always voltage of CPC pin (VCPC) is determined by,
Vcpc = VDD ⋅
1
2
⋅ LP ⋅ I pk ⋅ f SW ⋅ ηT
2
(10)
(7)
When voltage at the sense resistor reaches the reference
voltage set by the AP3775, the switch will be turned off
and primary current reaches its maximum value,
Here VDD is a constant voltage generated by IC. Then,
2 ⋅ VDD
Vcpc
=
IO
N PS ⋅ η i ⋅ I PK
(8)
I PK =
Vcs _ ref
(11)
Rcs
If ηT is efficiency of power transmission from transformer
primary to the output, then
When the constant reference VCS_REF is used, the peak
current IPK is constant. From formula (8) and (10), it is
obvious that VCPC and fSW increase linearly with the
output current IO.
VH=0.45V
VCS_REF
1.55V
VCPC
fSW
fSW
55kHz
20kHz
IO
42%IO
Figure 7. Relationship between VCPC, fSW and IO at Constant Peak Current Mode
IO>=42%*IO_MAX and is decreased to 0.45V/1.5 when
IO<42%* IO_MAX, as follows in Figure 8.
In the AP3775, in order to realize audio noise suppression,
two-segmented of current reference voltage VCS_REF is used
except LL mode. The reference is about 0.45V when
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Application Note 1088
AP3775
Figure 8. Relationship between VCPC, fSW and IO at Variable Peak Current Mode
Then from formula (8) and (10), we can see the VCPC and
fSW both has a leap at about 42% of maximum load. At the
leap point, if the peak current is decreased by 1.5 times, the
voltage of CPC pin at low IPK will be increased to 1.5 times,
and the switching frequency fSW at low IPK will be
increased to 1.52 times. So the load range in audio is
largely narrowed.
VCS_REF
VH=0.45V
VL=0.45V/1.5
36%IO
42%IO
IO
Figure 9. Hysteresis at Conversion between Low IPK and High IPK
In order to avoid unstable operation, a hysteresis is added
at the conversion between low IPK and high IPK.
Considering the relationship between audio noise and flux
density of transformer, deltaB≤2500 gauss is better for
audio noise suppression.
given by audio noise suppression. And the upper limit of
the AP3775 can be up to 120kHz. But this is only the limit
of the IC; the finally designed maximum switching
frequency is determined by the tradeoff between the
efficiency,
mechanical
dimensions
and
thermal
performance.
The low limitation of maximum switching frequency is
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Application Note 1088
capacitance of primary switch. Then some margin is added
to tons as,
2.3 Transformer and Power Devices Design
In the design of AP3775, constant current control function
will keep a fixed proportion between on-time tONS and
off-time tOFFS of rectifier D1 (in Figure 1) by discharging or
charging a capacitor embedded in the IC. The fixed
proportion is,
t ONS 4
=
t SW 9
tONS = I pks ⋅
(19)
From formula (4) and formula (14), we can get,
Vs ⋅ Io =
2 ⋅ t SW
= 4.5
t ONS
(13)
=
1
1
⋅ I PKS = ⋅ N PS ⋅ ηi ⋅ I PK
k
k
1
⋅ Lp ⋅ Ipk 2 ⋅ fsw ⋅ηi 2
2
Then,
(14)
t SW =
2.3.1 Calculate Turn Ratio of Transformer (NPS)
The turn ratio of transformer should be designed first,
which ensures the power converter operating in DCM
within the whole conditions,
tSW ≥ tONP + tONS
1
1 Lp
⋅ Ls ⋅ Ipks 2 ⋅ fsw = ⋅
⋅ ( Ipk ⋅ N PS ⋅ηi ) 2 ⋅ fsw
2
2 N PS 2
(20)
Then the output constant-current value IO is,
IO =
(18)
VS = VO + Vd
(12)
It is assumed,
k=
LS
⋅ 1. 1
VS
2
L p ⋅ I pk
⋅ ηi
2
(21)
2 ⋅ VS ⋅ I O
tONP, tONS and tSW in (15) are replaced with (16), (18) and
(21), then
2
Lp ⋅ I pk
⋅ ηi
(15)
2 ⋅ VS ⋅ I O
2
≥ I pks ⋅
Lp
Ls
⋅ 1.1 + I pk ⋅
Vs
Vindc_min
(22)
As we know, if equation (13) is met at minimum input
voltage and full load, it can ensure that the power converter
operates in DCM in all conditions.
Relationship between inductance of primary side and
secondary side is,
For the primary side current,
Ls =
t ONP = I pk ⋅
Lp
Vindc
When Vindc is the minimum value, the maximum tONP can
be obtained. So,
Vindc _ min
Vindc _ min ⋅η i ⎛ k
⎞
⋅ ⎜ − 1.1⎟
VS
⎝2
⎠
(24)
Then designed turns ratio NPS should be no more than
NPS_MAX defined in formula (24).
(17)
2.3.2 Check stress voltage of primary side switch and
reverse voltage of secondary diode
For the secondary side current, LS is the inductance of
secondary winding, Vd is the forward voltage of secondary
diode.
If NPS is fixed by customer according in design step 2.3.1,
real stress voltage of primary side switch and reverse
voltage of secondary diode can be calculated.
There is an oscillating signal on FB waveform after
secondary Schottky diode current decrease to zero, which
is caused by primary inductance and equivalent output
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(23)
2
N PS ≤ N PS _ MAX =
Vindc is the rectified DC voltage of input.
Lp
N PS
At full load, the system will work in the boundary of CC
regulation. IO can be given by formula (14),the following
can be obtained,
(16)
Where LP is the inductance of primary winding.
t ONP_MAX = I pk ⋅
Lp
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The maximum stress voltage of primary side switch is,
Vds _ switch = Vdc_spike + Vindc_max
V ⋅ NP
+ S
NS
PS = VS ⋅ I O =
Where, fSW was set by the user based on definite
requirement. Then, LP can be gotten by,
LP =
Maximum reverse voltage of secondary side,
Vindc_max ⋅ N S
NP
Np =
NS =
(31)
NP
N PS
(32)
Turns of auxiliary winding is,
(27)
NA =
N S ⋅ VA
VS
(33)
2.3.6 Check the maximum duty cycle of primary side
Vcs _ ref
I pk
LP ⋅ I PK
LP ⋅ I PK
≥
Ae ⋅ ∆B Ae ⋅ B max
As NPS and NP are fixed, we can get NS by,
In the AP3775, 0.45V is an internal reference voltage. If
the sensed voltage VCS_REF reaches 0.45V, the power switch
will shut down and tONP will be ended.
RCS =
(30)
The turns of primary winding,
2.3.3 Calculate the peak current of primary side and
current sensed resistor (IPK & RCS)
IPK can be calculated by the output current.
k ⋅ IO
N PS ⋅ ηi
2 ⋅ PS
1
⋅ 2
I ⋅ f SW ηi
2
PK
2.3.5 Calculate the turns of primary, secondary and
auxiliary (NP, NS, NA)
(26)
For Flyback converter design, higher turns ratio NPS brings
higher stress voltage of primary side switch, higher
transforming efficiency, and the lower reverse voltage of
secondary diode. Finally, in design of turns ratio NPS and
NPA, formula (24), (25), (26), should be totally considered.
I pk =
(29)
(25)
Be careful that the value of Vdc_spike is determined by the
snubber circuit design.
Vdr = VS +
1
2
2
⋅ L p ⋅ I pk
⋅ f SW ⋅ ηi
2
After turn ratio of primary side and secondary side is
designed, the maximum duty cycle of primary side at low
line voltage can be calculated again.
(28)
So RCS can be obtained and selected with a real value from
the standard resistor series. We recommended using 1%
tolerance resistors for RCS. After RCS is selected, IPK should
be modified based on the selected RCS.
Considering the Volt-second balance between magnetizing
and de-magnetizing, the formula of duty cycle is,
D max =
(VO + Vd ) ⋅ N t ons
⋅
Vindc ⋅ ηi
t sw
(34)
2.3.4 Calculate the inductance of primary side---LP
The primary side inductance LP is relative with the stored
energy. LP should be big enough to store enough energy, so
that PO_MAX can be obtained from this system.
2.3.7 Check reverse voltage of auxiliary diode
If NP and NA are fixed according in design step 2.3.5, real
reverse voltage of auxiliary diode can be calculated by
formulas (26).
According to formula (20), the output power can be given
by,
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Application Note 1088
2.4 Feedback Resistors Design
VD
VIN
NP
VO
NS
NA
RFB1
Q
FB
VFB
OUT
RFB2
Figure 10. Feedback Resistors Circuit
From above Figure 10,
Vo = VFB ⋅
RFB2 are within 5kΩ to 100kΩ.
(R FB1 + R FB 2 ) N S
⋅
− VD
R FB 2
NA
2.5 Line Compensation Design
(35)
R FB1 Vo + VD
=
⋅ NA −1
RFB 2 N S ⋅ VFB
The internal line compensation function in the AP3775 is
shown in Figure 11. S1 is closed when the primary switch
is “ON”. The line voltage can be detected from the FB pin.
The detected voltage internally compensates the peak
current. So the line compensation is determined by RLINE.
In different applications, the value of RLINE is different.
(36)
Through adjusting RFB1 and RFB2, a suitable output voltage
can be achieved. The recommended values of RFB1 and
VAUX
VDD
tONP
RFB1
gm
OUT
S1
FB
RFB2
RLINE
RCS
ILINE
VCS
Figure 11. Line Compensation Circuit
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Application Note 1088
Figure 12. Waveform of FB Pin
there is a total voltage increase of 6% at VFB when the
output is at full load (IOUT_MAX). And if the output is at
10%*IOUT_MAX, the increase voltage of VFB is 0.6%. Proper
version of IC can be chosen according to the resistance of
the output cable.
The negative voltage VN of FB pin (in Figure12) is linear
to line voltage. The AP3775 samples VN to realize the line
compensation.
VN = Vindc ⋅
NA
R FB 2
⋅
N P R FB1 + R FB 2
(37)
CABLE COMPENSATION SECTION
Cable
AP3775
VFB
Compensation
AP3775B
_CABLE/VFB %
Voltage
The compensated voltage of line compensation (VCS_LINE)
can be calculated by the following formula,
VCS _ LINE = Vin _ DC ⋅
NA
RFB 2
⋅
⋅ g m ⋅ RLINE
N P RFB1 + RFB 2
(38)
tdelay
LP
∆VFB % =
t delay
Lp
⋅ Rcs ) /(
∆VOUT _ CABLE = ∆VFB % ⋅ VFB ⋅
NA
RFB 2
⋅
⋅ gm )
N P RFB1 + RFB 2
(41)
VFB
Then from Figure 8,
Then RLINE can be adjusted to achieve excellent line
regulation of output current.
RLINE = (
∆VFB _ CABLE
(39)
⋅ Rcs
3 4 5 %
Assume,
This is designed to compensate the additional voltage of
VCS introduced by tdelay, which is the delay time of internal
drivers of IC and primary side switch.
Vdelta = Vindc ⋅
5 6 7 %
RFB1 + RFB 2 N S
⋅
= I O _ MAX ⋅ RCABLE
RFB 2
NA
(42)
Then after ∆VFB% is calculated, proper version of the
AP3775 can be chosen accordingly.
(40)
∆VFB % = I O _ MAX ⋅ RCABLE /(VFB ⋅
2.6 Cable Compensation Design
RFB1 + R FB 2 N S
⋅
)
RFB 2
NA
(43)
Design Example (for 5V/1.2A application):
Two versions of IC are designed to meet different
requirement for cable voltage compensation. As we know,
an increase voltage at VFB (∆VFB_CABLE) will introduce an
increase voltage at VOUT (∆VOUT_ CABLE), which is a linear
function of the output load (IOUT). Then in application of
the AP3775, CPC pin detects the load information and a
corresponding delta voltage is added to VFB to compensate
the voltage drop at output cable.
Specification:
Input voltage: 85VAC to 265VAC
Output voltage @ cable: VO_CABLE=5V
Output current: IO=1.2A
Output voltage @ PCB: VO=5.13V, (AWG26 Cable,
Length of Cable=100cm, RCABLE=0.267Ω)
As defined in datasheet below, for example, in the AP3775,
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Application Note 1088
Other setting by users:
Switching frequency: fSW=65kHz
Forward voltage of secondary diode: Vd=0.4V
Forward voltage of auxiliary diode: Vda=1.1V
VCC voltage: VCC=14V
Core_type: RM5 (Ae=23.7mm2), BMAX<3000GS
Vdc_spike=50V (with snubber circuit)
Np =
LP ⋅ I PK
LP ⋅ I PK
≥
= 65 T
Ae ⋅ ∆B Ae ⋅ B max
(51)
We choose NP=90T
NS =
NP
= 6T
N
(52)
NA =
N S ⋅VA
= 16 T
VS
(53)
Design Steps:
1) Calculate Turn Ratio of Transformer (NPS)
N PS ≤ N PS _ MAX =
Vindc _ min ⋅ η i ⎛ k
⎞
⋅ ⎜ − 1.1⎟ = 15.8
VS
2
⎠
⎝
6) Check the maximum duty cycle of primary side
(44)
The maximum duty cycle of primary side is calculated as
following,
(45)
Vindc_min = Vinac_min ⋅ 2 − 40
D=
Considering some margin for Flyback PSR control, we
choose NPS=15.
(VO + Vd ) ⋅ N ⋅ 0.4
= 0.43
Vindc ⋅ η i
(54)
7) Check reverse voltage of auxiliary diode
2) Check stress voltage of primary side switch and
reverse voltage of secondary diode.
Vdar = V A +
According to formulas (25), (26) and the selected NPS,
proper power devices could be chosen.
Vds _ switch = Vdc_spike + Vindc_max +
Vdr = VS +
Vindc_max ⋅ N S
NP
VS ⋅ N P
= 505V < 700V
NS
= 30V < 40V
Vindc_max ⋅ N A
NP
= 80V
(55)
8) Feedback Resistors
(46)
RFB1 Vo + VD
=
⋅ N A − 1 = 2.98
RFB 2 N S ⋅ VFB
(47)
RFB1=29.8kΩ, RFB2=10kΩ
(56)
9) Line Compensation Resistors
3) Calculate the peak current of primary side and
current sense resistor (IPK & RCS)
I pk =
RCS =
I pks
N ⋅ηi
=
k ⋅ IO
≈ 380mA
N ⋅ηi
VCS
≈ 1.2 Ω
I pk
RLINE = (
2 ⋅ VS ⋅ I O
= 1.5mH
2
2
I PK
⋅ f SW ⋅ η i
⋅ Rcs ) /(
NA
RFB 2
⋅
⋅ g m ) = 6.3k Ω
N P RFB1 + RFB 2
(57)
VFB=3.7V, the same in two versions of the AP3775. Then,
(49)
VFB % = I O _ MAX ⋅ RCABLE /(VFB ⋅
RFB1 + RFB 2 N S
⋅
) = 5 .8 %
RFB 2
NA
(58)
According to datasheet information, the AP3775 is a better
choice.
(50)
VO _ FL = VO _ NL + (VFB % ⋅ VFB ⋅
RFB1 + RFB 2 N S
⋅
) − I O _ MAX ⋅ RCABLE = 5.01V
RFB 2
NA
(59)
Where VO_NL=5V. Therefore, the output voltage at cable
terminal at full load is a little higher than the voltage at
light load.
5) Calculate the turns of primary, secondary and
auxiliary (NP, NS, NA)
Nov. 2012
Lp
10) Cable Compensation Choice
(48)
4) Calculate the inductance of primary side---LP
LP =
t delay
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Application Note 1088
Design Results Summary
1.Maximum peak current of primary side and RCS
IPK
380
mA
Peak current of primary side
RCS
1.2
Ω
LP
1.5
mH
NPS
15
NP
90
T
Turns of primary side
NS
6
T
Turns of secondary side
NA
16
T
Turns of auxiliary side
Current sensed resistor
2.Transformer
DMAX
Inductance of primary side
Turn ratio of primary and secondary
0.43
Maximum duty cycle of primary side at VINDC=80V
3. Primary power switch and diode
Vds_switch
505
V
Voltage stress of primary power switch
Vdr
30
V
Maximum reverse voltage of secondary diode
Vdar
80
V
Maximum reverse voltage of auxiliary diode
4. Voltage feedback resistors
RFB1
28.9k
Ω
Feedback resistor at upside from auxiliary side to FB pin
RFB2
10k
Ω
Feedback resistor at downside from FB pin to GND
Ω
Line compensation resistor
5. Line compensation resistor
RLINE
6.3k
6.Cable Compensation
IC version
AP3775
VO_NL
5
V
Output voltage @ light load
VO_FL
5.01
V
Output voltage @ full load
3. Summary
In order to get good performance of the AP3775, it is
important to correctly design standby power, switching
frequency, transformer parameters, feedback resistance and
line compensation resistance. This application note only
Nov. 2012
gives a preliminary design guideline about these aspects
and considers ideal conditions, so some parameters need to
be adjusted slightly on the basis of the calculated results.
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
12
Application Note 1088
4. Application of AP3775 with AP4341
FR1
L1
TR1
D1
C8
R 12
R3
D 4 to D7
R6
C1
+
C2
R7
D2
+
R4
OUT VCC
GND
R11
L2
C5
D3
C3
IC2
AP4341
+
+
C4
VO
R10
Q1
IC1
AP3775
VCS
VCC
CPC
R5
R16
OUT
FB
C6
EM
GND
IS
R17
R2
Figure 13. Typical Application Circuit of AP3775 with AP4341
In Primary Side Regulation of the AP3775 application, the
AP4341 must be used at secondary side as the output
voltage regulator at light load, excellent dynamic response
and low standby power can be achieved. When detecting
the output voltage lower than a certain level, AP4341
outputs periodical signals which will be coupled to
auxiliary side and detected by the AP3775, and the AP3775
will begin an operating pulse, then the output voltage will
Nov. 2012
rise. By fast response and cooperation, the AP4341 and
AP3775 can maintain a constant output voltage with very
low operating frequency at light load and also can
effectively improve the transient performance for Primary
Side Regulation power system. Beside, dummy load is not
needed at secondary side and as a result standby power will
be decreased.
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
13
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