AN1040

Application Note 1040
Design of Power Factor Correction Circuit Using AP1661A
Prepared by Zhao Xiang Yuan
System Engineering Dept.
1. Introduction
The AP1661A meets IEC61000-3-2 standard even at
one-quadrant load and THD lower than 10% at
high-end line voltage and full load.
The AP1661A is a current-mode PFC controller
operating in DCM boundary mode and pin-to-pin
compatible with the predecessor AP1661 but with
improved performance.
2. Product Features
•
Designed with advanced Bi-CMOS process, the
AP1661A features low start-up current and low
operating current for extremely low power
consumption to comply with the power saving
requirements.
•
•
•
•
•
•
The AP1661A features a special highly linear
multiplier to realize near unity power factor and
extremely low THD, even with wide range mains.
•
•
•
•
The AP1661A also has rich protection features such
as over voltage protection, brown-out protection and
open loop protection.
COMP
INV
2
1
VCC
8
MULT
4
Multiplier
Over Voltage
Detection
VCC
Internal
Supply 7V
R1
CS
3
2.5V
Voltage
Regulation
Zero Current Detection Control for DCM
Boundary Conduction Mode
Proprietary Design for Minimum THD
Ultra-low Start-up Current (30µA)
Low Quiescent Current (2.5mA)
Adjustable Output Voltage with Precise OVP
Internal Start-up Timer
Disable Function for Reduced Current
Consumption
Totem Pole Output with 600mA Source Current
and 800mA Sink Current
Under-voltage Lockout with 2.5V Hysteresis
1% Precise Internal Reference Voltage
Compact Size with DIP-8 and SOIC-8 Packages
R Q
S
UVLO
R2
7
Driver
GD
Vref
Zero Current
Detector
2.1V
1.6V
Starter
Disable
6
5
GND
ZCD
Figure 1. Functional Block Diagram of AP1661A
Sep. 2009
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
1
Application Note 1040
3. Pin Descriptions
VIN
INV (Pin 1): This pin is the inverting input of the
error amplifier. It is connected to an external resistor
divider which senses the output voltage.
Voltage
Regulation
VCC
8
COMP (Pin 2): This pin is the error amplifier output.
It is made available for voltage loop compensation by
resistor and capacitor combination between pin 1 and
this pin.
22V
MULT (Pin 3): Input of the multiplier. This pin
senses the AC sinusoidal voltage and is multiplied
with comp voltage.
Figure 2. Supply Block
VREF
Error Amplifier and OVP Block
The error amplifier regulates the PFC output voltage.
The internal reference on the non-inverting input of
the error amplifier is 2.5V. The error amplifier’s
inverting input (INV) is connected to an external
resistor divider which senses the output voltage. The
output of error amplifier is one of the two inputs of
multiplier. A compensation loop is connected outside
between INV and the error amplifier output.
Normally, the compensation loop bandwidth is set
very low to realize good power factor for PFC
converter.
CS (Pin 4): Input of the current control comparator.
This pin senses the power switch current and
compares with the output of the multiplier. When the
CS pin voltage is higher than the output of the
multiplier, the external MOSFET will be turned off.
ZCD (Pin 5): Zero current detection input. When the
ZCD pin voltage decreases below 1.6V, the external
MOSFET will be turned on. If it is connected to
GND, the device is disabled.
To ensure fast over voltage protection, the internal
OVP function is added. If the output over voltage
occurs, excess current will flow into the output pin of
the error amplifier through the feedback
compensation capacitor. The AP1661A monitors the
current flowing into the error amplifier output pin.
When the detected current is higher than 40µA, the
dynamic OVP is trigged. The IC will be disabled and
the drive signal is stopped. If the output over voltage
lasts so long that the output of error amplifier goes
below 2.25V, static OVP will take place. Also the IC
will be disabled until the output of error amplifier
returns to its linear region.
GND (Pin 6): Ground. Current return for gate driver
and control circuit of the IC.
GD (Pin 7): Gate driver output. A series resistor
between this pin and the gate of power switch can
reduce high frequency noise.
VCC (Pin 8): Supply voltage of gate driver and
control circuits of the IC.
4. Functional Block Description
Supply Block
As shown in Figure 2, pin 8 is the VCC of AP1661A.
There is a zener diode with typical 22V clamp
voltage (30mA rated) to protect the device. A voltage
regulator generates a 7.5V voltage to function as the
IC’s internal supply except for the output stage which
is supplied directly from VCC. In addition, a precise
internal reference (2.5V±[email protected]°C) is used to get a
good regulation.
R1 and R2 (see Figure 3) will be selected as below:
R1
Vo
=
−1
R 2 2.5V
R1 =
∆VOVP
40µA
Pin 2 (COMP) is the output of the error amplifier. A
slow bandwidth compensation network is placed
between this pin and INV (pin 1) to avoid output
voltage ripple influence to the system.
An undervoltage lockout (UVLO) comparator is used
to ensure a reliable operation
Sep. 2009
UVLO
In the simplest case, this compensation is just a
capacitor, which provides a low frequency pole as
well as a high DC gain.
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
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Application Note 1040
make the turn-on of the MOSFET occur exactly at
the valley of the drain voltage oscillation. When the
boost inductor current reaches zero, the inductor will
oscillate with the MOSFET drain capacitance (see
Figure 5). This will minimize the power loss when
turned on.
An internal starter generates a pulse to turn on the
external MOSFET at start-up since no signal is
coming from ZCD. The repetition rate of the starter is
greater than 70ms (@14kHz).
The ZCD pin can also be used to disable the IC. If the
voltage of this pin falls below 0.25V, the IC will be
shut down. Thus, the power consumption of the IC is
reduced.
Figure 3. Error Amplifier and OVP Block
Zero Current Detection Block
The AP1661A is a DCM boundary conduction
current mode PFC controller. Usually, the zero
current detection (ZCD) voltage signal comes from
the auxiliary winding of the boost inductor. When the
voltage of this pin decreases below 1.6V, the driver
signal becomes high to turn on the external
MOSFET.
R Q
S
Driver
Zero Current
Detector
2.1V
1.6V
Starter
200µA
0.2V
5
ZCD
Disable
Figure 5. Optimum MOSFET Turn-on
Vin
Multiplier Block (Figure 6)
The multiplier has two inputs. One (Pin 3) is the
divided AC sinusoidal voltage which makes the
current sense comparator threshold voltage vary from
zero to peak value. The other input is the output of
error amplifier (Pin 2). In this way, the input average
current wave will be sinusoidal as well as reflects the
load status. Accordingly, a high power factor and
good THD are achieved. The multiplier transfer
character is designed to be linear over a wide
dynamic range, namely, 0V to 3V for pin 3 and 2.0 V
to 5.8V for pin 2. The relationship between the
multiplier output and inputs is described as the
following equation:
L
Figure 4. Zero Current Detection Block
The boost inductor winding turn ration, m, should be
selected to ensure ZCD pin voltage higher than 2.1V
during MOSFET turned-off. Then
m≤
Vo − 2 ⋅ Vinrms(max)
2. 1
A resistor is placed between the auxiliary winding
and ZCD pin to limit the current sink into the IC. The
limiting resistor’s actual value can be fine-tuned to
Sep. 2009
VCS = k × (VCOMP - 2.5) × VMULT
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
3
Application Note 1040
The AP1661A is equipped with a special circuit that
reduces the AC input current conduction dead-angle
near the zero-crossings of the line voltage (crossover
distortion). In this way, the THD of the current is
considerably reduced.
where VCS (Multiplier output) is the reference for the
current sense, k is the multiplier gain, VCOMP is the
voltage on pin 2 (error amplifier output) and VMULT is
the voltage on pin 3.
Current Comparator and PWM Latch
The PFC switch’s turn-on current is sensed through
an external resistor in series with the switch. When
the sensed voltage exceeds the threshold voltage (the
multiplier output voltage), the current sense
comparator’s output will become low and the
external MOSFET will be turned off. This ensures a
cycle-by-cycle current mode control operation.
R3
Q
R4
Rs
MULT
COMP
2
Error
Amplifier
3
CS
4
Multiplier
1.6V
Current sense
comparator
The sense resistor value is calculated as:
R Q
S
RS ≤
Figure 6. Multiplier Block
When the power MOSFET is turned on, a narrow
spike on the leading edge of the current waveform
can usually be observed. There is an internal R/C
filter in AP1661A to attenuate this noise and prevent
the false triggering caused by the turn-on spike. In
low power applications, the external R/C filter
connected to the CS pin is not needed.
VMULTpk, the peak value for VMULT occuring at
maximum mains voltage, should be 3V or below. The
MULT pin resister divider (see figure 6) will be as
below:
VCS (V)
VMULTpk
Driver
The AP1661A totem pole output stage is capable of
driving a power MOSFET or IGBT with 600mA
source current and 800mA sink current.
2 ⋅ Vinrms(max)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
VCOMP=2.6V
VCOMP=2.8V
GND
Pin 6 is the Ground of the IC. This pin acts as the
current return both for the internal circuitry signal
and for the gate drive current. These two paths should
be laid out separately in the printed circuit board.
VCOMP=3.0V
VCOMP=3.2V
VCOMP=3.5V
VCOMP=4V
VCOMP=4.5V
VCOMP=5V
VCOMP=MAX
5. Comparison Between AP1661A and
AP1661
VMULT (V)
The AP1661A is pin-to-pin compatible with AP1661
and offers improved performance. Table 1 compares
the two devices and lists the key parameters that have
the most significant impact on the design.
Figure 7. Multiplier Characteristics Family
In practical application, the typical resistor divider of
MULT pin can be set 1/170 to achieve a good THD
performance.
Sep. 2009
I Rspk
where VCSpk is the maximum voltage of VCS, which
can be set 1.6V for linear operation in the entire
working range.
Figure 7 shows the typical multiplier characteristics
family. The linear operation of the multiplier is
guaranteed in the range of 0 to 3V of VMULT and 0 to
1.6V of VCS.
R4
=
R3 + R 4
VCSpk
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
4
Application Note 1040
Table 1. Comparison Between AP1661A and AP1661
Parameter
AP1661
AP1661A
Turn on & Turn off Threshold (typ.)
12/9.5V
12.5/10V
Start-up Current (typ.)
50µA
30µA
Quiescent Current (typ.)
2.6mA
2.5mA
4mA
3.5mA
Enable Threshold on Pin 1 INV (max.)
720mV
600mV
Current Sense Reference Clamp (typ.)
1.7V
1.6V
Operating Supply Current (typ.) @CL=1nF and f=70kHz
6. Typical Application of AP1661A
The AP1661A has an increased 0.5V UVLO
threshold to achieve more margin for the gate drive
voltage. The low start-up current and operating
current can reduce the power consumption to satisfy
the power saving requirements. INV(pin 1) features
brown-out and open-loop protection. To start the IC,
the voltage on this pin must exceed 0.5V (typ.).
When the input voltage is too low or the upper
feedback resistor fails open, the device will be
disabled. The INV can also be used as a remote
control input for power management. A lower current
sense clamp voltage allows lower peak current with
the same sense resistor to get a reliable over current
protection. The lower clamp voltage also allows a
lower sense resistor for the same peak current, which
can reduce the associated power dissipation to meet
energy saving requirement.
Here a wide range of demonstration board is designed
and the evaluation results are presented.
The target specification:
AC voltage RMS voltage: Vin_rms = 85V to 265V
DC output regulated voltage: VO = 400V
Rated output power: PO = 90W
Minimum switching frequency: fSW(min)=35kHz
Expected efficiency: η>90%
Output voltage ripple at full load: ∆VO≤±30V
Maximum output overvoltage: ∆VOVP=50V
Figure 8 shows the designed electrical schematic with
the values of all parts.
Figure 8. Design Electrical Schematic of AP1661A
Sep. 2009
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
5
Application Note 1040
Figure 9. Demo Board PCB and Component Layout (Top View, 125mm×56mm)
Figure 10. Demo Board PCB and Component Layout (Bottom View, 125mm×56mm)
Sep. 2009
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
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Application Note 1040
To evaluate the performance of the PFC
demonstration board, the following parameters have
been measured: PF (Power Factor), THD (Total
Harmonic Distortion), ∆V(Peak-to-Peak Output
Voltage Ripple), Vo (Output Voltage) and η
(Efficiency). Table 2 and Table 3 give the test results
of AP1661 and AP1661A at full load condition
respectively.
Compare AP1661A with AP1661, the converter can
get a higher PF and better THD, especially at high
end line voltage. The THD of AP1661A can even be
reduced below 10% at full load.
Table 2. AP1661-90W Evaluation Results
Vin_rms (V)
PIN (W)
PO (W)
η (%)
VO (V)
∆VO (V)
PF
THD (%)
85
99.21
89.85
90.57
398.8
17
0.9997
1.88
110
95.672
89.84
93.90
398.8
17
0.9992
3.55
150
93.996
89.84
95.58
398.9
17
0.9978
5.05
230
93.058
89.84
96.54
398.9
17
0.9874
8.66
250
92.977
89.82
96.60
398.9
17
0.9822
10.2
265
92.933
89.81
96.64
398.9
17
0.9773
11.71
Table 3. AP1661A-90W Evaluation Results
Vin_rms (V)
PIN (W)
PO (W)
η (%)
VO (V)
∆VO (V)
PF
THD (%)
85
98.43
89.2
90.62
396.2
17
0.9997
1.78
110
94.908
89.18
93.96
396.2
17
0.9992
3.41
150
93.262
89.18
95.62
396.2
17
0.9978
4.87
230
92.344
89.20
96.6
396.3
17
0.9898
5.26
250
92.25
89.19
96.68
396.3
17
0.9856
5.47
265
92.205
89.18
96.72
396.3
17
0.9818
5.98
Sep. 2009
Rev. 1. 0
BCD Semiconductor Manufacturing Limited
7
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