AN1066

Application Note 1066
Design Guideline and Application Notes of AP1682 System Solution
Prepared by Cheng Zeng Qi
System Engineering Dept.
1. Introduction
•
The AP1682 is a high performance AC/DC universal input
Primary Side Regulation Controller with Power Factor
Correction for LED driver applications. The device uses
Pulse Frequency Modulation (PFM) technology to regulate
output current while achieving high power factor and low
THD.
•
•
•
•
•
•
•
•
•
The AP1682 provides accurate constant current (CC)
regulation while removing the opto-coupler and secondary
control circuitry. It also eliminates the need of loop
compensation circuitry while maintaining stability. The
AP1682 achieves excellent regulation and high efficiency,
yet meets the requirement of IEC61000-3-2 harmonic
standard.
3. Pin Configuration and Description
The AP1682 features low start-up current, low operation
current and high efficiency. It also has rich protection
features including over voltage, short circuit, over current,
over temperature protection.
The AP1682 is available in SOIC-8 package.
2. Product Features
•
•
Primary Side Control for Output Current Regulation
Without Opto-coupler and Secondary CV/CC Control
Circuitry
Low Start-up Current
Apr. 2012
High Power Factor and Low THD for Universal Input
Range
Tight CC Regulation Performance for Universal Input
Mains Voltage Range
Eliminates Control Loop Compensation Circuitry
Wide VCC Voltage Range
Built-in Acceleration Start
Open-load and Reload Detection
Over Voltage and Short Circuit Protection
Over Temperature Protection
Over Current Protection
Cost Effective Total PFC LED Driver Solution
NC
1
8
VCC
VS
2
7
OUT
VPK
3
6
GND
CS
4
5
FB
Figure 1. Pin Configuration of AP1682
Pin Number
Pin Name
Function
1
NC
2
VS
3
VPK
4
CS
5
FB
6
GND
No connection
The rectified input voltage sensing pin. The pin is detecting the
instantaneous rectified sine waveform of input voltage.
The rectified input voltage peak value sensing pin. The pin is detecting
the rectified sine waveform peak value of input voltage.
The primary current sense pin.
This pin captures the feedback voltage from the auxiliary winding. FB
voltage is used to control no load output voltage and determine
acceleration stop point at start up phase.
Ground. Current return for gate driver and control circuits of the IC.
7
OUT
Gate driver output pin.
8
VCC
Supply pin of gate driver and control circuit of the IC.
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BCD Semiconductor Manufacturing Limited
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Application Note 1066
Figure 2. Functional Block Diagram of AP1682
4. Operation Principle Description
Tonp =
4.1 Power Factor Correction and Constant Output
Current Control Strategy
Vcs
Rcs
Tons
Tsw =
K
The function of PFC requires input AC current waveform
to follow input AC voltage waveform, a sinusoidal
waveform as we know.
2 ⋅ Tsw
(4)
Vcs L p ⋅ I pk
Vcs L p Vcs
⋅
⋅
⋅
L p ⋅ K ⋅ Vcs2
R
Vin
R V R
I in= cs
= cs in cs =
T
T
2 ⋅ Rcs2 ⋅ Tons ⋅ Vin
2 ⋅ ons
2 ⋅ ons
K
K
(1)
The primary switch on time Tonp, primary switch peak
current Ipk and switching period Tsw are defined as:
(5)
The input AC voltage VIN is defined
Vin = 2Vin _ rms ⋅ sin θ
Apr. 2012
(3)
Where, LP is the primary winding magnetizing inductance
of transformer, VCS is the primary current sense voltage,
RCS is the current sense resistor, TONS is the conduction
time of secondary side diode. From the above equations it
can be got:
The AP1682 solution uses PFM technology and Flyback
converter always operates at Discontinuous Current Mode
(DCM). So the input current IIN is
I pk ⋅ Tonp
(2)
Vin
I pk =
The AP1682 uses Primary Side Regulation (PSR) to
regulate constant output current and achieve the high
Power Factor at the same time.
I in=
L p ⋅ I pk
Rev. 2. 0
(6)
BCD Semiconductor Manufacturing Limited
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Application Note 1066
It is assumed that
V
Vcs = s ⋅ VCS _ REF = K LINE ⋅ VCS _ REF ⋅ Sin θ
V pk
T
K = ons = K LINE ⋅ K c ⋅ Sin θ
Tsw
above equations, it can be obtained that
(7)
I in=
(8)
2
Vout ⋅ N t ⋅ VCS ,EQ ⋅ K LINE
2 2 ⋅ Rcs ⋅ Vin _ rms
⋅ sin θ
(9)
So it can be seen that the input current follows the input
voltage sinusoidal waveform, which shows PFC function
works. Figure 3 shows the basic operation principle and
waveforms of AP1682 PFC solution.
VCS , EQ = VCS _ REF ⋅ K c
Here, VCS_REF is 1V, KC is 4/9 and VCS,EQ is 4/9V. From the
Figure 3. Basic Operation Waveforms
Apr. 2012
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Application Note 1066
And the output current IO can be got as
IO =
2
2
N t ⋅ VCS , EQ ⋅ K LINE
⋅η t ⋅ Sin 2θ N t ⋅ VCS , EQ ⋅ K LINE
⋅ η t 1 − Cos 2θ
Tons
N ⋅ T ⋅ V ⋅η
⋅ I pks = t ons cs t =
=
2 ⋅ Tsw
2 ⋅ Tsw ⋅ Rcs
2 ⋅ Rcs
2 ⋅ Rcs
2
works in acceleration start phase until FB pin voltage
reaches 1.75V. From 1.75V to 4V, the system works in CC
region. The output current is constant regardless of output
voltage changing. When open load condition or load
disconnecting happens, the output voltage rises to the
maximum value and the FB pin voltage reaches 4V. The
system will work in HICCUP state to keep output voltage
below the maximum value and VCC voltage changes
between startup threshold and UVLO threshold. If
abnormal condition happened such as fault connection or
excess auxiliary winding turns, FB pin voltage reaches to
6V, then AP1682 will enter FB OVP protection state. This
will lead to AP1682 latch working mode. Figure 4 shows
the FB pin working regions.
ηt is the power conversion efficiency considering the total
power dissipation.
From above output current equation it is concluded that the
output current has the double line frequency AC
components, which results in the double line frequency
output voltage and output current ripple. There are always
output capacitors to filter the ripple in Flyback topology, so
the output voltage ripple depends on the total output
capacitance. And for LED driver, the output current ripple
is determined by the output voltage ripple and LED loading
V-I characteristics.
The output current DC value is
I o _ mean =
1
π
π
2
Nt ⋅VCS ,EQ ⋅ K LINE
⋅ηt ⋅ Sin2θ
0
2 ⋅ Rcs
∫
dθ =
(10)
2
Nt ⋅VCS ,EQ ⋅ K LINE
⋅η t
4 ⋅ Rcs
(11)
Therefore, the constant output current control can be
realized with appropriate parameter design.
4.2 Acceleration Start
For LED lighting application, the lower turn on delay time
is required. To reduce start-up time, an acceleration start
function is embedded in AP1682. At start-up phase, after
VCC voltage reaches turn on threshold, AP1682 controls
the power converter operating at the max frequency with
DCM Boundary mode to provide more energy to output.
The acceleration start phase will stop when detected FB pin
voltage reaches soft start threshold 1.75V.
Figure 4. FB Function Region Diagram
4.5 Input Voltage Sensing
4.3 VCC Pin Voltage Region
With the resistor divider circuit connecting to rectified DC
bus, VS pin detects the instantaneous rectified sine
waveform signal of input voltage and VPK pin detects the
corresponding peak value. The internal divider by VS/VPK
generates sine waveform as current reference signal. In
general, the VS/VPK value should be design between 0 and
1.
In LED lighting application, because the LED cell forward
voltage drop VF varies with different current and operation
temperature, the output voltage need a wider operation
range. Therefore the VCC voltage which comes from aux
winding coupling with transformer winding also needs the
wider operating voltage range. The AP1682 start-up
voltage threshold is 18.5V (typ.), and the UVLO voltage
threshold is 8.0V. The AP1682 have a wide operating
voltage window from 8V to 30V. If the VCC pin voltage
is higher than 30V, the AP1682 will enter VCC OVP
protection state, which will lead to AP1682 automatic
restart.
4.6 Primary Current Sense and Over Current
Protection (OCP)
The current sense signal connecting to CS pin is for
primary peak current feedback and OCP function. The
primary current sense resistor value is one of design inputs
for output constant current value setting according to
equation (13). The CS pin peak value at one half line cycle
should be set as 1V. The primary OCP comparator
4.4 FB Pin Voltage Region
The FB pin voltage has several comparator thresholds for
different function. At start-up phase, the AP1682 system
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Application Note 1066
threshold is 4V for primary side short protection. When
OCP threshold is triggered, AP1682 enters latch mode and
switch stops working. The latch mode will be reset after
input power recycle.
5. Operation Parameter
Components Selection
Design
design method.
This application notes emphasis on the Flyback power
converter design with AP1682. BCD will release the
AP1682 design sheet tools for both Flyback and
Buck-Boost application to meet the all types of application
requirements.
and
The off-line primary side regulation power factor solution
with AP1682 is the single stage PFC Flyback structure.
Since of PFC operation and the special PFM control
technology, the circuit operation parameter of Flyback
converter is little different with the traditional off-line
Flyback converter. In a half line cycle, the operation
parameters, such like DC bus voltage, primary peak current,
duty cycle, etc., vary with input sine waveform voltage.
In Buck-Boost application, there is not transformer but an
inductor, which means the equivalent turns ratio is 1. In
order to match the different design requirements, the KP,
VS/VPK can be adjusted according to the following
equation:
K LINE <
5.1 Transformer Turns Ratio Determination
(12)
According to the PFM principle, at the minimum input
voltage VIN_RMS_MIN and the maximum output power (the
maximum output voltage VO_MAX and constant output
current IO) condition, the Flyback converter with AP1682
operates at the closest to DCM boundary mode. So from
the equation (10) it can be get
L p ⋅ I pk
2 ⋅ Vin _ rms _ min
+
Ls ⋅ I pks
Vo _ max + Vd
<
Ls ⋅ I pks
Vo _ max + Vd
⋅
1
K c ⋅ K LINE
(
K c ⋅ Vo _ max + Vd + 2 ⋅ Vin _ rms _ min ⋅ η t
)
(15)
Therefore, as to the higher output voltage (i.e., >200VDC)
Buck-Boost application, the KP value should be set as the
lower so that the converter keep operating at DCM mode.
On the other hand, if the output voltage is the lower, the KP
value should be set as the higher, so that the higher diode
rectifier conduction duty cycle, the lower primary peak
current, and the higher conversion efficiency.
In order to guarantee the Flyback converter operating at
DCM mode at the whole input range and output loading
condition, the Tons, Tonp and Tsw should meet
Tons + Tonp < Tsw
2 ⋅ Vin _ rms _ min ⋅ η t
5.2 The Current Sense Resistor Calculation
The primary current sense resistor can be calculated
according to equation (13) which is derived from equation
(9)
Rcs =
(13)
2
⋅η t
N t ⋅ VCS ,EQ ⋅ K LINE
4 ⋅ IO
=
2
N t ⋅ K LINE
⋅η t
9 ⋅ IO
(16)
5.3 Transformer Inductance Design
Where Vd isthe voltage drop on the secondary diode and
trace resistance. From the transformer relationship between
primary parameter and secondary parameter, it can be got:
⎛
⎞ 2 ⋅ Vin _ rms _ min ⋅ηt
1
N t < ⎜⎜
− 1⎟⎟ ⋅
Vo _ max + Vd
⎝ K c ⋅ K LINE
⎠
Considering the efficiency and transformer size, the
minimum switching frequency at low line input and
maximum output loading is set as FSW_MIN, then it can be
got
(14)
Vo _ max + Vd = Ls ⋅
The final turn ratio design should also be revised by
considering the primary switch and secondary diode
voltage stress requirements.
Tons
=
Lp
Nt
2
Nt ⋅
⋅
K LINE ⋅ VCS _ REF ⋅ηt
Rcs
K c ⋅ K LINE
Fsw _ min
=
L p ⋅ VCS _ REF ⋅ Fsw _ min ⋅ηt
N t ⋅ K c ⋅ Rcs
(17)
From the above equation, the primary inductance LP is
As we know, the Flyback converter is an isolated
Buck-Boost type converter. So the AP1682 also can be
used in non-isolated Buck-Boost application. The circuit
structure and operation principle of Buck-Boost converter
with AP1682 is very similar to the Flyback. As shown in
Figure 5 and Figure 6, comparing to the Flyback
application, the Buck-Boost converter has only inductor
instead of transformer, has not primary snubber circuit. The
most components of Flyback and Buck-Boost have same
Apr. 2012
I pks
Lp =
N t ⋅ K c ⋅ Rcs ⋅ (Vo _ max + Vd )
VCS _ REF ⋅ Fsw _ min ⋅ηt
(18)
5.4 Transformer Winding Turns Number Design
The worst case operation condition of transformer is at
peak voltage area of sine waveform input voltage in the
minimum input voltage VIN_RMS_MIN and the maximum
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Application Note 1066
output loading. The transformer design should be based on
the worst case operation condition.
The maximum on status average current of secondary
diode is
The effective area of ferrite core is Ae, and the maximum
flux density Bm is
I diode _ av _ max =
Bm =
L p ⋅ I pk
=
Ae ⋅ N p
4 ⋅ Lp ⋅ Io
Then the primary winding turns number NP is
Np =
4 ⋅ Lp ⋅ I o
Np
I s _ AC = −
(21)
Nt
N s ⋅ Vccmax
Vo _ min + Vd
(23)
∆Vo = RLED ⋅ K cr ⋅ I o = I o ⋅
Here, the VSPK is the spike voltage which is result from the
leakage inductance and depends on the primary peak
current value and leakage inductance value, approximately
about 100V to 200V.
⋅V
6 2 ⋅ R ⋅ Vin _ rms _ min ⋅ η t
(24)
Cout _ min
2
cs
Apr. 2012
2 ⋅ Vin _ rms _ max
Nt
+ (Vo _ max + Vd )
1 + (4 ⋅ π ⋅ Fline ⋅ Cout ⋅ RLED )
2
(30)
1
-1
2
K cr
>
4 ⋅ π ⋅ Fline ⋅ RLED
(31)
It can be seen that the higher output current ripple, the
higher required output capacitance. The worst case is when
Kcr is 100%, the required output capacitance is 0, that
means the maximum output current ripple amplitude (peak
value) equals to the output current average value. The
The maximum voltage stress of secondary diode is
Vdiode _ max =
RLED
From the above equation, it can be seen that the higher
output capacitance, the lower output current ripple. In order
to meet output current Kcr*IO requirement, the minimum
output capacitance Cout_min is
The maximum Drain to Source current (RMS value) is
2
CS _ REF
(29)
The output capacitor is a capacitive load paralleled with
output LED, so the output voltage ripple
The maximum voltage stress of primary switch is
VQds _ max = 2 ⋅ Vin _ rms _ max + N t * (Vo _ max + Vd ) + Vspk
(28)
∆Vo = RLED ⋅ ∆I o
5.5 Primary Switch and Secondary Diode Selection
N t ⋅ (Vo _ max + Vd ) ⋅ K c ⋅ K
(27)
Cos 2θ = − I o ⋅ Cos 2θ
Generally Kcr is less than 30%. As to the definite LED
loading, there is a dynamic resistance RLED at DC operation
point, which can be calculated with the V-I curve of LED
cells. So the output voltage ripple ∆VO is
Here, VO_MIN is the minimum output voltage under the
condition of the minimum LED cells and lowest LED cell
forward voltage drop, VCCmax is the required maximum
VCC voltage at that condition.
I Qd _ RMS _ max =
4 ⋅ Rcs
∆I o = K cr ⋅ I o
(22)
2
LINE
2
N t ⋅ VCS ,EQ ⋅ K LINE
⋅η t
The maximum output ripple current ∆IO (peak value) is
always defined by customer as
The auxiliary winding turns number Naux is
N aux =
(26)
From equation (8) it can be seen that the secondary side
current includes DC components and double line frequency
sine waveform AC component. The AC component of
output current is
Secondary side winding turns number NS is
Ns =
4.5 ⋅ I o
K LINE
5.6 Output Capacitor Selection
(20)
Ae ⋅ Bm ⋅ N t ⋅ K c ⋅ K LINE ⋅ηt
2
=
According to the above calculated voltage and current
stress, the proper MOSFET and Schottky diode part can be
selected as primary switch and secondary rectifier.
Certainly, the efficiency and BOM cost are also the
important factors for components selection.
(19)
Ae ⋅ N p ⋅ N t ⋅ K c ⋅ K LINE ⋅ηt
I pks
(25)
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Application Note 1066
5.9 Line Compensation Circuit Design
output ripple current also depends on the output LED
loading characteristics. The higher dynamic resistance RLED,
the lower output ripple current, the lower required output
capacitance.
Because there is a constant delay time Td_off from the time
when CS pin voltage reaches the given reference to the
time when the real primary peak current reaches peak value,
the primary peak current value has a gap ∆Ipk with the ideal
value
5.7 Input Voltage Sense Circuit Design
The voltage range of the VS pin and VPK pin is from 0 to
clamp level 3.5V. As to most of isolated Flyback
application, the KLINE, the maximum value of VS/VPK,
always sets as 1. It is recommended to set the maximum
voltage of VS and VPK as 3V at the maximum input voltage
Vin_rms_max. The VS pin resistor divider proportion should
be set as
R6
=
R3 + R4 + R5 + R6
3
2 ⋅ Vin _ rms _ max
2 ⋅ Vin _ rms ⋅ sin θ = L p ⋅
(32)
2 ⋅ Vin _ rms ⋅ sin θ ⋅
=
(33)
(38)
6. Layout Consideration
The PCB layout rules are highlighted as following:
•
The Flyback converter power current flow loop area
should be minimized for better EMI performance
•
The R-RCD or DZ clamp snubber and output rectifier
loop areas should be minimized to achieve good EMI
and efficiency performance
•
The power ground and signal ground should be
connected by one node. Common connection of GND
will introduce disturbances to small signals. The
ground of transformer must be separate from the
ground of IC in order to pass ESD test.
•
C6 should be placed as close as possible to Pin VCC
of the AP1682 respectively.
Assume VCC auxiliary winding is tightly coupled with
primary and secondary winding, the auxiliary winding
voltage is
(34)
By sensing FB pin voltage, the LED driver can work at
HICCUP mode and keep output voltage below the
maximum output voltage limit value under no load or load
disconnection conditions. The FB pin voltage at normal
operation should be less than the minimum CV threshold,
so the voltage divider at FB pin should meet
Apr. 2012
(37)
Lp
Since the delay time Td_off includes IC internal delay time,
about 60ns, and primary switch turn off delay time and fall
time, this delay time value should be determined with the
real design application.
5.8 FB Pin Sense Circuit Design
N AUX
R17
⋅ (VO + V d ) ⋅
NS
R16 + R17
2 ⋅ Vin _ rms ⋅ sin θ ⋅ Td _ off ⋅ R cs
Td _ off ⋅ Rcs
R12
=
Rcomp + R12
Lp
The RC low pass filter consists of R7 and C4. It is
recommended use 1µF value for capacitor C4 and 330k for
R7 so that the corner frequency should be less than 10Hz.
3=
R12 + Rcs
= Rcs ⋅ ∆I pk
Rcomp + R12 + Rcs
Since RCS<<R14, then
In order to reduce the power loss on resistor connecting to
DC bus, the total resistance of R3+R4+R5+R6 should be as
large as possible.
N AUX
⋅ (VO + Vd )
NS
(36)
A resistor RCOMP is connected from DC bus to CS pin in
order to cancel the peak current gap ∆Ipk. The
compensation circuit should meet
Because VPK pin senses the peak value of sine waveforms,
a low pass filter is required to get the average value of sine
waveform voltage. So the VPK pin resistor divider
proportion should be set as
V AUX =
Td _ off
With the different input voltage, the different ∆IPK results
in the different constant output current. Therefore, a line
compensation circuit is necessary to decrease or eliminate
this gap and achieve the better output current accuracy.
A ceramic capacitor less than 100pF should be placed
closely VS pin to GND pin to avoid high frequency noise.
R5 + R6
3⋅π
=
R3 + R4 + R5 + R6 2 2 ⋅ Vin _ rms _ max
∆I pk
(35)
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Application Note 1066
7. Design Example
Nominal DC output voltage: VO=12V
Output constant current: IO=0.6A
Full load switching frequency: fSW=80kHz
Expected efficiency: η> [email protected]
Here is a design example of LED driver to demonstrate the
design process of AP1682 solution.
7.1 The Specification
AC mains voltage range: VIN_ac = 85 to 265VRMS
7.2 The Design Schematic
Figure 5. Typical Application Schematic of Isolated Solution with AP1682
7.3
Design
Parameter
Calculation
Components Selection
7.3.1 Transformer Parameter Determination
and
Certainly, the calculated results are theoretical value since
of some assumed condition and parameter tolerance. So
designer need fine-tune these design parameters to match
the real design.
For PSR isolated LED driver, the transformer parameters
determine the power converter operation status, so firstly
transformer design should be frozen, including primary to
secondary winding turns ratio, primary winding inductance,
etc. It is assumed that the secondary diode forward voltage
drop Vd is about 0.4V, transformer converter ratio ηt is
about 0.9 and the KLINE value is 1. According to design
specification and equation (14), the maximum turn ratio
should be
Nt <
1.25 ⋅ 2 ⋅ Vin _ rms _ min ⋅ ηt
Vo + Vd
= 10 .9
According to LED power board size requirements, a EF16
ferrite core is chose as transformer core. The effective area
of EF16 is 20.1mm2, the maximum flux density is set as
0.3T, so the primary winding turns number and secondary
winding turn number are
(39)
Ns =
Considering the primary switch and secondary diode
voltage stress, the Nt is selected as 9.
2
N t ⋅ K LINE
⋅η t
= 1.5
9 ⋅ IO
(40)
0.444 ⋅ N t ⋅ Rcs ⋅ (Vo + Vd )
= 1.03m
1 ⋅ Fsw _ min ⋅ η t
Apr. 2012
Np
= 12.6
Nt
= 114
(42)
(43)
(44)
N p = N t ⋅ N s = 117
The VCCmax is set as 16V, so the VCC winding turns number
is
The primary winding inductance of transformer LP is
calculated as
Lp =
Ae ⋅ Bm ⋅ N t ⋅ K c ⋅ K LINE ⋅ η t
Because transformer winding turns number must be integer,
so it can select NS as 13 TS, then primary winding turns
number should be
Then the primary sense resistor RCS is calculated as
Rcs =
4 ⋅ Lp ⋅ I o
Np =
N aux =
(41)
Rev. 2. 0
N s ⋅ Vccmax
= 16.7 ≈ 17
Vo + Vd
(45)
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Application Note 1066
7.3.2 Power Components Selection
With the designed transformer turns ratio, the primary
switch voltage stress is
Figure 6 shows the LED cell in design example forward
voltage forward current V-I curve characteristics. At the
output current DC operation point, the current variation of
each LED cell is 0.42A to 0.78A, and voltage variation is
3.45V to 4.1V. The output loading uses 4 pieces LED
cells in series. So the dynamic resistance RLED is
VQds _ max = 2 ⋅ Vin _ rms _ max + N t * (Vo _ max + Vd ) + Vspk
= 2 ⋅ 265 + 9 ⋅ 12.4 + 100 = 586
(46)
4 ⋅ ∆VLED 4 ⋅ (4.1 − 3.45)
=
= 7.22
∆I LED
0.78 − 0.42
Here, the VSPK is estimated about 100V. Therefore, a 600V
MOSFET device can be used here.
RLED =
The primary switch maximum RMS current is
The required output current ripple is defined as 30% of
output current, Kcr=0.3. So at the 50Hz AC frequency
condition, the required output capacitance should be
I Qd _ RMS _ max =
2
N t ⋅ (Vo _ max + Vd ) ⋅ K LINE
⋅ K c ⋅ VCS2 _ REF
6 2 ⋅ RCS ⋅ Vin _ rms _ min ⋅ η t
= 0.226
(47)
Cout _ min
Actually, in order to achieve the higher efficiency, the
much more higher current stress MOSFET is always
selected in real design to reduce the conduction power loss.
2 ⋅ Vin _ rms _ max
Nt
+ (Vo _ max + Vd ) = 54
(48)
R5 + R6
3⋅π
3⋅π
=
=
R3 + R4 + R5 + R6 2 2 ⋅ Vin _ rms _ max 2 2 ⋅ 265
The maximum on status average current is
I diode _ av _ max =
4.5 ⋅ I o
= 2.7
K LINE
(51)
7.3.4 External Circuit Design of AP1682
The maximum value of VPK pin is set as 3V, so the
proportion of VPK sense circuit is as
The secondary diode voltage stress is
Vdiode _ max =
1
-1
2
K cr
>
= 700 µF
4 ⋅ π ⋅ Fline ⋅ RLED
(50)
(52)
If R3 and R4 is selected as 1M, so the R5+R6 is calculated
as about 25.4k. In order to achieve the DC average value of
half rectified sine waveform, the low pass filter is
necessary. So a 0.33µF capacitor C4 is paralleled with R7
of 330K here.
(49)
A 60V/3A Schottky diode SB360 can be selected here. If
the higher efficiency is required, the higher current rating
diode is preferred.
The maximum value of VS pin is also set as 3V, so the
proportion of VS sense circuit is as
7.3.3 Output Capacitance Calculation
A big capacitance output capacitor is needed to eliminate
the double line frequency output current ripple. This ripple
is also relative to LED loading characteristics, dynamic
resistance RLED near DC value current.
R6
=
R3 + R4 + R5 + R6
3
=
2 ⋅ Vin _ rms _ max
3
2 ⋅ 265
(53)
So the R6 is calculated as about 16.2K. A ceramic
capacitor C3 is paralleled between VS pin and Ground to
bypass the high frequency noise. Too high capacitance will
result in the distortion of sine waveform current reference,
and then the worse Power Factor. So the capacitor less than
100pF value is recommended.
The FB pin resistor divider is used to detect output voltage
so that the power board can operate at no load condition.
The FB pin OVP threshold is 4V, therefore, the resistor
divider proportion is
3⋅ NS
R17
=
R16 + R17
N AUX ⋅ (VO + V d )
Figure 6. LED Cell Forward V-I Curve
Apr. 2012
Rev. 2. 0
(54)
BCD Semiconductor Manufacturing Limited
9
Application Note 1066
In order to reduce the components quantity, a resistor R20
is connected to the point between 2 start-up resistors
R8=R9=750K. Since the R8 and R9 value is much less
than line compensation resistor value, the R20 is about half
of line compensation value, 10M.
Here, R16=52.3k and R17=12k are selected.
The line compensation resistor value meet equation (55), if
the Td_off is assumed about 80ns, so the line compensation
resistor is
Rline
⎛ T
⋅R
R14 ⋅ ⎜1 − d _ off cs
⎜
L
p
⎝
=
Td _ off ⋅ Rcs
Lp
⎞
⎟ 2.4 K ⋅ ⎛1 − 80 n ⋅ 1.5 ⎞
⎜
⎟
⎟
1m ⎠
⎝
⎠=
≈ 20 M
80 n ⋅ 1.5
1m
Item
Description
QTY
C1
33nF/400V, X-capacitor
1
C2
100nF/400V, capacitor CL21
1
C3
100pF/16V, 0603, ceramic capacitor
1
C4
330nF/16V, 0603, ceramic capacitor
1
C5
1µF/25V, 1206, ceramic capacitor
1
C6
1nF/100V, 1206, ceramic capacitor
1
C7
1500µF/16V, 105ºC, 10mm*20mm electrolytic capacitor
1
C8
1nF/ 500V 0805, ceramic capacitor
1
2.2nF/275V, Y safety capacitor
1
D1
Diode, 1N4148, SOD-323
1
D2
1A/600V, SMA, US1J
1
D3
BCD, APD360VRT-G1, 3A/60V, Schottky diode, SMA
1
TVS 150V, SMA
1
7.5mH, Inductor,Φ6.5mm*12.5mm
2
F1
Fuse, 1.25A/250V
1
VR1
Varistor 07D471K
1
BD1
0.5A/600V,TO-269AA,MB6S
1
R1,R2
10KΩ, 5%, 1206, resistor
2
R3, R4
1MΩ, 1%,1206, resistor
2
R5
11KΩ, 1%, 0603, resistor
1
R6
16KΩ, 1%,0603, resistor
1
R7
330KΩ, 5%,0603, resistor
1
CY1
ZD1
L1,L2
Apr. 2012
7.4 The Material BOM List of Isolated Solution
with AP1682
(55)
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
10
Application Note 1066
Item
Description
QTY
R8,R9
750KΩ, 5%,1206, resistor
2
R10
100KΩ, 5%,0603, resistor
1
R11
20Ω, 5%,0603 , resistor
1
R12
3K3, 5%,0603 , resistor
1
R13
2R4, 1%,1206 , resistor
1
R14
3R3, 1%, 1206, resistor
1
R15
10Ω, 5%, 0805, resistor
1
R16
52.3KΩ, 1%,0603 , resistor
1
R17
12KΩ, 1%,0603 , resistor
1
R18
18KΩ, 5%,1206, resistor
1
R19
100Ω, 5%,1206, resistor
1
R20
10MΩ, 5%, 1206, resistor
1
R21
47R, 5%, 1206, resistor
1
R22
200KΩ, 5%, 1206, resistor
1
T1
EF16 10 pin 950µH, 5%,Transformer
1
U1
AP1682MTR-G1, SOIC-8, BCD’s IC
1
Q1
MOSFET, Infineon, SPI04N60, 4A/600V ,TO-251
1
7.5 Transformer Specifications
7.5.1. Electrical Diagram
Figure 7. Transformer Electrical Schematic Diagram
Apr. 2012
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
11
Application Note 1066
7.5.2. Electrical Specifications
Primary
Inductance
Primary Leakage
Inductance
Electrical
Strength
Pin 1-3, all other windings open, measured
at 1kHz, 0.4VRMS
Pin1-3, all other windings shorted, measured
at 10kHz, 0.4VRMS
1000µH,
±5%
50µH (Max)
60 seconds, 60Hz, from Pin 1-5 to Pin 6-10
3000Vac
7.5.3. Materials
Item
Description
1
Core: EF16, PC40 or equivalent
2
Bobbin: EF16, Horizontal, 12 Pin, (6/6)
3
Wire:ø0.13mm, for internal wire shielding winding
4
Wire: ø0.21mm, for the Primary winding
5
Wire: ø0.16mm, for the Auxiliary winding
6
Triple Insulated Wire: ø0.5mm for Secondary Winding
7
Tape: 0.05mm thick, 10mm wide
8
Glue: DELO AD895
7.5.4 Transformer Winding Construction Diagram
1
2
6
5
W5:
0.21mm 38Ts
W4:
0.16mm 17Ts
W3:
0.5mm 13Ts TIW
W2:
0.13mm 50Ts
WD1:
0.21mm 39Ts
0.21mm 40Ts
Black
White
1 layer 6
13mm tape
2
3
Figure 8. Transformer Winding Construction Diagram
Apr. 2012
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
12
Application Note 1066
Winding Sequence: Begin from the central column of the Bobbin. Primary side of the bobbin is placed on the
left hand side, and secondary side of the bobbin is placed on the right hand side.
W1
Start at Pin 3. Wind 40 turns of ø0.21 mm wire [4] from left to right. Wind another 39
Primary winding turns on the next layer from right to left. Finish on Pin 2. Wind tightly & spread evenly.
Insulation
1 Layer of insulation tape [7], 0.05mm thick, 10.0mm wide.
W2
Shielding
winding
Start at Pin 6. Wind 62 turns of ø0.16mm wire [3] from left to right. The terminal floats.
Wind tightly & spread evenly.
Insulation
2 Layers of insulation tape [7], 0.05mm thick, 10.0mm wide.
W3 Secondary
Winding
Start at white terminal. Wind 13 turns of ø0.5mm Triple Insulated Wire [6] from left to
right. Finish with black terminal. Wind tightly & spread evenly.
Insulation
2 Layers of insulation tape [7], 0.05mm thick, 10.0mm wide.
W4
Auxiliary
winding
Start at Pin 5. Wind 17 turns of ø0.16mm wire [5] from left to right. Finish on Pin 6.
Wind tightly & spread evenly.
Insulation
1 Layer of insulation tape [7], 0.05mm thick, 10.0mm wide.
W5
Primary winding
Insulation
Glue
Start at Pin 2. Wind 38 turns of ø0.21mm wire [4] from left to right, Finish on Pin 1.
Wind tightly & spread evenly.
2 Layers of insulation tape [8], 0.05mm thick, 10.0mm wide.
Glue[8] core and bobbin
Core short to Pin5
7.6 PCB Layout
Figure 9. Demo Board PCB and Component Layout (Top View)
Apr. 2012
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
13
Application Note 1066
Figure 10. Demo Board PCB and Component Layout (Bottom View)
7.7 Test Result
7.7.1 Full Load Efficiency
Input Condition
PIN (W)
VO (VDC)
IO (ADC)
PO (W)
Efficiency
120VAC/60Hz
9.79
12.58
0.614
7.91
80.8%
230VAC/50Hz
9.63
12.58
0.614
7.93
82.3%
7.7.2 Output Current Regulation
Apr. 2012
Output Current (A)
3 LEDs
4 LEDs
5 LEDs
Load
Regulation (%)
85
0.622
0.610
0.594
2.30%
100
0.623
0.612
0.595
2.30%
110
0.623
0.613
0.596
2.21%
120
0.623
0.613
0.596
2.21%
130
0.623
0.613
0.596
2.21%
150
0.622
0.613
0.597
2.05%
170
0.621
0.614
0.597
1.97%
190
0.620
0.614
0.599
1.72%
220
0.620
0.614
0.600
1.64%
230
0.619
0.614
0.600
1.56%
240
0.618
0.614
0.601
1.39%
265
0.615
0.612
0.601
1.15%
Line Regulation (%)
0.65%
0.33%
0.59%
2.38%
Input Voltage (VAC)
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
14
Application Note 1066
0.63
0.70
0.65
0.62
Output Current (A)
Output Current (A)
0.60
0.61
50Hz
60Hz
0.60
0.59
0.55
3LEDs
4LEDs
5LEDs
0.50
0.45
0.40
0.58
0.35
0.57
80
100
120
140
160
180
200
220
240
260
0.30
280
80
Input Voltage (V)
100
120
140
160
180
200
220
240
260
Input Voltage (Vac)
Figure 11. Line Regulation of Output Current
at Full Load
Figure 12. Load Regulation of Output Current
7.7.3 Power Factor and Harmonics
Figure 14. Full Load Power Factor & THD @ 230Vac
Figure 13. Full Load Power Factor & THD @ 120Vac
8. Non-isolated Buck-Boost Design Example
Nominal DC output voltage: VO=100V
Output constant current: IO=93mA
Expected efficiency: η> 90%
Here is another non-isolated Buck-Boost design example of
LED driver with AP1682 solution. The design specification is
8.1 The Specification
AC mains voltage range: VIN_ac = 85 to 265VRMS
Apr. 2012
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
15
Application Note 1066
8.2 The Non-isolated Buck-Boost Design Schematic
Figure 15. Typical Application Schematic of Non-isolated Solution with AP1682
8.3 The Material BOM List of Non-isolated Solution with AP1682
Item
QTY
C1
33nF/400V, X-capacitor
1
C2
100nF/400V, capacitor CL21
1
C3
100pF/16V, 0603, ceramic capacitor
1
C4
330nF/16V, 0603, ceramic capacitor
1
C5
1µF/25V, 1206, ceramic capacitor
1
C7
33µF/160V, 105°C, 10mm*20mm electrolytic capacitor
1
D1
Diode, 1N4148, SOD-323
1
D3
ES1J, 1A/600V, SMA
1
4.7mH, Inductor,Φ8mm*12.5mm
2
F1
Fuse, 1.25A/250V
1
VR1
Varistor 07D471K
1
BD1
0.5A/600V,TO-269AA,MB6S
1
R1,R2
10KΩ, 5%, 1206, resistor
2
R3, R4
750KΩ, 1%,1206, resistor
2
R5
4K7Ω, 1%, 0603, resistor
1
R6
12KΩ, 1%,0603, resistor
1
R7
330KΩ, 5%,0603, resistor
1
L1,L2
Apr. 2012
Description
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
16
Application Note 1066
Item
Apr. 2012
Description
QTY
R8, R9
750KΩ, 5%,1206, resistor
2
R10
100KΩ, 5%,0603, resistor
1
R11
20Ω, 5%,0603 , resistor
1
R12
3KΩ, 5%,0603 , resistor
1
R13
1R5, 1%,1206 , resistor
1
R14
1R6, 1%, 1206, resistor
1
R15
10Ω, 5%, 0805, resistor
1
R16
56KΩ, 1%,0603 , resistor
1
R17
12KΩ, 1%,0603 , resistor
1
R18
680KΩ, 5%,1206, resistor
1
R20
8M2, 5%, 1206, resistor
1
T1
EE16-7.2 6 pin 1.3mH, 5%,Transformer
1
U1
AP1682MTR-G1, SOIC-8, BCD’s IC
1
Q1
MOSFET, Infineon, SPI04N60, 4A/600V ,TO-251
1
Rev. 2. 0
BCD Semiconductor Manufacturing Limited
17