AN1075

Application Note 1075
Design of Power Factor Correction Circuit Using AP1662
Prepared by Wang Zhao Kun
System Engineering Department
1. Introduction
2. Product Features
The AP1662 is an active power factor control IC
which is designed mainly for use as a pre-converter in
electronic ballasts, AC-DC adapters and off-line SMPS
applications. The AP1662 includes an internal start-up
timer for stand-alone applications, a one-quadrant multiplier to realize near unity power factor and a zero current detector to ensure DCM boundary conduction
operation. The totem pole output stage is capable of
driving Power MOSFET with 600mA source current
and 800mA sink current.
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Designed with the advanced BiCMOS process, the
AP1662 features low start-up current, low operation
current and low power dissipation. The AP1662 also
has rich protection features including over-voltage protection, input under-voltage lockout with hysteresis
and multiplier output clamp to limit maximum peak
current.
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COMP
INV
CS
3
4
Multiplier
Voltage
Regulation
VCC
MULT
2
1
Zero Current Detection Control for DCM Boundary Conduction Mode
Adjustable Output Voltage with Precise OverVoltage Protection
Low Start-up Current with 40µA Typical Value
Low Operating Supply Current with 2.5mA Typical Value
1% Precise Internal Reference Voltage
Internal Start-up Timer
Disable Function for Reduced Current
Consumption
Totem Pole Output with 600mA Source Current
and 800mA Sink Current
Under-Voltage Lockout with 2.5V of Hysteresis
Overvoltage
Detection
11V
8
Internal
R1 Supply 7.5V
24V
R2
VCC
R Q
S
7
Driver
Vref
GD
Zero Current
Detector
2.1V
1.6V
Starter
Enable
Disable
6
5
ZCD
GND
Figure 1. Functional Block Diagram of AP1662
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Application Note 1075
3. Pin Descriptions
age must exceed the start-up threshold voltage (13V
max.).
INV (Pin 1): This pin is the inverting input of the
error amplifier. It is connected to an external resistor
divider which senses the output voltage.
VIN
Voltage
Regulation
COMP (Pin 2): This pin is the error amplifier output,
it is made available for voltage loop compensation by
resistor and capacitor combination between pin 1 and
this pin.
VCC
8
24V
UVLO
VREF
MULT (Pin 3): Input of the multiplier. This pin senses
the AC sinusoidal voltage and is multiplied with the
COMP pin voltage.
Figure 2. Supply Block
Error Amplifier
The error amplifier regulates the PFC output
voltage. The internal reference on the non-inverting
input of the error amplifier is 2.5V. The error
amplifier's inverting input (INV) is connected to an
external resistor divider which senses the output
voltage. The output of the error amplifier is one of the
two inputs of multiplier. A compensation loop is
connected outside between the INV and the error
amplifier output. Normally, the compensation loop
bandwidth is set very low to realize a high power
factor for the PFC converter.
CS (Pin 4): Input of the current control comparator.
This pin senses the power switch current and
meashures it against the output of the multiplier. When
the CS pin voltage is higher than the output of the
multiplier, the gate driver signal will become low to
turn off the external MOSFET.
ZCD (Pin 5): Zero current detection input. When the
ZCD pin voltage decreases below 1.6V, the gate drive
signal becomes too high to turn on the external MOSFET. If it is connected to GND, the device is disabled.
GND (Pin 6): Ground. Current return for gate driver
and control circuits of the IC.
To ensure fast over voltage protection, the internal
OVP function is added. If the output over voltage
occurs, excess current will flow into the output pin of
the error amplifier through the feedback compensation
capacitor. (see Figure 3) The AP1662 monitors the
current flowing into the error amplifier output pin.
When the detected current is higher than 40µA, the
dynamic OVP is triggered. The IC will be disabled
and the driver signal will be stopped. If the output over
voltage lasts so long that the output of the error
amplifier goes below 2.25V, static OVP will take
place. Also the IC will be disabled until the error
amplifier returns to its linear region.
GD (Pin 7): Gate driver output. A series resistor
between this pin and the power switch gate can reduce
high frequency noise.
VCC (Pin 8): Supply voltage of gate driver and control circuits of the IC.
4. Functional Block Descriptions
Supply Block
As shown in Figure 2, pin 8 is the VCC of AP1662.
There is a zener diode with typical 24V clamp voltage
(30 mA rated) to protect the device. A voltage
regulator generates a 7.5V voltage to function as the
IC's internal supply. It also produces a precise internal
reference voltage (2.5V±1% at 25oC)
R1 and R2 (see Figure 3) will be selected as below:
R1
Vo
=
−1
R 2 2.5V
R1 =
∆VOVP
40µA
Pin 2 (COMP) is the output of the error amplifier. A
feedback low bandwidth compensation network is
A hysteresis comparator detects the VCC pin's voltage. As long as the VCC voltage is high enough, the
driver is enabled. To start the AP1662, the VCC voltJan. 2012 Rev. 1. 0
BCD Semiconductor Manufacturing Limited
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Application Note 1075
placed between this pin and the INV (pin 1) to avoid
output voltage ripple influence to the system.
R Q
S
In the simplest case, this compensation is just a
capacitor, which provides a low frequency pole as
well as a high DC gain. A simple method to define the
capacitance value is to provide about 20dB attenuation
at twice line frequency (100Hz):
Zero Current
Detector
2.1V
1.6V
Starter
120µA
0.2V
CCOMP =
10
2π ⋅ R1
VO
5
Error
Amplifier
INV 1
COMP
MULT
2
3
Multiplier
Figure 4. Zero Current Detection, Triggering
PWM
and Disable Block
2.25V
OVP
Current
Detector
Vin
Driver
IOVP
2.5V
R2
ZCD
Disable
L
I
R1
Driver
IOVP
Vds
Vo
+
Vinpk
40µA
AP1662
t
VZCD
Figure 3. Error Amplifier and OVP Block
2.1V
1.6V
0.7V
Zero Current Detection (Figure 4)
AP1662 is a DCM boundary conduction current
mode PFC controller. Usually, the zero current detection (ZCD) voltage signal comes from the auxiliary
winding of the boost inductor. When the ZCD pin
voltage decreases below 1.6V, the gate drive signal
becomes too high to turn on the external MOSFET.
500 mV of hysteresis is provided to avoid false triggering.
t
iL
t
Figure 5. Optimum MOSFET Turn-on
The boost inductor winding turn ratio, m, should be
selected to ensure ZCD pin voltage is higher than 2.1V
during MOSFET turned-off. Then
m≤
t
VGD
valley of the drain voltage oscillation (When the boost
inductor current reaches zero, the inductor will oscillate with the MOSFET drain capacitance. (see Figure
5)). This will minimize the MOSFET power dissipation when turned-on.
VO − 2 ⋅ VINRMS (MAX )
2 .1
An internal starter generates a pulse to the gate of the
MOSFET at first start-up. The frequency of the pulse
is about 14 kHz.
A resistor is placed between the auxiliary winding
and ZCD pin to limit the current sink to the IC. The
limiting resistor's actual value can be fine-tuned to
make the turn-on of the MOSFET occur exactly on the
If the ZCD pin is driven by an external signal, the
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Application Note 1075
AP1662 will be synchronized to (the negative-going
edges of) that signal. If left floating, the AP1662 will
work at the frequency of its internal starter.
R3
Q
The ZCD pin can be used for disabling the IC. Making its voltage below 0.15V or short to the ground will
disable the device thus reducing the IC supply current
consumption.
R4
Rs
MULT
COMP
2
Error
Amplifier
Multiplier Block (Figure 6)
The multiplier has two inputs. One (Pin 3) is the
divided AC sinusoidal voltage which makes the current sense comparator threshold voltage vary from
zero to peak value. The other input is the output of the
error amplifier (Pin 2). In this way, the input average
current wave will be sinusoidal as well as reflect the
load status. Accordingly, a high power factor and low
THD are achieved. The multiplier transfer character is
designed to be linear over a wide dynamic range,
namely, 0 V to 3V for Pin 3 and 2.0 V to 5.8 V for Pin
2. The relationship between the multiplier output and
inputs is described as the following equation:
CS
3
4
Multiplier
1.7V
Current Sense
Comparator
R Q
S
Figure 6. Multiplier Block
1.8
VCOMP=2.6V
1.6
VCOMP=2.8V
VCS (V)
1.4
VCS = k × (VCOMP − 2.5) × VMULT
where VCS (Multiplier output) is the reference for the
current sense, k is the multiplier gain, VCOMP is the
voltage on pin 2 (error amplifier output) and VMULT is
the voltage on pin 3.
VCOMP=3V
1.2
VCOMP=3.2V
1.0
VCOMP=3.5V
VCOMP=4V
0.8
VCOMP=4.5V
0.6
VCOMP=5V
0.4
VCOMP=Max
0.2
0.0
0
1
2
3
4
VMULT (V)
Figure 7. Multiplier Characteristics Family
Figure 7 shows the typical multiplier characteristics
family. The linear operation of the multiplier is guaranteed to be in the range of 0 to 3V of VMULT and 0 to
1.6V of VCS.
Current Comparator and PWM Latch (Figure 6)
The PFC switch's turn-on current is sensed through
an external resistor in series with the switch. When the
sensed voltage exceeds the threshold voltage (the multiplier output voltage), the current sense comparator's
output will become low and the external MOSFET
will be turned off. This ensures a cycle-by-cycle current mode control operation.
VMULTpk, the peak value for VMULT, will occur at
maximum mains voltage, should be 3V or below. The
MULT pin resistor divider (see Figure 6) will be as
follows:
The sense resistor value is calculated as follows:
VMULTpk
R4
=
R3 + R 4
2 ⋅ VINRMS ( MAX )
RS ≤
The AP1662 is equipped with a special circuit that
reduces the AC input current conduction dead-angle
near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced.
VCSpk
I CSpk
where VCSpk is the maximum voltage of VCS, can be
set 1.6V for linear operation in the entire working
range. The maximum current sense reference is 1.8V.
The maximum value usually occurs during the startup
process or abnormal conditions such as short load.
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Application Note 1075
Boost Inductor
Through the following calculation, the
instantaneous switching frequency along a line cycle
equation can be found:
When the power MOSFET is turned on, a narrow
spike on the leading edge of the current waveform can
usually be observed. There is an internal R/C filter in
AP1662 to attenuate this noise and prevent the false
triggering caused by the turn-on spike. In low power
applications, the external R/C filter connected to the
CS pin is not needed.
f sw (θ ) =
Driver
The AP1662 totem pole output stage is capable of
driving a Power MOSFET or IGBT with 600mA
source current and 800mA sink current.
2
(VO − 2 ⋅ VINRMS ⋅ sin(θ )) ⋅ VINRMS
⋅η
2 ⋅ L ⋅ PO ⋅ VO
The switching frequency will be at the minimum
level at the top of the sinusoid and at the maximum
level at the zero crossings of the line voltage. Figure
10 shows an example of the switching frequency
changing during the half line cycle.
GND
Pin 6 is the Ground of the IC. This pin acts as the
current return both for the internal circuitry signal and
for the gate drive current. These two paths should be
laid out separately in the printed circuit board.
The absolute minimum frequency fSW(MIN) can
occur at either the maximum or the minimum mains
voltage. Thus the inductor value is defined by:
2
⋅η
(VO − 2 ⋅ VINRMS ) ⋅ VINRMS
L=
2 ⋅ f SWMIN ⋅ PO ⋅ VO
5. Boost Circuit Basic Design
The most popular power factor correction topology
is the Boost circuit. The boost converter consists of a
boost inductor (L), a controlled power switch (Q), a
diode (D), an output capacitor (CO) and a control
circuit (see Figure 8).
where VINRMS can be either VINRMS(MIN) or VINRMS(MAX). The lower value for L can be selected.
The suggested minimum switching frequency is
greater than the frequency of the internal starter
(15kHz) to ensure a correct DCM boundary Conduction Mode operation.
The goal of the PFC is to shape the input current in
a sinusoidal waveform, in-phase with the input
sinusoidal voltage.
To do this, the AP1662 uses the so-called DCM
boundary Conduction Mode technique. Figure 9
shows the inductor current waveform and MOSFET
gate drive signal. During a line frequency period, the
turn-on time of MOSFET is kept constant, thus the
inductor peak current is in track with input sinusoidal
voltage waveform. When MOSFET turns off, the
inductor current will decrease. Just after the inductor
current reaches zero, MOSFET will turn on again.
The maxim inductor current is:
I LMAX _ pk =
2 2 ⋅ VO ⋅ I O
η ⋅VINRMS ( MIN )
By AP method, we can select a type of core. Then
the inductor primary turns can be calculated according
L
VIN ~
CIN
D
Q
AP1662
CO
Load
Figure 8. Boost Converter Circuit
BCD Semiconductor Manufacturing Limited
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Application Note 1075
output capacitor. In addition, a high frequency ripple
will appear on the ESR of the output capacitor due to
Boost converter switching.
to the following methods:
N=
L ⋅ I LMAX _ PK
B max⋅ AE
To select Bmax according to characteristics of ferrite
core and margin consideration of saturation flux
density.
∆VO = I O ⋅
1
2
+ ESRCO
(4π ⋅ f AC ⋅ CO ) 2
With a low ESR capacitor,
iLpk
CO ≥
iLavg
iL
PO
4π ⋅ f AC ⋅ CO ⋅ ∆VO
If the load is resistive, the ripple current of the output capacitor is:
2
I CO ( RMS ) =
vgs
t
V
32 2 ⋅ PO
− ( O )2
2
RO
9π ⋅η ⋅ VINRMS ⋅ VO
6. Layout Considerations
Figure 9. Boost Inductor Current
in DCM Boundary Conduction Mode
There are some considerations when laying out the
PCB of the PFC circuit.
250
The power switching circuit loop should be as small
as possible. In Boost circuit, when MOSFET turns on,
there is a current flow loop including a rectifying
bridge, Boost inductor and MOSFET. When the MOSFET turns off, the current flow loop includes the Boost
inductor, diode and output capacitor. The two loops
should be small to avoid high frequency radiation
noise.
Frequency(kHz)
200
150
100
50
0
0
30
60
90
120
150
180
Degrees
Figure 10. Switching Frequency in Half Line Cycle
Output Capacitor
The output bulk capacitor (CO) selection depends on
the DC output voltage, the allowed overvoltage, the
output voltage ripple and ripple current on the capacitor.
To achieve a high power factor, the output voltage
feedback control loop is slow. As a result, there is
twice the mains frequency voltage ripple across the
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The connection between the power and signal GND
should be a single point connection. Common connection of GND will introduce disturbances to small signals. Figure.11 shows the ideal ground connection
diagram. The power ground and signal ground should
be separated. The IC ground (GND) should connect
directly to the power ground of the PFC MOSFET current sense resistor; the shorter the track is, the better
the IC works. The VCC capacitor C2 and C3 should be
placed close to pin 8 to ensure good noise suppression.
The drain of the MOSFET has high dv/dt when
switching. The control circuit including AP1662
should be kept away from it. If the MOSFET sticks to
a heat sink, the heat sink should be connected to the
power GND.
BCD Semiconductor Manufacturing Limited
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Application Note 1075
DC
BUS
R1
VIN
1
INV
8 VCC
R3
C2
D1
GD 7 R5
Q
R6
AP1662
C3
3
MULT
Co
CS 4
GND
6
R4
Rs
R2
Signal
GND
Power
GND
Figure 11. Correct GND Connection for AP1662 in PCB
BCD Semiconductor Manufacturing Limited
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