AN22

Application Note 22
Issue 1 May 1996
High Frequency DC-DC Conversion using High
Current Bipolar Transistors
400kHz Operation with Optimised Geometry Devices
Neil Chadderton
Dino Rosaldi
Introduction
DC-DC conversion is o n e o f t h e
fundamental circuit functions within the
electronics industry and addresses a
wide field of market sectors,
applications and supply requirements. A
general trend, (to pursue cost, size and
reliability advantages) has been to
reduce the size of the DC-DC converter
systems, and as the inductive elements
of such a system are quite often the
bulkiest components, increases in
s w i t c h i n g f r e q u e nc y p r ov i d e o n e
method to allow this. Switching
frequencies therefore have increased
from tens of kHz to hundreds of kHz,
which has forced a revision of the
enabling switching devices.
It is an often assumed maxim that
bipolar transistors are useful for DC-DC
conversion functions up to perhaps
50kHz, and for service beyond this
frequency, that MOSFETs provide the
only solution. The purpose of this
application note is to demonstrate that
bipolar transistors possessing superior
geometrys - thereby providing a higher
current capability per die area, can and
are operated to reasonably high
switching frequencies with minimal
loss. This often allows a more compact
de s i gn (du e to the higher s ilicon
efficiency of bipolar technology) and
lower cost.
Background
To obtain the most efficient performance
f r o m b i p o l a r t r a n s i s to r s a t h i g h
switching frequencies, an appreciation
of the basic switching mechanisms and
base charge analysis is useful. Appendix
A provides an introduction to bipolar
transistor switching behaviour, and
appendix B provides references for
mathematical treatments.
There are various methods for
increasing the maximum switching
speed of bipolar transistors. Some of
these rely on preventing saturation of
the device, thus vastly reducing the
stored charge, while other methods
remove the charge at turn-off. Figures 1,
2 and 5 show a number of common
speed-up networks. Figures 1a through
1d show various options for preventing
saturation, and effectively reduce/limit
base drive when the collector terminal
has fallen to a specific level. (Figure 1a is
often termed a Schottky transistor, and
is often used for IC transistors, and
AN22 - 1
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
ZTX789A
Input
Q3
Q1 1K
2N3904
Q1
L2
200uH
1N5820
+Bat
100uF
Q1
L1
10uH
Q2
a
b
Q2
2N3904
Drive
D3
R1
R2
Feedback
D2
330
Q1
Q1
D1
c
1N4148
R3
C1
d
Figure 2.
PNP Transistor Speed-up Circuit to Allow Replacement of P-Channel MOSFETs within
High Current Converters. (The circuit shown is suitable for output currents up to 1.5A;
other variants are capable of operation to 5A output).
Figure 1.
Non-saturating Bipolar Transistor Speed-up Methods.
Figures 1c and 1d are variants of the so
called Baker clamp circuit).
These methods (the Baker clamp being
preferred for high power applications) of
course do not allow the transistor’s
collector-emitter voltage to saturate to a
very low level, and so the resultant
on-state loss may be high and therefore
prohibit the use of smaller packaged,
though adequately current capable
devices. Figures 2 and 5 show two
methods that allow true saturation by
permitting sufficient forward base drive,
while removing charge quickly at turn-off.
Design of such networks is non-critical,
and by suitable choice of components
allow high levels of base overdrive with no
penalty to turn-off time duration.
Figure 2 shows a method of speeding up
PNP devices to enable replacement of
large P-Channel MOSFETs - this particular
circuit being designed for fast charging of
ba tte ry
pa cks
by
Benchmarq
Microelectronics. Figures 3 and 4 show the
relevant waveforms, for a standard
passive turn-off method (base-emitter
pull-up resistor) and the speed-up circuit
of Figure 2 - the combined storage and fall
times being reduced from 1.2µs to 80ns.
Importantly, the major switching loss
contributor - the fall time, has been
significantly reduced to 40ns, which is
comparable to, or better than P-Channel
MOSFET performance. This allows cost
effective replacement of large packaged
devices.
AN22 - 2
Figure 3.
Turn-off Waveforms for PNP Step-down
Converter using Passive Turn-off.
Upper Trace - Collector-to-0V, 5V/div;
Middle Trace - PNP base-to-0V;
Lower Trace - PWM IC Output, 5v/div.
Timebase at 2µs/div.
Figure 4.
Turn-off Waveforms for PNP Step-down
Converter (of Figure 2) using Active
Turn-off.
Upper Trace - Collector-to-0V, 5V/div;
Middle Trace - PNP base-to-0V;
Lower Trace - PWM IC Output, 5v/div.
Timebase at 2µs/div.
AN22 - 3
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
ZTX789A
Input
Q3
Q1 1K
2N3904
Q1
L2
200uH
1N5820
+Bat
100uF
Q1
L1
10uH
Q2
a
b
Q2
2N3904
Drive
D3
R1
R2
Feedback
D2
330
Q1
Q1
D1
c
1N4148
R3
C1
d
Figure 2.
PNP Transistor Speed-up Circuit to Allow Replacement of P-Channel MOSFETs within
High Current Converters. (The circuit shown is suitable for output currents up to 1.5A;
other variants are capable of operation to 5A output).
Figure 1.
Non-saturating Bipolar Transistor Speed-up Methods.
Figures 1c and 1d are variants of the so
called Baker clamp circuit).
These methods (the Baker clamp being
preferred for high power applications) of
course do not allow the transistor’s
collector-emitter voltage to saturate to a
very low level, and so the resultant
on-state loss may be high and therefore
prohibit the use of smaller packaged,
though adequately current capable
devices. Figures 2 and 5 show two
methods that allow true saturation by
permitting sufficient forward base drive,
while removing charge quickly at turn-off.
Design of such networks is non-critical,
and by suitable choice of components
allow high levels of base overdrive with no
penalty to turn-off time duration.
Figure 2 shows a method of speeding up
PNP devices to enable replacement of
large P-Channel MOSFETs - this particular
circuit being designed for fast charging of
ba tte ry
pa cks
by
Benchmarq
Microelectronics. Figures 3 and 4 show the
relevant waveforms, for a standard
passive turn-off method (base-emitter
pull-up resistor) and the speed-up circuit
of Figure 2 - the combined storage and fall
times being reduced from 1.2µs to 80ns.
Importantly, the major switching loss
contributor - the fall time, has been
significantly reduced to 40ns, which is
comparable to, or better than P-Channel
MOSFET performance. This allows cost
effective replacement of large packaged
devices.
AN22 - 2
Figure 3.
Turn-off Waveforms for PNP Step-down
Converter using Passive Turn-off.
Upper Trace - Collector-to-0V, 5V/div;
Middle Trace - PNP base-to-0V;
Lower Trace - PWM IC Output, 5v/div.
Timebase at 2µs/div.
Figure 4.
Turn-off Waveforms for PNP Step-down
Converter (of Figure 2) using Active
Turn-off.
Upper Trace - Collector-to-0V, 5V/div;
Middle Trace - PNP base-to-0V;
Lower Trace - PWM IC Output, 5v/div.
Timebase at 2µs/div.
AN22 - 3
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
+5V
measurements for the ZTX1048A - for
example, at a collector current of 1A and
a forced gain of 200, a turn-off charge of
900pC is required to neutralise stored
charge and eliminate storage time
effects.
100n
ZTX1048A
C
To Oscilloscope
Q1
+5V
Input
RB
0V
0V
Figure 5.
Capacitive Speed-up method/Circuit to Determine Minimum Value of Turn-Off Charge
of a Bipolar Transistor.
Stored Charge (C)
IC/IB=50
RC
IC/IB=100
IC/IB=150
IC/IB=200
10n
[Note 1: Appendix A also includes some
ancillary material on the minimum
amount of trigger charge necessary for
pulse circuits].
1n
0.1
1
10
IC - Collector Current (A)
Power Conversion Circuits
Stored Charge v IC
Figure 8.
Turn-off Charge Required as a Function of
Collector Current and Forced Gain, for the
ZTX1048A Bipolar Transistor.
Figure 5 shows the standard speed-up
c a p a c i t a n c e m e t h o d , a l t h o u gh i n
practice a finished design would use a
fixed value capacitor. A similar circuit
can also be used to determine the
capacitance required for a particular bias
condition. In practise the variable
capac itance (or value of parallel
capacitance) is adjusted such that the
sum of stored charge and junction
capacitance charge is just removed allowing for device variation,
temperature and bias tolerance.
Figure 6.
Turn-Off Waveforms, and Effect of
Va ry ing
Pa r a lle l
(“S p eed -Up ”)
Capacitance.
Upper trace - Input waveform;
lower traces - (a) C=0, (b) C=100pF,
(c) C=120pF, (d) C=130pF (stored charge
just removed).
Figure 7.
Turn-Off Waveforms, and Effect of
V aryi n g
Par allel
(“S peed-Up”)
Capacitance.
Trace (a) - Input waveform;
turn-off traces - (b) C=0, (c) C=470pF, (d)
C=820pF, (e) C=1.5nF (stored charge
removed).
Horizontal scale=200ns/div, Vertical
scale=2V/div. ZTX300, IB=1mA, IC=10mA.
Horizontal scale=500ns/div, Vertical
scales: Input=2V/div; collector=5V/div.
ZTX1048A, IB=10mA, IC=500mA.
AN22 - 4
The oscillographs in Figures 6 and 7
show the effec t of increasing the
capacitor value from zero (Eg. open
circuit) to a value adequate to neutralise
the stored charge. Figure 6 is for a small
signal device, while Figure 7 is for the
ZTX1048A - a transistor utilising the
Zetex Matrix geometry, and a Super-β
emitter process to produce a 4A DC rated
part in the TO92 style E-Line package.
Figure 8 summarises a set of such
T o d e m o n s t r a t e t he p e r f or m a nc e
advantages possible when the bipolar
transistor’s turn-off charge is addressed,
this
section
considers
such
modifications to a basic step-down
DC-DC converter. The circuit shown in
Figure 9 was used to provide a means of
evaluation, and is of fairly standard
implementation, apart from the choice
of the FMMT718 SuperSOT SOT23 PNP
transistor. This circuit, with minimal
design optimisation, can produce the
efficiency against load current
characteristic shown in Figure 10. This
chart also shows how the bias
conditions for the pass device can be
modified to increase the current
capability of the circuit, albeit with some
compromise to conversion efficiency at
lower load currents. Curves 1, 2 and 3
illustrate this effect for base currents of
9.4mA, 43mA and 170mA respectively.
Figure 11 shows how the efficiency
varies with input voltage for the IB=43mA
option. Higher output current designs
are possible with larger die transistors
from the Zetex range, such as the
ZTX788B, ZTX789A, ZTX790A, ZTX948
and ZTX949. For a comprehensive listing
please refer to Semiconductor Data
Books one and two.
AN22 - 5
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
+5V
measurements for the ZTX1048A - for
example, at a collector current of 1A and
a forced gain of 200, a turn-off charge of
900pC is required to neutralise stored
charge and eliminate storage time
effects.
100n
ZTX1048A
C
To Oscilloscope
Q1
+5V
Input
RB
0V
0V
Figure 5.
Capacitive Speed-up method/Circuit to Determine Minimum Value of Turn-Off Charge
of a Bipolar Transistor.
Stored Charge (C)
IC/IB=50
RC
IC/IB=100
IC/IB=150
IC/IB=200
10n
[Note 1: Appendix A also includes some
ancillary material on the minimum
amount of trigger charge necessary for
pulse circuits].
1n
0.1
1
10
IC - Collector Current (A)
Power Conversion Circuits
Stored Charge v IC
Figure 8.
Turn-off Charge Required as a Function of
Collector Current and Forced Gain, for the
ZTX1048A Bipolar Transistor.
Figure 5 shows the standard speed-up
c a p a c i t a n c e m e t h o d , a l t h o u gh i n
practice a finished design would use a
fixed value capacitor. A similar circuit
can also be used to determine the
capacitance required for a particular bias
condition. In practise the variable
capac itance (or value of parallel
capacitance) is adjusted such that the
sum of stored charge and junction
capacitance charge is just removed allowing for device variation,
temperature and bias tolerance.
Figure 6.
Turn-Off Waveforms, and Effect of
Va ry ing
Pa r a lle l
(“S p eed -Up ”)
Capacitance.
Upper trace - Input waveform;
lower traces - (a) C=0, (b) C=100pF,
(c) C=120pF, (d) C=130pF (stored charge
just removed).
Figure 7.
Turn-Off Waveforms, and Effect of
V aryi n g
Par allel
(“S peed-Up”)
Capacitance.
Trace (a) - Input waveform;
turn-off traces - (b) C=0, (c) C=470pF, (d)
C=820pF, (e) C=1.5nF (stored charge
removed).
Horizontal scale=200ns/div, Vertical
scale=2V/div. ZTX300, IB=1mA, IC=10mA.
Horizontal scale=500ns/div, Vertical
scales: Input=2V/div; collector=5V/div.
ZTX1048A, IB=10mA, IC=500mA.
AN22 - 4
The oscillographs in Figures 6 and 7
show the effec t of increasing the
capacitor value from zero (Eg. open
circuit) to a value adequate to neutralise
the stored charge. Figure 6 is for a small
signal device, while Figure 7 is for the
ZTX1048A - a transistor utilising the
Zetex Matrix geometry, and a Super-β
emitter process to produce a 4A DC rated
part in the TO92 style E-Line package.
Figure 8 summarises a set of such
T o d e m o n s t r a t e t he p e r f or m a nc e
advantages possible when the bipolar
transistor’s turn-off charge is addressed,
this
section
considers
such
modifications to a basic step-down
DC-DC converter. The circuit shown in
Figure 9 was used to provide a means of
evaluation, and is of fairly standard
implementation, apart from the choice
of the FMMT718 SuperSOT SOT23 PNP
transistor. This circuit, with minimal
design optimisation, can produce the
efficiency against load current
characteristic shown in Figure 10. This
chart also shows how the bias
conditions for the pass device can be
modified to increase the current
capability of the circuit, albeit with some
compromise to conversion efficiency at
lower load currents. Curves 1, 2 and 3
illustrate this effect for base currents of
9.4mA, 43mA and 170mA respectively.
Figure 11 shows how the efficiency
varies with input voltage for the IB=43mA
option. Higher output current designs
are possible with larger die transistors
from the Zetex range, such as the
ZTX788B, ZTX789A, ZTX790A, ZTX948
and ZTX949. For a comprehensive listing
please refer to Semiconductor Data
Books one and two.
AN22 - 5
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
FMMT
718
220uH
+5V/
+3.3V
220
80
Efficiency (%)
30K
150
LL5818
0.05
ILim
C
Vin
470uF
-ve
Vin
22pF
PWM IC
1000uF
E
2
40
Osc
10
0.01
7K5/
220pF 13K
(Set Vout)
1.8n
Figure 9.
Basic Step-Down DC-DC Converter using the LM3578 and the FMMT718.
(With values shown, Fop=50kHz, IB=43mA, peak efficiency=88%).
10
Figure 12.
Efficiency against Load Current for the
Converter of Figure 9.
IB=43mA; Fop=90kHz; Vin=7V; Vout=5V.
Effect of Variation of Inductor Value.
Curve 1 - 25µH, Curve 2 - 180µH.
100
80
1
Efficiency v Output Current
0V
100
0.1
Output Current (A)
0V
To investigate optio ns for higher
switching frequencies requires a change
to the PWM controller IC. Figure 13
shows a circuit based on the TI5001
device. This IC is capable of operation up
to a switching frequency of 400kHz, and
can sink a maximum of 20mA into the VO
pin.
The initial circuit was configured to
operate at 150kHz, with the FMMT718
base current set to 9mA by a 560Ω base
resistor (R1) - effectively a forced gain of
222 at 2A. Turn-on and turn-off times
were measured at 200ns and 1.44µs
80
1
Efficiency (%)
Efficiency (%)
1
60
20
470K
+ve
Gnd
Optimisation, and some scope for higher
frequency operation is possible with this
basic converter. Figure 12 shows the
effect of varying the inductors value,
with the switching frequency set to
90kHz. Turn-on time was recorded at
55ns, and turn-off at 1.5µs.
100
60
2
40
3
20
Vin
60
0.1uF
560
1000uF
ZTX718
40
L1
Vout
20
D1
470uF
1N5818
Vcc
10
0.01
0
0.1
1
5
10
7
9
11
13
Output Current (A)
Input Voltage (V)
Efficiency v Output Current
Efficiency v Input Voltage
Figure 10.
Efficiency against Load Current for the
Converter of Figure 9, with IB a s a
parameter.
Curve 1 - IB=9.4mA; Curve 2 - IB=43mA;
Curve 3 - IB=170mA. Fop=50kHz; Vin=7V;
Vout=5V.
15
Figure 11.
Efficiency against Input Voltage for the
Converter of Figure 9. (IB=43mA; Iout=1A).
AN22 - 6
40uH
R1
DTC
22k
Vo
SCP
TL5001
4.7nF
Comp
10nF
Rf
2k2
5k6
F/b
RT
5k6
Gnd
Figure 13.
Basic Step-Down DC-DC Converter using the TI5001 and the FMMT718. (With values
shown, Fop=150kHz, IB=9mA, peak efficiency=81%).
AN22 - 7
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
FMMT
718
220uH
+5V/
+3.3V
220
80
Efficiency (%)
30K
150
LL5818
0.05
ILim
C
Vin
470uF
-ve
Vin
22pF
PWM IC
1000uF
E
2
40
Osc
10
0.01
7K5/
220pF 13K
(Set Vout)
1.8n
Figure 9.
Basic Step-Down DC-DC Converter using the LM3578 and the FMMT718.
(With values shown, Fop=50kHz, IB=43mA, peak efficiency=88%).
10
Figure 12.
Efficiency against Load Current for the
Converter of Figure 9.
IB=43mA; Fop=90kHz; Vin=7V; Vout=5V.
Effect of Variation of Inductor Value.
Curve 1 - 25µH, Curve 2 - 180µH.
100
80
1
Efficiency v Output Current
0V
100
0.1
Output Current (A)
0V
To investigate optio ns for higher
switching frequencies requires a change
to the PWM controller IC. Figure 13
shows a circuit based on the TI5001
device. This IC is capable of operation up
to a switching frequency of 400kHz, and
can sink a maximum of 20mA into the VO
pin.
The initial circuit was configured to
operate at 150kHz, with the FMMT718
base current set to 9mA by a 560Ω base
resistor (R1) - effectively a forced gain of
222 at 2A. Turn-on and turn-off times
were measured at 200ns and 1.44µs
80
1
Efficiency (%)
Efficiency (%)
1
60
20
470K
+ve
Gnd
Optimisation, and some scope for higher
frequency operation is possible with this
basic converter. Figure 12 shows the
effect of varying the inductors value,
with the switching frequency set to
90kHz. Turn-on time was recorded at
55ns, and turn-off at 1.5µs.
100
60
2
40
3
20
Vin
60
0.1uF
560
1000uF
ZTX718
40
L1
Vout
20
D1
470uF
1N5818
Vcc
10
0.01
0
0.1
1
5
10
7
9
11
13
Output Current (A)
Input Voltage (V)
Efficiency v Output Current
Efficiency v Input Voltage
Figure 10.
Efficiency against Load Current for the
Converter of Figure 9, with IB a s a
parameter.
Curve 1 - IB=9.4mA; Curve 2 - IB=43mA;
Curve 3 - IB=170mA. Fop=50kHz; Vin=7V;
Vout=5V.
15
Figure 11.
Efficiency against Input Voltage for the
Converter of Figure 9. (IB=43mA; Iout=1A).
AN22 - 6
40uH
R1
DTC
22k
Vo
SCP
TL5001
4.7nF
Comp
10nF
Rf
2k2
5k6
F/b
RT
5k6
Gnd
Figure 13.
Basic Step-Down DC-DC Converter using the TI5001 and the FMMT718. (With values
shown, Fop=150kHz, IB=9mA, peak efficiency=81%).
AN22 - 7
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
respectively. The chart shown in Figure
14 (curve 1) illustrates the resultant
efficiency versus load profile. The
circuit’s conversion efficiency peaks at
81% at 23mA output, but falls thereafter
to 71% at 2A, due mainly to switching
losses, though in some part to
increasing VCE(sat) at higher currents. The
latter factor could be addressed in part
by considering the load requirements,
and optimising for the relevant
condition, but the switching losses
would remain.
Q2
100
R1
1
Efficiency (%)
80
60
2
C1
R2
Q1
D1
40
20
0
0.01
0.1
PWM IC
10
1
Figure 15.
Bipolar Transistor Turn-off Circuit to allow
Capacitive Turn-off Charge Neutralisation
with PWM Controller IC.
Output Current (A)
Efficiency v Output Current
Figure 14.
Efficiency against Load Current for the
Converters of Figure 13 and 16.
L1
FMMT718
Vin
40uH
Figure 17.
Switching Waveforms for the circuit of
Figure 16, operating at 150kHz. Upper
trace; 2V/div, Collector-to-0V. Lower
tr a ce ; 2V / d i v , B a s e- t o -0 V. Vin=7V,
Vout=5V, IL=220mA.
Vout
By considering the base turn-off charge
and effecting a suitable turn-off circuit
(Figure 15) the circuit shown in Figure 16
was produced. This shows a significant
improvement in conversion efficiency at
medium to higher currents; as shown in
100
D1
390
0.1uF
1000uF
FMMT3904
1N4148
1N5818
80
470uF
2.2nF
22k
Vcc
2k2
SCP
DTC
Rf
Vo
TL5001
RT
Comp
4.7nF
10nF 5k6
Efficiency (%)
560
3
1
60
2
5
4
40
20
F/b
5k6
Gnd
0
0.01
0.1
1
Output Current (A)
Figure 16.
Basic Step-down DC-DC Converter using the TI5001/FMMT718 Combination with
Capacitive Turn-off Circuit.
AN22 - 8
10
Figure 18.
Efficiency against Load Current for the Converter of Figure 16. Curve 1 - Fop=150kHz;
curve 2 - 220kHz; curve 3 - 300kHz; curve 4 - 400kHz. IB=10mA. Curve 5 - 400kHz and
IB=5mA.Vin=7V, Vout=5V.
AN22 - 9
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
respectively. The chart shown in Figure
14 (curve 1) illustrates the resultant
efficiency versus load profile. The
circuit’s conversion efficiency peaks at
81% at 23mA output, but falls thereafter
to 71% at 2A, due mainly to switching
losses, though in some part to
increasing VCE(sat) at higher currents. The
latter factor could be addressed in part
by considering the load requirements,
and optimising for the relevant
condition, but the switching losses
would remain.
Q2
100
R1
1
Efficiency (%)
80
60
2
C1
R2
Q1
D1
40
20
0
0.01
0.1
PWM IC
10
1
Figure 15.
Bipolar Transistor Turn-off Circuit to allow
Capacitive Turn-off Charge Neutralisation
with PWM Controller IC.
Output Current (A)
Efficiency v Output Current
Figure 14.
Efficiency against Load Current for the
Converters of Figure 13 and 16.
L1
FMMT718
Vin
40uH
Figure 17.
Switching Waveforms for the circuit of
Figure 16, operating at 150kHz. Upper
trace; 2V/div, Collector-to-0V. Lower
tr a ce ; 2V / d i v , B a s e- t o -0 V. Vin=7V,
Vout=5V, IL=220mA.
Vout
By considering the base turn-off charge
and effecting a suitable turn-off circuit
(Figure 15) the circuit shown in Figure 16
was produced. This shows a significant
improvement in conversion efficiency at
medium to higher currents; as shown in
100
D1
390
0.1uF
1000uF
FMMT3904
1N4148
1N5818
80
470uF
2.2nF
22k
Vcc
2k2
SCP
DTC
Rf
Vo
TL5001
RT
Comp
4.7nF
10nF 5k6
Efficiency (%)
560
3
1
60
2
5
4
40
20
F/b
5k6
Gnd
0
0.01
0.1
1
Output Current (A)
Figure 16.
Basic Step-down DC-DC Converter using the TI5001/FMMT718 Combination with
Capacitive Turn-off Circuit.
AN22 - 8
10
Figure 18.
Efficiency against Load Current for the Converter of Figure 16. Curve 1 - Fop=150kHz;
curve 2 - 220kHz; curve 3 - 300kHz; curve 4 - 400kHz. IB=10mA. Curve 5 - 400kHz and
IB=5mA.Vin=7V, Vout=5V.
AN22 - 9
Application Note 22
Issue 1 May 1996
Figure 14, curve 2. This shows a peak
efficiency of 92%. Figure 17 shows the
switching waveforms, including the
collector-to-0V waveform - note the
rapid turn-off edge; this was measured
to be 25ns. The efficiency at lower
currents has of course reduced, due to
the extra current taken by the turn-off
circuit. This efficiency profile can be
modified for specific applications by
sacrificing high current efficiency in
favour of low current performance or
vice-versa.
Further modifications were effected to
assess performance at still higher
switching frequencies. Figure 18 shows
the efficiency/load current profiles for
switching frequencies from 150kHz to
400kHz. Figure 19 shows the efficiency
against input voltage for the 220kHz
version - the curve varying little over the
measured range. Figure 18 curve 5, is
again for a switching frequency of
400kHz, but with lower base drive
(RB=680Ω) and a reduction to 1.5nF for
the turn-off capacitor. The oscillographs
shown in Figures 20 and 21 show the
turn-on and turn-off switching
waveforms for the 400kHz version.
These show collector rise and fall times
of 20ns and 30ns respectively.
Conclusions
Figure 20.
Switching Waveforms for the Converter
of Figure 16 operating at 400kHz.
Turn-on edges. Risetime= 20ns.
Upper trace - Base-to-0V, 2V/div.
Lower trace - Collector-to-0V, 2V/div.
Timebase at 50ns/div.
100
80
Efficiency (%)
Application Note 22
Issue 1 May 1996
This application note has demonstrated
that with due attention to the base and
collector charge phenomena in bipolar
transistors, the operating switching
frequency of those parts can be
extended well beyond the currently
accepted notional maximum of 40kHz, to
several hundred kHz. Various speed-up
methods have been summarised, and
examples of those particularly suitable
and complementary to high current
capable transistors examined, and
circuit examples presented.
60
40
20
0
5
7
9
11
13
15
Input Voltage (V)
Efficiency v Input Voltage
Figure 19.
Efficiency against Input Voltage for the
Converter of Figure 16.
Fop=220kHz; Vout=5V; load current=1A.
Figure 21.
Switching Waveforms for the Converter
of Figure 16 operating at 400kHz.
Turn-off edges. Falltime=30ns.
Upper trace - Base-to-0V, 2V/div.
Lower trace - Collector-to-0V, 2V/div.
Timebase at 50ns/div.
AN22 - 10
AN22 - 11
Application Note 22
Issue 1 May 1996
Figure 14, curve 2. This shows a peak
efficiency of 92%. Figure 17 shows the
switching waveforms, including the
collector-to-0V waveform - note the
rapid turn-off edge; this was measured
to be 25ns. The efficiency at lower
currents has of course reduced, due to
the extra current taken by the turn-off
circuit. This efficiency profile can be
modified for specific applications by
sacrificing high current efficiency in
favour of low current performance or
vice-versa.
Further modifications were effected to
assess performance at still higher
switching frequencies. Figure 18 shows
the efficiency/load current profiles for
switching frequencies from 150kHz to
400kHz. Figure 19 shows the efficiency
against input voltage for the 220kHz
version - the curve varying little over the
measured range. Figure 18 curve 5, is
again for a switching frequency of
400kHz, but with lower base drive
(RB=680Ω) and a reduction to 1.5nF for
the turn-off capacitor. The oscillographs
shown in Figures 20 and 21 show the
turn-on and turn-off switching
waveforms for the 400kHz version.
These show collector rise and fall times
of 20ns and 30ns respectively.
Conclusions
Figure 20.
Switching Waveforms for the Converter
of Figure 16 operating at 400kHz.
Turn-on edges. Risetime= 20ns.
Upper trace - Base-to-0V, 2V/div.
Lower trace - Collector-to-0V, 2V/div.
Timebase at 50ns/div.
100
80
Efficiency (%)
Application Note 22
Issue 1 May 1996
This application note has demonstrated
that with due attention to the base and
collector charge phenomena in bipolar
transistors, the operating switching
frequency of those parts can be
extended well beyond the currently
accepted notional maximum of 40kHz, to
several hundred kHz. Various speed-up
methods have been summarised, and
examples of those particularly suitable
and complementary to high current
capable transistors examined, and
circuit examples presented.
60
40
20
0
5
7
9
11
13
15
Input Voltage (V)
Efficiency v Input Voltage
Figure 19.
Efficiency against Input Voltage for the
Converter of Figure 16.
Fop=220kHz; Vout=5V; load current=1A.
Figure 21.
Switching Waveforms for the Converter
of Figure 16 operating at 400kHz.
Turn-off edges. Falltime=30ns.
Upper trace - Base-to-0V, 2V/div.
Lower trace - Collector-to-0V, 2V/div.
Timebase at 50ns/div.
AN22 - 10
AN22 - 11
Application Note 22
Issue 1 May 1996
In order to understand the requirement
for speed-up capacitors, consider the
simple inverter circuit shown in Figure
22, and the resultant switching
waveforms shown schematically in
Figure 23.
Appendix A
Bipolar Transistor Switching
Behaviour
In most swi tching circ uits tri gger
capacitors are required to differentiate
pulses and provide DC isolation between
stages, and speed-up capacitors are
needed to neutralise the stored charge
a n d j u n c t i o n c a p a c i ta nc e s o f th e
transistors. In most cases it is sufficient
to choose values small enough not to
interfere with the operation of the circuit
at its maxi mum freque ncy . The se
capacitors do however have minimum
v a l u e s d e p e nd in g on t he ty pe o f
transistor used, the base and collector
currents, and the amplitude of the
waveforms involved.
+5V
Initially Q1 is cut off with its base-emitter
(b-e) junction reverse biased to -1.67V
and its collector-base (c-b) reverse
biased by 6.67V. On the rising edge of
the input pulse the potential at point A
(VBE) rises exponentially as the junction
capacitances of the transistor charge,
until the VBE reaches 0.6-0.7V and the b-e
junction starts to conduct significant
current. The time before this occurs from
the start of the input pulse is termed the
delay time, td. As the base current (IB)
flows, charged carriers accumulate in
the base region, and the collector
current increases in proportion until it is
Input
Voltage
+5V
0V
R3
1k
Base
Voltage
Cbc
Output Collector
Current
R1
5mA
R2
20k
ts
0mA
Q1
td
10k
Input
0.7V
0V
-1.67V
Collector
Voltage
Cbe
+5V
tr
tf
0V
0V
-5V
Simple Inverter Switching Waveform
Figure 22.
Figure 23.
Bipolar Transistor Switching Circuit for Bipolar Transistor Switching Waveforms
Illustration of Basic Switching Behaviour. for the Inverter Circuit of Figure 22.
AN22 - 12
Application Note 22
Issue 1 May 1996
limited by the collector load resistance
R3. The time taken for the collector
current to rise from 10% to 90% of its
final value is the rise time, tr. As the
collector voltage approaches zero, the
c-b junction becomes forward biased
and conducts the excess base current.
The base now starts acting as an emitter
and begins to inject charge carriers into
the collector. This causes a considerable
accumulation of charge in the collector
region which must be removed, either
by recombination or by reverse base
current, before the device can begin to
turn off. The time taken for this excess
charge to be removed is called the
storage time (ts), and during this time the
transistor remains saturated. At the end
of the storage time all excess charge
carriers have been removed and the
base charge is simply that required to
maintain collector current. As this
charge is reduced further the collector
current falls in sympathy until the device
is cut off. The time taken for the collector
current to fall from 90% to 10% is called
the fall time, tf.
Due to the l ow leakage of silicon
transistors, it is not usually necessary to
reverse bias the base to ensure DC
stability. This does tend to reduce the
delay time, but increases the storage
and fall times as the stored charge can
only be dissipated by recombination
ins tead of b y t he rev erse curren t
provided by R2. This can be overcome
by including a capacitor in parallel with
the base drive resistor, of such value that
the charge stored on it is sufficient to
neutralis e the total charge in the
transistor. This value will be dependent
on the transistor type, the base and
collector currents and the amplitude of
the input or driving pulse. For practical
applications it is necessary to determine
th e r e q u i r e d c a p a c i t o r v a l u e s b y
measurement, preferably using a worst
case version of the circuit. As a guide,
minimum values of turn-off charge have
been provided for small signal,
switching and high current low VCE(sat)
transistors, and are reproduced for
various DC conditions within Appendix
C. These charts were produced using
test circuits similar to that shown in
Figure 5. As carrier diffusion coefficients
and recombination are temperature
dependent, then storage time will also
possess this dependence to some
degree.
Therefore
in
some
circumstances allowance must be made,
a n d c o m p o n e n t v a l u e s a d j u s te d
accordingly.
The mount of trigger charge necessary
for pulse applications can be considered
in a similar manner, and for obtaining
approximate values the circuit shown in
Figure 24 can be employed. The values
o b t a i n e d a r e h i g h e r t h a n fo r th e
“speed-up” case as the trigger capacitor
not only has to remove the stored charge
but also has to overcome the DC bias
provided by RB. In a practical circuit,
th e r e m a y w e l l b e a d d i t i o n a l
components, which will absorb some
fraction of the trigger charge. Therefore
it will usually be necessary to use a
h i g h e r v a l u e o f c a p a c i t a n c e t h an
measurement (or provided curves)
would suggest - it is advised to closely
breadboard/model the actual circuit as
closely as possible with worst case
component values. Figure 25 shows an
example oscillograph for the ZTX300
small signal device, and Figure 26
presents curves for the minimum trigger
AN22 - 13
Application Note 22
Issue 1 May 1996
In order to understand the requirement
for speed-up capacitors, consider the
simple inverter circuit shown in Figure
22, and the resultant switching
waveforms shown schematically in
Figure 23.
Appendix A
Bipolar Transistor Switching
Behaviour
In most swi tching circ uits tri gger
capacitors are required to differentiate
pulses and provide DC isolation between
stages, and speed-up capacitors are
needed to neutralise the stored charge
a n d j u n c t i o n c a p a c i ta nc e s o f th e
transistors. In most cases it is sufficient
to choose values small enough not to
interfere with the operation of the circuit
at its maxi mum freque ncy . The se
capacitors do however have minimum
v a l u e s d e p e nd in g on t he ty pe o f
transistor used, the base and collector
currents, and the amplitude of the
waveforms involved.
+5V
Initially Q1 is cut off with its base-emitter
(b-e) junction reverse biased to -1.67V
and its collector-base (c-b) reverse
biased by 6.67V. On the rising edge of
the input pulse the potential at point A
(VBE) rises exponentially as the junction
capacitances of the transistor charge,
until the VBE reaches 0.6-0.7V and the b-e
junction starts to conduct significant
current. The time before this occurs from
the start of the input pulse is termed the
delay time, td. As the base current (IB)
flows, charged carriers accumulate in
the base region, and the collector
current increases in proportion until it is
Input
Voltage
+5V
0V
R3
1k
Base
Voltage
Cbc
Output Collector
Current
R1
5mA
R2
20k
ts
0mA
Q1
td
10k
Input
0.7V
0V
-1.67V
Collector
Voltage
Cbe
+5V
tr
tf
0V
0V
-5V
Simple Inverter Switching Waveform
Figure 22.
Figure 23.
Bipolar Transistor Switching Circuit for Bipolar Transistor Switching Waveforms
Illustration of Basic Switching Behaviour. for the Inverter Circuit of Figure 22.
AN22 - 12
Application Note 22
Issue 1 May 1996
limited by the collector load resistance
R3. The time taken for the collector
current to rise from 10% to 90% of its
final value is the rise time, tr. As the
collector voltage approaches zero, the
c-b junction becomes forward biased
and conducts the excess base current.
The base now starts acting as an emitter
and begins to inject charge carriers into
the collector. This causes a considerable
accumulation of charge in the collector
region which must be removed, either
by recombination or by reverse base
current, before the device can begin to
turn off. The time taken for this excess
charge to be removed is called the
storage time (ts), and during this time the
transistor remains saturated. At the end
of the storage time all excess charge
carriers have been removed and the
base charge is simply that required to
maintain collector current. As this
charge is reduced further the collector
current falls in sympathy until the device
is cut off. The time taken for the collector
current to fall from 90% to 10% is called
the fall time, tf.
Due to the l ow leakage of silicon
transistors, it is not usually necessary to
reverse bias the base to ensure DC
stability. This does tend to reduce the
delay time, but increases the storage
and fall times as the stored charge can
only be dissipated by recombination
ins tead of b y t he rev erse curren t
provided by R2. This can be overcome
by including a capacitor in parallel with
the base drive resistor, of such value that
the charge stored on it is sufficient to
neutralis e the total charge in the
transistor. This value will be dependent
on the transistor type, the base and
collector currents and the amplitude of
the input or driving pulse. For practical
applications it is necessary to determine
th e r e q u i r e d c a p a c i t o r v a l u e s b y
measurement, preferably using a worst
case version of the circuit. As a guide,
minimum values of turn-off charge have
been provided for small signal,
switching and high current low VCE(sat)
transistors, and are reproduced for
various DC conditions within Appendix
C. These charts were produced using
test circuits similar to that shown in
Figure 5. As carrier diffusion coefficients
and recombination are temperature
dependent, then storage time will also
possess this dependence to some
degree.
Therefore
in
some
circumstances allowance must be made,
a n d c o m p o n e n t v a l u e s a d j u s te d
accordingly.
The mount of trigger charge necessary
for pulse applications can be considered
in a similar manner, and for obtaining
approximate values the circuit shown in
Figure 24 can be employed. The values
o b t a i n e d a r e h i g h e r t h a n fo r th e
“speed-up” case as the trigger capacitor
not only has to remove the stored charge
but also has to overcome the DC bias
provided by RB. In a practical circuit,
th e r e m a y w e l l b e a d d i t i o n a l
components, which will absorb some
fraction of the trigger charge. Therefore
it will usually be necessary to use a
h i g h e r v a l u e o f c a p a c i t a n c e t h an
measurement (or provided curves)
would suggest - it is advised to closely
breadboard/model the actual circuit as
closely as possible with worst case
component values. Figure 25 shows an
example oscillograph for the ZTX300
small signal device, and Figure 26
presents curves for the minimum trigger
AN22 - 13
Application Note 22
Issue 1 May 1996
+5V
Appendix B
References
To Oscilloscope
(References 1, 2 and 3 contain
mathematical treatment of charge
analysis with respect to switching
characteristics of bipolar transistors similar background can be found in most
semiconductor physics books).
RC
C1
1. Switching Transistor Handbook,
chapter five - “Transient Characteristics
of Transistors” . Motorola Inc.,
Technical Editor William D. Roehr.
Q1
Input
0V
a ZTX107
b ZTX300
c ZTX500
1n
10n
ZTX869
a
b ZTX510
c
ZTX949
IC/I B=50
Stored Charge (C)
10n
IC/IB=100
IC/I B=150
10n
IC/IB=200
IC/IB=50
IC/I B=100
IC/I B=150
1n
100p
1n
0.1
10
1
0.1
IC - Collector Current (A)
ZTX310
100n
1m
and Switching Transistors
Figure 26.
Minimum Trigger Charge for Small Signal
and Switching Transistors. Forced Gains
(IC/IB) of : a)10; b)20; c)40.
No significant difference observed for
different forced gains on the ZTX310 series.
10
100n
ZTX968
10m
ZTX1048A
IC/I B=50
Stored Charge (C)
10p
100u
1
IC - Collector Current (A)
Stored Charge v IC for ZTX949
Stored Charge v IC for ZTX869
IB - Base Current (A)
Min. Trigger Charge v IB for Small Signal
AN22 - 14
4. Switching and Linear Power Supply,
Power Converter Design. Abraham I.
Pressman. Hayden Press.
100n
Stored Charge (C)
Minimum Trigger Charge (C)
Figure 25.
Trigger Waveforms and Effect of Varying
Trigger Capacitance. Upper trace - Input
waveform; lower traces - output at
collector, (a) Variable capacitor “C1” below
critical value, (b) “C1” at critical value with
collector voltage rising to 90% of final value,
(c) “C1” above critical value. Horizontal
scale=200ns/div, Vertical scale=2V/div.
ZTX300, IB=1mA, IC=10mA.
3. Semiconductor Device Technology,
section 2.2.26 BJT Modelling - Physical
BJT Models, subsection 2) Charge
Control BJT Model. Malcolm E. Goodge.
MacMillan Press.
Characterisation Charts showing typical stored charge as a function of load current
and bias level.
charge necessary for small signal types
ZTX107, ZTX300 and ZTX500, and
sw itc hing trans i stors ZTX310 and
ZTX510.
100p
2. Pulse, Digital and Switching
Waveforms, Chapter 20 - “Transient
Switching Characteristics”, Millman and
Taub. McGraw-Hill Book Company.
Appendix C
Figure 24.
Circuit to Determine Minimum Value of Trigger Charge for Bipolar Transistor.
Stored Charge (C)
RB
Application Note 22
Issue 1 May 1996
IC/I B=50
IC/I B=100
IC/I B=150
IC/I B=200
10n
1n
100p
IC/IB=100
IC/IB=150
IC/IB=200
10n
1n
0.1
1
10
IC - Collector Current (A)
0.1
1
10
IC - Collector Current (A)
Stored Charge v IC for ZTX968
AN22 - 15
Stored Charge v IC for ZTX1048A
Application Note 22
Issue 1 May 1996
+5V
Appendix B
References
To Oscilloscope
(References 1, 2 and 3 contain
mathematical treatment of charge
analysis with respect to switching
characteristics of bipolar transistors similar background can be found in most
semiconductor physics books).
RC
C1
1. Switching Transistor Handbook,
chapter five - “Transient Characteristics
of Transistors” . Motorola Inc.,
Technical Editor William D. Roehr.
Q1
Input
0V
a ZTX107
b ZTX300
c ZTX500
1n
10n
ZTX869
a
b ZTX510
c
ZTX949
IC/I B=50
Stored Charge (C)
10n
IC/IB=100
IC/I B=150
10n
IC/IB=200
IC/IB=50
IC/I B=100
IC/I B=150
1n
100p
1n
0.1
10
1
0.1
IC - Collector Current (A)
ZTX310
100n
1m
and Switching Transistors
Figure 26.
Minimum Trigger Charge for Small Signal
and Switching Transistors. Forced Gains
(IC/IB) of : a)10; b)20; c)40.
No significant difference observed for
different forced gains on the ZTX310 series.
10
100n
ZTX968
10m
ZTX1048A
IC/I B=50
Stored Charge (C)
10p
100u
1
IC - Collector Current (A)
Stored Charge v IC for ZTX949
Stored Charge v IC for ZTX869
IB - Base Current (A)
Min. Trigger Charge v IB for Small Signal
AN22 - 14
4. Switching and Linear Power Supply,
Power Converter Design. Abraham I.
Pressman. Hayden Press.
100n
Stored Charge (C)
Minimum Trigger Charge (C)
Figure 25.
Trigger Waveforms and Effect of Varying
Trigger Capacitance. Upper trace - Input
waveform; lower traces - output at
collector, (a) Variable capacitor “C1” below
critical value, (b) “C1” at critical value with
collector voltage rising to 90% of final value,
(c) “C1” above critical value. Horizontal
scale=200ns/div, Vertical scale=2V/div.
ZTX300, IB=1mA, IC=10mA.
3. Semiconductor Device Technology,
section 2.2.26 BJT Modelling - Physical
BJT Models, subsection 2) Charge
Control BJT Model. Malcolm E. Goodge.
MacMillan Press.
Characterisation Charts showing typical stored charge as a function of load current
and bias level.
charge necessary for small signal types
ZTX107, ZTX300 and ZTX500, and
sw itc hing trans i stors ZTX310 and
ZTX510.
100p
2. Pulse, Digital and Switching
Waveforms, Chapter 20 - “Transient
Switching Characteristics”, Millman and
Taub. McGraw-Hill Book Company.
Appendix C
Figure 24.
Circuit to Determine Minimum Value of Trigger Charge for Bipolar Transistor.
Stored Charge (C)
RB
Application Note 22
Issue 1 May 1996
IC/I B=50
IC/I B=100
IC/I B=150
IC/I B=200
10n
1n
100p
IC/IB=100
IC/IB=150
IC/IB=200
10n
1n
0.1
1
10
IC - Collector Current (A)
0.1
1
10
IC - Collector Current (A)
Stored Charge v IC for ZTX968
AN22 - 15
Stored Charge v IC for ZTX1048A
Application Note 22
Issue 1 May 1996
Application Note 22
Issue 1 May 1996
Appendix C (continued)
Stored Charge (C)
10n
a ZTX107
b ZTX300
c
ZTX500
1n
a
b ZTX510
c
ZTX310
100p
10p
100u
1m
Minimum Trigger Charge (C)
Forced gains (IC/IB) of a:)10, b)20, C) 40.
No significant difference observed for the different forced gains for the ZTX310 series
10m
10n
a ZTX107
b ZTX300
c ZTX500
1n
a
b ZTX510
c
ZTX310
100p
10p
100u
10m
IB - Base Current (A)
Min. Trigger Charge v IB for Small Signal
Switching Transistors
and Switching Transistors
100n
10n
Stored Charge (C)
ZTX618
Stored Charge (C)
1m
IB - Base Current (A)
Stored Charge v IB for Small Signal and
IC/IB=50
IC/IB=100
IC/IB=150
IC/IB=200
10n
1n
100p
ZTX717
IC/IB=50
IC/IB=100
IC/IB=150
1n
IC/IB=200
100p
0.1
1
0.1
10
1
10
IC - Collector Current (A)
IC - Collector Current (A)
Stored Charge v IC for ZTX618
Stored Charge v IC for ZTX717
10n
100n
ZTX718
ZTX849
Stored Charge (C)
Stored Charge (C)
IC/IB=50
IC/IB=100
IC/IB=150
IC/IB=200
1n
100p
IC/IB=50
IC/IB=100
10n
IC/IB=150
1n
0.1
1
10
0.1
1
IC - Collector Current (A)
IC - Collector Current (A)
Stored Charge v IC for ZTX718
Stored Charge v IC for ZTX849
AN22 - 16
10
AN22 - 15
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