Application Note SMBus communication with MLX90614 1 Scope This document introduces the users in SMBus communication protocol and especially how it can be used to communicate with MLX90614 infrared thermometers. The MLX90614 is an Infra Red thermometer for non contact temperature measurements. Both the IR sensitive thermopile detector chip and the signal conditioning ASSP are integrated in the same TO-39 can. Thanks to its low noise amplifier, 17-bit ADC and powerful DSP unit, a high accuracy and resolution of the thermometer is achieved. The thermometer comes factory calibrated with a digital PWM and SMBus output. As a standard, the 10-bit PWM is configured to continuously transmit the measured temperature in range of -20 to 120 °C, with an output resolution of 0.14 °C and the POR default is SMBus. The original purpose of the SMBus was to define the communication link between an intelligent battery, charger for the battery and a microcontroller that communicates with the rest of the system. However, SMBus can also be used to connect a wide variety of devices including power-related devices, system sensors, EEPROMs, communications devices etc. The original specification of the SMBus protocol can be found on http://www.smbus.org/specs/ 2 Related Melexis Products EVB90614 is the evaluation board which supports the MLX90614 devices. 3 Table of contents 1 2 3 4 Scope............................................................................................................................................................. 1 Related Melexis Products............................................................................................................................... 1 Table of contents............................................................................................................................................ 1 General SMBus protocol discription............................................................................................................... 2 4.1 Definitions of terms................................................................................................................................... 2 4.2 SMBus overview....................................................................................................................................... 2 4.3 Electrical characteristics of SMBus devices ............................................................................................... 5 4.4 Timeouts ................................................................................................................................................... 6 4.5 Slave device timeout definitions and conditions ......................................................................................... 6 4.6 Master device timeout definitions and conditions ....................................................................................... 7 4.7 Low-power DC specifications.................................................................................................................... 7 4.8 High-power DC specifications................................................................................................................... 7 4.9 Bit transfer ................................................................................................................................................ 8 5 Comparing the I2C Bus to the SMBus .......................................................................................................... 10 5.1 Timeout and Clock Speed differences ...................................................................................................... 10 5.2 DC specifications differences .................................................................................................................. 10 5.3 Other differences..................................................................................................................................... 11 6 SMBus comunication with MLX90614 ........................................................................................................ 12 6.1 Overview ................................................................................................................................................ 12 6.2 Timings................................................................................................................................................... 12 6.3 Detailed Communication description ....................................................................................................... 13 6.4 Sleep Mode ............................................................................................................................................. 16 6.5 Electrical considerations of SMBus applications with MLX90614............................................................ 16 7 Conclusion................................................................................................................................................... 19 390119061402 Rev 002 Page 1 of 19 Dec-2006 Application Note SMBus communication with MLX90614 4 General SMBus protocol discription 4.1 Definitions of terms ACK - Acknowledgement from receiver Address Resolution Protocol - A protocol by which SMBus devices with assignable addresses on the bus are enumerated and assigned non-conflicting slave addresses. ASSP - Application Specific Standard Product Bus Master - Any device that initiates SMBus transactions and drives the clock. Bus Slave - Target of a SMBus transaction which is driven by some master. LSb - The Last Significant bit Master-receiver - A bus master in a SMBus transaction when receiving data from a bus slave. Master-transmitter - A bus master in a SMBus transaction when transmitting data onto the bus. MSb - The Most Significant bit NACK - Not Acknowledgement from receiver OD - Open Drain PEC - Packet Error Code PP - Push Pull Repeated Start - A repeated START is a START condition on the SMBus used to switch from write mode to read mode in a combined format protocol (e.g. Byte Read). The repeated START always follows an Acknowledge, and it always indicates that an address phase is beginning. Slave-receiver - A Slave-receiver is a device that acts as a bus slave in a SMBus transaction while it is receiving address, command or other data from a device acting as a bus master in the transaction. Slave-transmitter - A Slave-transmitter is a device acting as a bus slave in a SMBus transaction while it is transmitting data on the bus in response to a bus master’s request. 4.2 SMBus overview Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). Each device connected to the bus is software addressable by a unique address and a simple master/slave relationships exist at all times. Masters can operate as master-transmitters or as master-receivers. It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. Serial, 8-bit oriented, bi-directional data transfer can be made at up to 100 kbit/s. The System Management Bus (SMBus) is a two-wire interface, that various system component chips can use to communicate with each other and with the rest of the system. It is based on the principles of operation of I2C protocol. Multiple devices, both bus masters and bus slaves, may be connected to a SMBus segment. Generally, a bus master device initiates a bus transfer between it and a single bus slave and provides the clock signals. The one exception to this rule is during initial bus setup when a single master may initiate transactions with multiple slaves simultaneously. A bus slave device can receive data provided by the master or it can provide data to the master. Only one device may master the bus at any time. Since more than one device may attempt to take control of the bus as a master, the SMBus protocol provides an arbitration mechanism that relies on the wired-AND connection of all SMBus device interfaces to the SMBus. 390119061402 Rev 002 Page 2 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Devices may be powered by the bus VDD or by another power source Vbus (Fig.1). Fig.1: SMBus Topology VDD may be 3 to 5 volts +/- 10% and there may be SMBus devices powered directly by the bus VDD. Both SDA and SCL lines are bi-directional, connected to a positive supply voltage through a pull-up resistor or a current source or other similar circuit. When the bus is free, both lines are high. The output stages of the devices connected to the bus must have an open drain or open collector in order to perform the wired-AND function. SMBus standard recommends for both the input and output stages of SMBus devices, not to load the bus when their power plane is turned off, i.e. powered-down devices should provide no leakage path to ground. A device that wants to place a ‘zero’ on the bus must drive the bus line to the defined logic low voltage level. In order to place a logic ‘one’ on the bus, the device should release the bus line letting it be pulled high by the bus pull-up circuitry. The bus lines may be pulled high by a pull-up resistor or by a current source. In case this involves a higher bus capacitance, a more sophisticated circuit may be used that can limit the pull-down sink current while also providing enough current during the low-tohigh transition to maintain the rise time specifications of the SMBus. In SMBus systems with higher bus capacitance (like wires) RPU=1.5kΩ (VDD=5V,IPULLUP=3.3mA) is suitable otherwise RPU=22kΩ(VDD=5V,IPULLUP=227µA) can be used to meet SMBus low power DC specification (see low and high power DC specification below). Version 1.1 of the SMBus specification introduced a Packet Error Checking mechanism to improve reliability and communication robustness. Implementation of Packet Error Checking by SMBus devices is optional for SMBus devices. Packet Error Checking, whenever applicable, is implemented by appending a Packet Error Code (PEC) at the end of each message transfer. The PEC uses an 8-bit cyclic redundancy check (CRC-8) of each read or write bus transaction to calculate a Packet Error Code (PEC). The PEC may be calculated in any way that conforms to a CRC-8 represented by the polynomial, C(x) = x8 + x2 + x1 + 1 and must be calculated in the order of the bits as received. The PEC calculation includes all bytes in the transmission, including address, command and data. The PEC calculation does not include ACK, NACK, START, STOP nor Repeated START bits. This means that the PEC is computed over the entire message from the first START condition. For the CRC calculation we use the following procedure: In the case of the SMBus, the polynomial used is X8 + X2 + X + 1. The width of this polynomial is 8 (the highest power of X indicates the width) and it can be represented as 1 0000 0111. Since the width of the polynomial is 8 we refer to our CRC method as CRC-8. A message is represented as a bit-stream augmented with M = 8 zeroes at the end. The augmented bit-stream message is devised by the polynomial 1 0000 0111. The remainder will be the CRC-8 check byte. 390119061402 Rev 002 Page 3 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Fig.2 shows a CRC calculation example. Fig.2 For more information about calculation of CRC refer to the next document: http://www.sbs-forum.org/marcom/dc2/20_crc-8_firmware_implementations.pdf Fig.3 shows the common structure of an SMBus transaction Fig.3: SMBus Transaction 390119061402 Rev 002 Page 4 of 19 Dec-2006 Application Note SMBus communication with MLX90614 4.3 Electrical characteristics of SMBus devices The diagram bellow illustrates the various SMBus timings Fig.4: SMBus timing measurements The table below describes all timings. Table 1 Symbol fSMB tBUF tHD:STA tSU:STA tSU:STO tHD:DAT tSU:DAT tTIMEOUT tLOW tHIGH tLOW:SEXT tLOW:MEXT tF tR T POR Parameter SMBus Operation frequency Bus free time between Stop and Start condition Hold time after(Repeated)Start Condition.After this period, the first clock is generated Repeated Start Condition setup time Stop Condition setup time Data hold time Data setup time Detect clock low timeout Clock low period Clock high period Cumulative clock low extend time (slave device) Cumulative clock low extend time (master device) Clock/Data Fall time Clock/Data Rise Time Time in which a device must be Operational after power-on reset Min 10 4.7 Max 100 - Units kHz µs Comments See note 1 4.0 - µs 4.7 4.0 300 250 25 4.7 4.0 - 35 50 25 µs µs ns ns ms µs µs ms See note 3 See note 4 - 10 ms See note 5 - 300 1000 500 ns ns ms See note 6 See note 6 See note 7 See note 2 Note 1: A master shall not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency shall not be reduced below the minimum value of fSMB due to periodic clock extending by slave devices . This limit does not apply to the bus idle condition, and this limit is independent from the tLOW: SEXT and tLOW: MEXT limits. For example, if the SCL is high for tHIGH,MAX, the clock must not be periodically stretched longer than 1/fSMB,MIN – fHIGH,MAX. This requirement does not pertain to a device that extends the SCL low for data processing of a received byte, data buffering and so forth for longer than 100us in a nonperiodic way. Note 2: Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of tTIMEOUT,MIN. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller and most devices that can master the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or a stop condition.A timeout condition can only be ensured if the device that is forcing the timeout holds the SCL low for tTIMEOUT,MAX or longer. 390119061402 Rev 002 Page 5 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Note 3: tHIGH,MAX provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is free if it detects that the clock and data signals have been high for greater than tHIGH,MAX. Note 4: tLOW:SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message from the initial START to the STOP. It is possible that, another slave device or the master will also extend the clock causing the combined clock low extend time to be greater than tLOW:SEXT. Therefore, this parameter is measured with the slave device as the sole target of a full-speed master. Note 5: tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device or another master will also extend the clock causing the combined clock low time to be greater than tLOW:MEXT on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of the master. Note 6: Rise and fall time is defined as follows: tR = (VIL,MAX - 0.15) to (VIH,MIN + 0.15) tF = (VIH,MIN + 0.15)to (VIL,MAX - 0.15) Note 7: For the first silicon revision of a MLX90614 module this value is above 500ns 4.4 Timeouts Timeout measurement intervals illustrates the definition of the timeout intervals, tLOW:SEXT and tLOW:MEXT. Fig.5: Timeout measurement intervals 4.5 Slave device timeout definitions and conditions The tTIMEOUT,MIN parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly recommended that a slave device release the bus (stop driving the bus and let SCL and SDA float high) when it detects any single clock held low longer than tTIMEOUT,MIN. Devices that have detected this condition must reset their communication and be able to receive a new START condition in no later than tTIMEOUT,MAX. Slave devices that violate tLOW:SEXT are not conformant with this specification. A Master is allowed to abort the transaction in progress to any slave that violates the tLOW:SEXT or tTIMEOUT,MIN specifications. 390119061402 Rev 002 Page 6 of 19 Dec-2006 Application Note SMBus communication with MLX90614 4.6 Master device timeout definitions and conditions tLOW: MEXT is defined as the cumulative time a master device is allowed to extend its clock cycles within one byte in a message as measured from: START to ACK ACK to ACK ACK to STOP A system host may not violate tLOW:MEXT except when caused by the combination of its clock extension with the clock extension from a slave device or another master. A Master is allowed to abort the transaction in progress to any slave that violates the tLOW:SEXT or tTIMEOUT,MIN specifications. This can be accomplished by the Master issuing a STOP condition at the conclusion of the byte transfer in progress. Note: A Master should take care when evaluating tLOW:SEXT violation during arbitration since the clock may be held low by multiple slave devices simultaneously. The arbitration interval may be extended for several bytes in the case of devices that respond to commands to the SMBus ARP address. If timeouts are handled at the driver level, the software may need to allow timeouts to be configured or disabled by applications that use the driver in order to support older devices that do not fully meet the SMBus timeout specifications. Devices that implement ‘shared’ slave addresses may also violate this specification due to combined clock stretching by the different devices sharing the address. TTIMEOUT,MIN, however, does not increase due to combined clock stretching. Therefore, this is a safer timeout parameter for a Master to use when it knows it’s accessing SMBus 2.0 devices. 4.7 Low-power DC specifications In the table bellow are given low power DC parameters of the SMBus specification. Table 2 Symbol VIL VIH VOL ILEAK IPULLUP Parameter Min Max Units Comments Data, Clock Input Low Voltage 0.8 V Data, Clock Input High Voltage 2.1 VDD V Data, Clock Output Low Voltage 0.4 V Input Leakage ±5 µA Note 1 Current trough pull-up resistor or 100 350 µA Note 2 current source VDD Nominal bus voltage 2.7 5.5 V 3V to 5V ±10% Note 1: Devices must meet this specification whether powered or unpowered. However, a microcontroller acting as an SMBus host may exceed ILEAK by no more than 10 µA. Note 2: The IPULLUP,MAX specification is determined primarily by the need to accommodate a maximum of 1.1K equivalent series resistor of removable SMBus devices, such as the Smart Battery, while maintaining the VOL,MAX of the bus. Because of the relatively low pull-up current, the system designer must ensure that the loading on the bus remains within acceptable limits. Additionally, to prevent bus loading, any devices that remain connected to the active bus while unpowered (that is, their Vcc lowered to zero), must also meet the leakage current specification. 4.8 High-power DC specifications High-power SMBus is specified below. These higher power specifications provide the robustness necessary, for example, to allow SMBus to cross the PCI connector, thus allowing SMBus devices on PCI add-in cards to communicate with other devices on both the system board and other PCI add-in cards in the same system. These higher power electrical 390119061402 Rev 002 Page 7 of 19 Dec-2006 Application Note SMBus communication with MLX90614 specifications are an alternative to the lower power specifications stated above and may be used in environments where necessary. Table 3 Symbol VIL VIH VOL ILEAK-BUS ILEAK-PIN VDD IPULLUP CBUS CI VNOISE Parameter Min Max Units Comments SMBus signal Input low voltage 0.8 V SMBus signal Input high voltage 2.1 VDD V SMBus signal Output low voltage 0.4 V @ IPULLUP µA Input Leakage per bus segment ±200 µA Input Leakage per device pin ±10 3V to 5V ±10% Nominal bus voltage 2.7 5.5 V Current sinking, VOL=0.4V 4 mA Capacitive load per bus segment 400 pF Note 1 Capacitance for SDA or SCL pin 10 pF Note 2 Signal noise immunity from 300 mVp-p This AC item applies 10MHz to 100MHz To the high-power DC Specification only Note 1: Capacitive load for each bus line includes all pin, wire and connector capacitances. The maximum capacitive load affects the selection of the RPU pull-up resistor or the current source in order to meet the rise time specifications of SMBus. Note 2: Pin capacitance (CI) is defined as the total capacitive load of one SMBus device as seen in a typical manufacturer' s data sheet. While SMBus devices used in low-power segments have practically no minimum current sinking requirements due to the low pull-up current specified for low-power segments, devices in highpower segments are required to sink a minimum current of 4 mA while maintaining the VOL,MAX of 0.4 Volts. The requirement for 4 mA sink current determines the minimum value of the pull-up resistor RPU that can be used in SMBus systems. Unpowered devices connected to either a low-power or high-power SMBus segment must provide, either within the device or through the interface circuitry, protection against “back powering” the SMBus. 4.9 Bit transfer In accordance to the SMBus specification, the MSb is transferred first. SMBus uses fixed voltage levels to define the logic “ZERO” and logic “ONE” on the bus respectively. The data on SDA must be stable during the “HIGH” period of the clock. Data can change state only when SCL is low. Each transfer begins with START bit and finishes with STOP bit (Fig.6). Fig.6: SMBus byte format START bit is defined by HIGH to LOW transition of the SDA line while SCL is HIGH. STOP bit is defined by LOW to HIGH transition of the SDA line while SCL is HIGH. Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master (ACK clock). The transmitter, master or slave, releases the SDA line (HIGH) during the acknowledge clock cycle. In order to 390119061402 Rev 002 Page 8 of 19 Dec-2006 Application Note SMBus communication with MLX90614 acknowledge a byte, the receiver must pull the SDA line LOW during the HIGH period of the clock pulse according to the SMBus timing specifications. A receiver that wishes to NACK a byte must let the SDA line remain HIGH during the acknowledge clock pulse. A SMBus device must always acknowledge (ACK) its own address. A SMBus slave device may decide to NACK a byte other than the address byte in the following situations: The slave device is busy performing a real time task, or data requested are not available. The master upon detection of the NACK condition must generate a STOP condition to abort the transfer. Note that as an alternative, the slave device can extend the clock LOW period within the limits of the specifications in order to complete its tasks and continue the transfer. The slave device detects an invalid command or invalid data. In this case the slave device must NACK the received byte. The master upon detection of this condition must generate a STOP condition and retry the transaction. If a master-receiver is involved in the transaction it must signal the end of data to the slave-transmitter by generating an NACK on the last byte that was clocked out by the slave. The slave-transmitter must release the data line to allow the master to generate a STOP condition. 390119061402 Rev 002 Page 9 of 19 Dec-2006 Application Note SMBus communication with MLX90614 5 Comparing the I2C Bus to the SMBus The I2C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other. Normally devices, both masters and slaves, are freely interchangeable between both buses. Both buses feature addressable slaves (although specific address allocations can vary between the two). The buses operate at the same speed, up to 100kHz, but the I2C bus has both 400kHz and 2MHz versions. Complete compatibility between both buses is ensured only below 100kHz. Here are explored the significant differences between I2C and SMB. 5.1 Timeout and Clock Speed differences Timeout and (as a consequence of timeout) minimum clock speed are the most important differences between the I2C bus and the SMBus. I2C Bus = DC (no timeout) SMBus = 10kHz (35mS timeout) Timeout is where a slave device resets its interface whenever SCL goes low for longer than the timeout, typically 35mSec. Use of a timeout also dictates a minimum speed for the clock, because it can never go static. Thus, the SMBus has a minimum-clock-speed specification. By comparison, the I2C bus can go static indefinitely. In the I2C bus, either a master or a slave can hold the clock low as long as necessary to process data. In the I2C bus, if the slave locks up and holds either SCL or SDA low, error recovery is impossible. Very few slave devices actually have the ability to hold SCL. As a result, the most common bus error is slave devices that have ended up in a state where SDA is low. In the I2C bus, a master accomplishes error recovery by clocking SCL until SDA is high and then issuing a Start followed by a Stop. In contrast to the I2C bus, SMBus slaves are expected to reset their interface whenever SCL is low for longer than the timeout specified in the SMBus specification of 35mS. SMBus specifies tLOW: SEXT as the cumulative clock low extend time for a slave device. I2C does not have a similar specification. SMBus specifies tLOW: MEXT as the cumulative clock low extend time for a master device. Again I2C does not have a similar specification. 5.2 DC specifications differences Both I2C and SMBus are capable of operating with mixed devices that have either fixed input levels (such as Smart Batteries) or input levels related to VDD. When mixing devices, the I2C specification defines the VDD to be 5.0 Volt +/- 10% and the fixed input levels to be 1.5 and 3.0 Volts. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed at 0.8 and 2.1 Volts. This SMBus specification allows for bus implementations with VDD ranging from 3 to 5 Volts +/- 10%. I2C specifies the maximum leakage current to be 10 µA while SMBus version 1.0 specified maximum leakage current of 1 uA. Version 1.1 of the SMBus specification relaxes the leakage requirements to 5 µA, in order to reduce the cost of testing of SMBus devices. While I2C defines maximum bus capacitance 400pF SMBus does not specify a maximum bus capacitance. Instead it specifies the IPULLUP maximum of 350µA in Low-power DC specification and minimum 4mA in High-power DC specification. Bus capacitance can be calculated taking into consideration the maximum rise time and IPULLUP. In the table below are given a summery of level specifications for the I2C Bus and the SMBus. Table 4 High I2C VDD Dependent I2C Fixed SMBus 390119061402 Rev 002 0.7*VDD 3.0V 2.1V Page 10 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Low 5.3 I2C VDD Dependent 0.3*VDD I2C Fixed SMBus 1.5V 0.8V Other differences ACK and NACK usage: The differences in the use of the NACK bus signaling follow: In I2C, a slave receiver is allowed not to acknowledge the slave address, if for example is unable to receive because it’s performing some real time task. SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable device’s presence on the bus (battery, docking station, etc.). I2C specifies that a slave device, although it may acknowledge its own address, some time later in the transfer it may decide that it cannot receive any more data bytes. The I2C specifies, that the device may indicate this by generating the not acknowledge on the first byte to follow. Besides to indicate a slave device busy condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This is important because SMBus does not provide any other resend signaling. More information about the differences between I2C and SMBus can be found on: http://www.maxim-ic.com/appnotes_frame.cfm/appnote_number/476 http://www.smbus.org/specs/ 390119061402 Rev 002 Page 11 of 19 Dec-2006 Application Note SMBus communication with MLX90614 6 SMBus comunication with MLX90614 6.1 Overview The MLX90614 can only be used as a slave device. Generally, the master initiates the start of data transfer by selecting a slave through the Slave Address (SA). The MLX90614 meets all the timing specifications of the SMBus (refer to Electrical characteristics of SMBus devices above). MLX90614 has 32x17 RAM. It is not possible to write into the RAM memory. It can only be read and only a limited number of RAM registers are of interest to the customer (see Table 6 below). (RAM readings format is described in more details below as well as in the MLX90614 data sheet.) 32x16 EEPROM is available for keeping the calibration data, chip configuration and chip ID. Entire EEPROM can be read via the SMBus compatible interface. Some EEPROM locations are write protected (access is possible with entry to Calibration mode). Before writing to EEPROM an erase has to take place. Erase is simply writing zero into EEPROM. Erase operations have the same access constrains as the write operations. Note that changes in EEPROM will result in reconfiguration of the ASIC after POR (also includes enter and exit Sleep mode). For example, Slave Address can be changed in EEPROM, but the ASIC will respond to the old SA until POR is exited. If MLX90614 is configured in PWM output mode, a SMBus request condition is needed. SMBus request overrides the OD/PP bit that configures the SDA/PWM pin into Open Drain NMOS or Push-Pull CMOS. For example, MLX90614 configured for PP PWM will switch to OD SMBus upon SMBus request condition. The diagram below illustrates the way of switching to SMBus if PWM is enabled. PWM output can be the POR default if configured in EEPROM. Fig.7 SMBus request The MLX90614’s SMBus request condition requires forcing LOW the SCL pad for period longer than the request time tREQ (see Table 5 below). The Data line value is ignored in this case. Once disabled PWM, it can be only enabled by switching Off-On of the supply or exit from Sleep Mode. 6.2 Timings The specific timings in MLX90614’s SMBus are: SMBus Request (tREQ) is the time that the SCL should be forced low in order to switch the MLX90614 from PWM mode to SMBus mode; Tsuac (SD) is the time after the eighth falling edge of SCL that MLX90614 will force PWM/SDA low to acknowledge the last received byte. Thdac (SD) is the time after the ninth falling edge of SCL that MLX90614 will release the PWM/SDA so the MD could continue with the communication. Tsuac (MD) is the time after the eighth falling edge of SCL that MLX90614 will release PWM/SDA so that the MD could acknowledge the last received byte. Thdac (MD) is the time after the ninth falling edge of SCL that MLX90614 will take control over the PWM/SDA so the it could continue with the next byte to transmit. (The indexes MD and SD for the latest timings are 390119061402 Rev 002 Page 12 of 19 Dec-2006 Application Note SMBus communication with MLX90614 used – MD when the master device is making acknowledge; SD when the slave device is making acknowledge). For other timings see Electrical characteristics of SMBus devices above. Fig.8:MLX90614 specific timings In Table 5 are given the values of the specific timings. Table 5 Symbol Parameter tREQ SMBus Request tsuac (MD) tsuac(SD) thdac(MD) thdac(SD) 6.3 Min 2 0.5 1.5 1.5 0.5 Max 1 2 2 1 Units Comments ms µs µs µs µs Detailed Communication description Table 6 describes commands needed for communication with MLX90614. Table 6 Command D e s c r i p t i on 001 x xxxx* E E P R O M A c c e s s 000x xxxx* 01 1 0 0000 01 1 0 0001 R A M A c c e s s E n te r C a lib r a tio n M o d e E xi t C a l i b r a t i o n M o d e ( E n t e r A p p l i c a t i o n m o d e ) 1 1 1 1 0000** R e a d F la g s 1 1 1 1 1 1 1 1 E n te r S L E E P m o d e Note *: The xxxxx is the address of the cell that has to be accessed. Read/Write is selected via the Read/Write bit (refer to Fig. 3). Note**: Behaves like read command. The MLX90614 returns PEC after 16 bits data of which only 4 are meaningful and if the MD wants it, it can stop the communication after the first byte. The difference between read and read flags is that the latter does not have a repeated start bit. 390119061402 Rev 002 Page 13 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Table 7 describes most important RAM registers. For other registers in RAM and EEPROM memory refer to MLX90614 datasheet. Table 7 N ame A ddr e s s ( h e x ade c i mal ) IR s e n s o r 1 d a ta 0x04 A m b ie n t s e n s o r d a ta 0x03 IR s e n s o r 2 d a ta L in e a r iz e d a m b ie n t te m p e r a tu r e T 0x05 A 0x06 L in e a r iz e d o b je c t te m p e r a tu r e T o b j1 0x07 L in e a r iz e d o b je c t te m p e r a tu r e T o b j2 0x08 RAM and EEPROM memories are accessible in two modes: Application mode and Calibration mode. The main difference between the modes is that in Calibration mode additional 17 cells of the EEPROM become write accessible (See MLX90614 datasheet). Note that these cells are provided for advanced usage of MLX90614. A typical application of MLX90614 will not need access to these cells. Therefore Application mode is enough to read and reconfigure most of the MLX90614. All bytes are sent and received with MSb first. The format of SMBus reading from RAM is: RAM memory is read only via SMBus. The reading data are divided by two, due to a sign bit (Sn) in RAM (for example, TOBJ1 - RAM address 0x07h will sweep between 0x27ADh to 0x7FFF as the object temperature rises from -70.01°C to +382.19°C). The MSb read from RAM is an error flag (active high) for the linearized temperatures (TOBJ1, TOBJ2 and Ta). The MSb for the raw data (e.g. IR sensor1 data) is a sign bit (sign and magnitude format). The format of SMBus reading from EEPROM is: 390119061402 Rev 002 Page 14 of 19 Dec-2006 Application Note SMBus communication with MLX90614 EEPROM memory is accessible for reading in both modes without restriction. The format of SMBus writing in EEPROM is: In Application mode only 9 cells are accessible for writing. An attempt to write not accessible EEPROM cell results in no change. The format of SMBus transaction which enters Calibration, Application or Sleep mode is: The format of a SMBus transaction which reads flags is: Flags read are: Data[7] - EEBUSY – the previous write/erase EEPROM access is still in progress. High active. Data[6] - Unused Data[5] - EE_DEAD – EEPROM double error has occurred. High active. Data[4] - INIT – POR initialization routine is still ongoing. Low active. Data[3] - Not implemented. Data[2..0] - All zeros. Data[8..15] - All zeros. Flags read is a diagnostic feature. The MLX90614 can be used regardless of these flags. 390119061402 Rev 002 Page 15 of 19 Dec-2006 Application Note SMBus communication with MLX90614 6.4 Sleep Mode MLX90614 can enter Sleep Mode via command “Enter SLEEP mode” sent via the SMBus interface. This mode is not available for the 5V supply version. To limit the current consumption to 2.5uA (typ), the SCL pin should be kept low during sleep (Fig.9). MLX90614 goes back into power-up default mode (via POR reset) by setting SCL pin high and then PWM/SDA pin low for at least tDDq=13ms (Fig.10). Fig.9 6.5 Fig.10 Electrical considerations of SMBus applications with MLX90614 PP/-OD ; SMBus Vdd Vdd Vdd +Vdd Din PWM/SDA SCL/Vz Dout Synthesized Zener diode for building external HV voltage regulator Vss Vss Vss SCLin Vss Vss Fig.11: Input/Output pin schematics of MLX90614 For reliability reasons, the MLX90614 incorporates ESD clamp diodes to Vdd and from Vss. Therefore a powered-down MLX90614 will load the SMBus. This differs from the SMBus specification. In power-managed systems it is therefore needed to keep the MLX90614 powered when the SMBus is needed. This is no issue in sleep mode. 390119061402 Rev 002 Page 16 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Fig.12: SCL line undershoot with MLX90614 A synthesized Zener diode is integrated on the SCL/Vz pin of the device. It allows simple implementation of higher voltage regulators. There are several things that influence the SMBus applications with that feature: Transient response of SCL pin of MLX90614 adds undershoot to the SMBus SCL line. Rising edge on the bus results in partial opening of the zener diode, as shown on Fig.12. This undershoot is typically well beyond the threshold level for high-to-low transition on SCL line. When an external regulator is build the SCL can no longer be used. This would cause the regulator to turn off and on with every clock cycle. Use of MLX90614 in >5V system is shown on Fig. 13. However, if it is needed to have SMBus communication with an MLX90614 already connected to a schematic like this, it will be necessary to override the power supply regulator as shown on Fig. 13. Then the SCL pin can be toggled and the SMBus communication will run. SCL input leakage is increased. In worst case (over temperature and voltage on the SCL pin) this leakage may significantly exceed the sleep mode power drain of the MLX90614. Sleep mode is available with the 3V version only, while the zener diode function can be used with the 5V version. However, the zener diode is present in all MLX90614 versions, so the leakage will be seen on the 3V version too. It is recommended to disable the pull-up on the SCL line in order to prevent the leakage from increasing the overall power-down power drain of the SMBus system. Voltage regulator Equivalent schematics 1 Vss U1 MLX90614Axx SDA SDA SCL 4 +5V +5V SDA SDA Vdd R1 3 C1 1 Vss U1 MLX90614Axx SCL/Vz C1 2 U1 5.7V Vdd R1 Q1 +5V 4 Q1 +V SCL/Vz +5V R1 2 Q1 +V +5V R2 SDA 3 +V R3 U2 C2 SCL SCL Vdd MCU SDA SCL Vss Fig.13: External voltage regulator with MLX90614 The input levels of the MLX90614 are not 100% compliant with the SMBus specification. The SMBus specification states an input low voltage maximum value of 0.8V and a minimum high voltage of 2.1V. For the MLX90614 (refer to the data sheet) the specifications differs. When 5V (also applies for >5V applications) is used, the MLX90614 uses an on-chip voltage regulator (5V – to – 3V±10%). With the 3V version, the power supply is used directly. 390119061402 Rev 002 Page 17 of 19 Dec-2006 Application Note SMBus communication with MLX90614 Then, at 5V (as well as at >5V) the internal circuitry of MLX90614 operates at 3V±10%, while at 3V the power supply specification covers 3V±20%. The higher tolerance of this power supply results in a higher tolerance of the input levels. Worst-case values for MLX90614Axx are Vin,L=0.5…1.5V and Vin,H=1.6…2.4V (over all temperatures and supply voltages), and for MLX90614Bxx – 0.5…1,5V and 1.2…2.8V (idem). However, this does not mean, that MLX90614Axx is likely to have Vin,L=1.5V and Vin,H=1.6V at the same time; also MLX90614Bxx will not have Vin,L=1.5V and Vin,H=1.2V at the same time. Both thresholds decrease as the power supply voltage decreases. The two thresholds are also affected by temperature in the same direction. A hysteresis is provided on both SDA and SCL inputs for noise immunity. As a summary, keeping the logic levels on the bus Vlow<0.5V and Vhigh>2.8V will certainly cover all operational cases with the MLX90614, but is not likely to be really necessary. Detailed values (guaranteed by design, not test limits) are given below: Table 8 V dd ( 3V ) V i n, L , -4 0 ° C, mi n 2 .4 2 .8 3 3. 2 3. 6 0. 7 3 0. 9 1 1 . 00 1 . 09 1 .2 9 0. 5 7 V i n, L , -4 0 ° C, max 0. 7 5 0. 8 4 0. 9 4 1 .1 3 V i n, L , + 2 7 ° C, mi n 0. 6 3 0. 8 2 0. 9 1 1 . 01 1 .2 0 V i n, L , + 1 2 5 ° C, mi n 0. 7 2 0. 9 1 1 . 01 1 .1 1 1 .3 0 V i n, L , + 2 7 ° C, max 0. 7 9 0. 9 7 1 . 07 1 .1 7 1 .3 6 V i n, L , + 1 2 5 ° C, max 0. 8 8 1 . 07 1 .1 7 1 .2 7 1 .4 6 V i n, H , -4 0 ° C, max 1 .5 4 1 .9 3 2 .1 2 2 .3 2 2 .6 9 V i n, H , -4 0 ° C, mi n 1 .2 3 1 .6 1 1 .8 1 2 . 01 2 .4 0 V i n, H , + 2 7 ° C, mi n 1 .4 1 1 .8 0 1 .9 9 2 .1 9 2 .5 7 V i n, H , + 1 2 5 ° C, mi n 1 .5 7 1 .9 3 2 .1 1 2 .2 9 2 .6 4 V i n, H , + 2 7 ° C, max V i n, H , + 1 2 5 ° C, max 3.00 1 .6 7 2 . 03 1 .7 2 2 .2 1 2 . 07 2 .3 8 2 .2 5 2 .7 4 2 .4 3 VinL, VinH, V 2 .7 7 Vin,L,-40 °C,m in Vin,L,-40 °C,m ax 2.50 Vin,L,+27°C,min Vin,L,+27°C,max 2.00 Vin,L,+125°C,min Vin,L,+125°C,max 1.50 Vin,H,-40°C,m in Vin,H,-40°C,m ax 1.00 Vin,H,+27°C,m in Vin,H,+27°C,m ax 0.50 Vin,H,+125°C,m in Vdd,V (3V version) 0.00 2 .4 2.8 3 3.2 Vin,H,+125°C,m ax 3.6 Fig.14: Input voltage levels versus power supply voltage and temperature Both temperature and supply voltage increase both low and high thresholds. 390119061402 Rev 002 Page 18 of 19 Dec-2006 Application Note SMBus communication with MLX90614 7 Conclusion The MLX90614 can easily be used in with the SMBus interface to build a network of sensors. Also for a single sensor the SMBus interface can be the preferred choice for communicating with the application controller. 390119061402 Rev 002 Page 19 of 19 Dec-2006