Data Sheet

PCF85063TP
Tiny Real-Time Clock/calendar
Rev. 4 — 6 May 2015
Product data sheet
1. General description
The PCF85063TP is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low
power consumption. An offset register allows fine-tuning of the clock. All addresses and
data are transferred serially via the two-line bidirectional I2C-bus. Maximum bus speed is
400 kbit/s. The register address is incremented automatically after each written or read
data byte.
For a selection of NXP Real-Time Clocks, see Table 35 on page 43
2. Features and benefits
 Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
 Clock operating voltage: 0.9 V to 5.5 V
 Low current: typical 0.22 A at VDD = 3.3 V and Tamb = 25 C
 400 kHz two-line I2C-bus interface (at VDD = 1.8 V to 5.5 V)
 Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz,
8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)
 Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
 Minute and half minute interrupt
 Oscillator stop detection function
 Internal Power-On Reset (POR)
 Programmable offset register for frequency adjustment
3. Applications






1.
Digital still camera
Digital video camera
Printers
Copy machines
Mobile equipment
Battery powered devices
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCF85063TP
Name
Description
Version
HWSON8
plastic thermal enhanced very very thin
small outline package; no leads; 8
terminals;
body 2  3  0.75 mm
SOT1069-2
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF85063TP/1
PCF85063TP/1Z
tape and reel, 7 inch
1
935297365147
5. Marking
Table 3.
Marking codes
Product type number
Marking code
PCF85063TP/1
063
6. Block diagram
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Fig 1.
PCF85063TP
Product data sheet
Block diagram of PCF85063TP
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
7. Pinning information
7.1 Pinning
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For mechanical details, see Figure 27.
Fig 2.
Pin configuration for HWSON8 (PCF85063TP)
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
OSCI
1
input
oscillator input
OSCO
2
output
oscillator output
INT
3
output
interrupt output (open-drain)
VSS
4[1]
supply
ground supply voltage
SDA
5
input/output serial data line
SCL
6
input
serial clock input
CLKOUT
7
output
clock output (push-pull)
VDD
8
supply
supply voltage
[1]
PCF85063TP
Product data sheet
The die paddle (exposed pad) is connected to VSS and should be electrically isolated.
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Rev. 4 — 6 May 2015
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3 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8. Functional description
The PCF85063TP contains 11 8-bit registers with an auto-incrementing register address,
an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which
provides the source clock for the Real-Time Clock (RTC) and calender, and an I2C-bus
interface with a maximum data rate of 400 kbit/s.
The built-in address register will increment automatically after each read or write of a data
byte up to the register 0Ah. After register 0Ah, the auto-incrementing will wrap around to
address 00h (see Figure 3).
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Fig 3.
Handling address registers
All 11 registers (see Table 5) are designed as addressable 8-bit parallel registers although
not all bits are implemented. The first two registers (memory address 00h and 01h) are
used as control and status register. The register at address 02h is an offset register
allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses 04h
through 0Ah are used as counters for the clock function (seconds up to years counters).
The Seconds, Minutes, Hours, Days, Months, and Years registers are all coded in Binary
Coded Decimal (BCD) format. When one of the RTC registers is written or read, the
contents of all time counters are frozen. Therefore, faulty writing or reading of the clock
and calendar during a carry condition is prevented.
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 52
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NXP Semiconductors
PCF85063TP
Product data sheet
8.1 Registers organization
Table 5.
Registers overview
Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 8 on page 10.
Address
Register name
Bit
Reference
7
6
5
4
3
2
1
0
12_24
CAP_SEL
Control and status registers
00h
Control_1
EXT_TEST
-
STOP
SR
-
CIE
01h
Control_2
-
-
MI
HMI
TF
COF[2:0]
02h
Offset
MODE
OFFSET[6:0]
03h
RAM_byte
B[7:0]
Section 8.2.1
Section 8.2.2
Section 8.2.3
Section 8.2.4
Time and date registers
Rev. 4 — 6 May 2015
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04h
Seconds
OS
SECONDS (0 to 59)
Section 8.3.1
05h
Minutes
-
MINUTES (0 to 59)
Section 8.3.2
06h
Hours
-
-
07h
Days
-
-
DAYS (1 to 31)
08h
Weekdays
-
-
-
-
09h
Months
-
-
-
MONTHS (1 to 12)
0Ah
Years
YEARS (0 to 99)
AMPM
HOURS (1 to 12) in 12 hour mode
Section 8.3.3
HOURS (0 to 23) in 24 hour mode
Section 8.3.4
-
WEEKDAYS (0 to 6)
Section 8.3.5
Section 8.3.6
Section 8.3.7
PCF85063TP
Tiny Real-Time Clock/calendar
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2 Control registers
8.2.1 Register Control_1
Table 6.
Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
7
EXT_TEST
6
-
5
STOP
4
Value
-
2
CIE
1
external clock test mode
Section 8.2.1.1
normal mode
1
external clock test mode
0
unused
-
STOP bit
Section 8.2.1.2
0[1]
RTC clock runs
1
RTC clock is stopped; all RTC divider chain
flip-flops are asynchronously set logic 0
software reset
0[1]
no software reset
1
initiate software reset[2]; this bit always
returns a 0 when read
0
-
correction interrupt enable
Section 8.2.3
no correction interrupt generated
1
interrupt pulses are generated at every
correction cycle
12 or 24 hour mode
0[1]
24 hour mode is selected
1
12 hour mode is selected
CAP_SEL
internal oscillator capacitor selection for
quartz crystals with a corresponding load
capacitance
0[1]
7 pF
1
12.5 pF
[1]
Default value.
[2]
For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.2.1.3).
PCF85063TP
Product data sheet
Section 8.2.1.3
unused
0[1]
12_24
0
Reference
0[1]
SR
3
Description
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Rev. 4 — 6 May 2015
Section 8.3.3
-
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2.1.1
EXT_TEST: external clock test mode
A test mode is available which allows for on-board testing. In this mode, it is possible to
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST in register Control_1. Then
pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the
signal applied to pin CLKOUT.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided
down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a
known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP
must be cleared before the prescaler can operate again.)
From a stop condition, the first 1 second increment will take place after 32 positive edges
on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.
Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When
entering the test mode, no assumption as to the state of the prescaler can be made.
Operation example:
1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1)
2. Set STOP (register Control_1, bit STOP = 1)
3. Clear STOP (register Control_1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to pin CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to pin CLKOUT
8. Read time registers to see the second change
Repeat 7 and 8 for additional increments.
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2.1.2
STOP: STOP bit function
The function of the STOP bit (see Figure 4) is to allow for accurate starting of the time
circuits. The STOP bit function causes the upper part of the prescaler (F2 to F14) to be
held in reset and thus no 1 Hz ticks are generated. It also stops the output of clock
frequencies lower than 8 kHz on pin CLKOUT.
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Fig 4.
STOP bit functional diagram
The time circuits can then be set and do not increment until the STOP bit is released (see
Figure 5 and Table 7).
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
Table 7.
First increment of time circuits after STOP bit release
Bit
Prescaler bits
STOP
F0F1-F2 to F14
[1]
1 Hz tick
Time
Comment
hh:mm:ss
Clock is running normally
0
12:45:12
01-0 0001 1101 0100
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
12:45:12
prescaler is reset; time circuits are frozen
08:00:00
prescaler is reset; time circuits are frozen
XX-0 0000 0000 0000
08:00:00
prescaler is now running
XX-1 0000 0000 0000
08:00:00
-
XX-0 1000 0000 0000
08:00:00
-
08:00:00
-
:
:
:
11-1 1111 1111 1110
08:00:00
-
00-0 0000 0000 0001
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:01
-
:
:
:
XX-0 0000 0000 0000
New time is set by user
1
XX-0 0000 0000 0000
STOP bit is released by user
0
XX-1 1000 0000 0000
WR
V
08:00:01
-
00-0 0000 0000 0000
08:00:01
-
10-0 0000 0000 0000
08:00:01
-
:
:
:
11-1 1111 1111 1110
08:00:01
-
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
11-1 1111 1111 1111
V
DDD
[1]
F0 is clocked at 32.768 kHz.
The lower two stages of the prescaler (F0 and F1) are not reset. And because the I2C-bus
is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is
between zero and one 8.192 kHz cycle (see Figure 5).
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VWRSUHOHDVHG
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Fig 5.
DDD
STOP bit release timing
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 7) and the unknown state of the 32 kHz clock.
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2.1.3
Software reset
A reset is automatically generated at power-on. A reset can also be initiated with the
software reset command. Software reset command means setting bits 6, 4, and 3 in
register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence
01011000 (58h), see Figure 6.
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Fig 6.
Software reset command
In reset state all registers are set according to Table 8 and the address pointer returns to
address 00h.
Table 8.
Register reset values
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_1
0
0
0
0
0
0
0
0
01h
Control_2
0
0
0
0
0
0
0
0
02h
Offset
0
0
0
0
0
0
0
0
03h
RAM_byte
0
0
0
0
0
0
0
0
04h
Seconds
1
0
0
0
0
0
0
0
05h
Minutes
0
0
0
0
0
0
0
0
06h
Hours
0
0
0
0
0
0
0
0
07h
Days
0
0
0
0
0
0
0
1
08h
Weekdays
0
0
0
0
0
1
1
0
09h
Months
0
0
0
0
0
0
0
1
0Ah
Years
0
0
0
0
0
0
0
0
The PCF85063TP resets to:
Time — 00:00:00
Date — 20000101
Weekday — Saturday
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2.2 Register Control_2
Table 9.
Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol
Value
Description
7 to 6
-
00
unused
5
MI
4
minute interrupt
0[1]
disabled
1
enabled
HMI
3
half minute interrupt
0[1]
disabled
1
enabled
TF
timer flag
0[1]
no timer interrupt generated
1
2 to 0
[1]
8.2.2.1
COF[2:0]
see Table 11
flag set when timer interrupt generated
CLKOUT control
Default value.
MI and HMI: minute and half minute interrupt
The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for
generating interrupt pulses on pin INT; see Figure 7. The timers are running in sync with
the seconds counter (see Table 19 on page 17).
The minute and half minute interrupts must only be used when the frequency offset is set
to normal mode (MODE = 0), see Section 8.2.3. In normal mode, the interrupt pulses on
pin INT are 1⁄64 s wide.
When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When
starting HMI, the first interrupt will be generated after 1 second to 29 seconds.
Subsequent periods do not have such a delay. The timers can be enabled independently
from one another. However, a minute interrupt enabled on top of a half minute interrupt is
not distinguishable.
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In this example, the TF flag is not cleared after an interrupt.
Fig 7.
PCF85063TP
Product data sheet
INT example for MI
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
Table 10.
Effect of bits MI and HMI on INT generation
Minute interrupt (bit MI)
Half minute interrupt (bit HMI)
Result
0
0
no interrupt generated
1
0
an interrupt every minute
0
1
an interrupt every 30 s
1
1
an interrupt every 30 s
The duration of the timer is affected by the register Offset (see Section 8.2.3). Only when
OFFSET[6:0] has the value 00h the periods are consistent.
8.2.2.2
TF: timer flag
The timer flag (bit TF) is set logic 1 on the first trigger of MI or HMI and remains set until it
is cleared by command.
8.2.2.3
COF[2:0]: Clock output frequency
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] bits in the register Control_2. Frequencies of 32.768 kHz (default) down to 1 Hz
can be generated for use as a system clock, microcontroller clock, input to a charge
pump, or for calibration of the oscillator.
Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by
setting COF[2:0] to 111. When disabled, the CLKOUT is LOW.
The duty cycle of the selected clock is not controlled but due to the nature of the clock
generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.
The STOP bit function can also affect the CLKOUT signal, depending on the selected
frequency. When the STOP bit is set logic 1, the CLKOUT pin generates a continuous
LOW for those frequencies that can be stopped. For more details of the STOP bit function,
see Section 8.2.1.2.
Table 11.
PCF85063TP
Product data sheet
CLKOUT frequency selection
COF[2:0]
CLKOUT frequency (Hz) Typical duty cycle[1]
Effect of STOP bit
000[2]
32768
60 : 40 to 40 : 60
no effect
001
16384
50 : 50
no effect
010
8192
50 : 50
no effect
011
4096
50 : 50
CLKOUT = LOW
100
2048
50 : 50
CLKOUT = LOW
101
1024
50 : 50
CLKOUT = LOW
110
1[3]
50 : 50
CLKOUT = LOW
111
CLKOUT = LOW
-
-
[1]
Duty cycle definition: % HIGH-level time : % LOW-level time.
[2]
Default value.
[3]
1 Hz clock pulses are affected by offset correction pulses.
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
8.2.3 Register Offset
The PCF85063TP incorporates an offset register (address 02h) which can be used to
implement several functions, such as:
• Accuracy tuning
• Aging adjustment
• Temperature compensation
Table 12.
Offset - offset register (address 02h) bit description
Bit
Symbol
7
MODE
6 to 0
[1]
Value
Description
offset mode
OFFSET[6:0]
0[1]
normal mode: offset is made once every two
hours
1
course mode: offset is made every 4 minutes
offset value
see Table 13
Default value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB
introduces an offset of 4.069 ppm. The offset value is coded in two’s complement giving a
range of +63 LSB to 64 LSB.
Table 13.
Offset values
OFFSET[6:0]
Offset value in
decimal
Offset value in ppm
Normal mode
MODE = 0
Fast mode
MODE = 1
0111111
+63
+273.420
+256.347
0111110
+62
+269.080
+252.278
:
:
:
:
0000010
+2
+8.680
+8.138
0000001
+1
+4.340
+4.069
0
0[1]
0[1]
0000000[1]
1111111
1
4.340
4.069
1111110
2
8.680
8.138
:
:
:
:
1000001
63
273.420
256.347
1000000
64
277.760
260.416
[1]
Default value.
The correction is made by adding or subtracting clock correction pulses, thereby changing
the period of a single second but not by changing the oscillator frequency.
It is possible to monitor when correction pulses are applied. To enable correction interrupt
generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a
pulse is generated on pin INT. The pulse width depends on the correction mode. If
multiple correction pulses are applied, an interrupt pulse is generated for each correction
pulse applied.
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
8.2.3.1
Correction when MODE = 0
The correction is triggered once every two hours and then correction pulses are applied
once per minute until the programmed correction values have been implemented.
Table 14.
Correction pulses for MODE = 0
Correction value
Update every nth hour Minute
Correction pulses on
INT per minute[1]
+1 or 1
2
00
1
+2 or 2
2
00 and 01
1
+3 or 3
2
00, 01, and 02
1
:
:
:
:
+59 or 59
2
00 to 58
1
+60 or 60
2
00 to 59
1
+61 or 61
2
00 to 59
1
2nd and next hour
00
1
+62 or 62
2
00 to 59
1
2nd and next hour
00 and 01
1
+63 or 63
02
00 to 59
1
2nd and next hour
00, 01, and 02
1
02
00 to 59
1
2nd and next hour
00, 01, 02, and 03
1
64
[1]
The correction pulses on pin INT are 1⁄64 s wide.
In MODE = 0, any timer or clock output using a frequency below 64 Hz is affected by the
clock correction (see Table 15).
Table 15.
Effect of correction pulses on frequencies for MODE = 0
Frequency (Hz)
Effect of correction
CLKOUT
32768
no effect
16384
no effect
8192
no effect
4096
no effect
2048
no effect
1024
no effect
1
affected
Timer source clock
4096
8.2.3.2
no effect
64
no effect
1
affected
1⁄
60
affected
Correction when MODE = 1
The correction is triggered once every four minutes and then correction pulses are applied
once per second up to a maximum of 60 pulses. When correction values greater than 60
pulses are used, additional correction pulses are made in the 59th second.
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
Clock correction is made more frequently in MODE = 1; however, this can result in higher
power consumption.
Table 16.
Correction pulses for MODE = 1
Correction value
Update every nth
minute
Second
+1 or 1
2
00
1
+2 or 2
2
00 and 01
1
+3 or 3
2
00, 01, and 02
1
:
:
:
:
Correction pulses on
INT per second[1]
+59 or 59
2
00 to 58
1
+60 or 60
2
00 to 59
1
+61 or 61
2
00 to 58
1
2
59
2
+62 or 62
+63 or 63
64
[1]
2
00 to 58
1
2
59
3
2
00 to 58
1
2
59
4
2
00 to 58
1
2
59
5
The correction pulses on pin INT are 1⁄1024 s wide. For multiple pulses, they are repeated at an interval of
s.
1⁄
512
In MODE = 1, any timer source clock using a frequency below 1.024 kHz is also affected
by the clock correction (see Table 17).
Table 17.
Effect of correction pulses on frequencies for MODE = 1
Frequency (Hz)
Effect of correction
CLKOUT
32768
no effect
16384
no effect
8192
no effect
4096
no effect
2048
no effect
1024
no effect
1
affected
Timer source clock
PCF85063TP
Product data sheet
4096
no effect
64
affected
1
affected
1⁄
60
affected
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Tiny Real-Time Clock/calendar
8.2.3.3
Offset calibration workflow
The calibration offset has to be calculated based on the time. Figure 8 shows the workflow
how the offset register values can be calculated:
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Fig 8.
PCF85063TP
Product data sheet
Offset calibration calculation workflow
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
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With the offset calibration an accuracy of 2 ppm (0.5  offset per LSB) can be reached (see
Table 13).
1 ppm corresponds to a time deviation of 0.0864 seconds per day.
(1) 3 correction pulses in MODE = 0 correspond to 13.02 ppm.
(2) 4 correction pulses in MODE = 1 correspond to 16.276 ppm.
(3) Reachable accuracy zone.
Fig 9.
Result of offset calibration
8.2.4 Register RAM_byte
The PCF85063TP provides a free RAM byte, which can be used for any purpose, for
example, status byte of the system.
Table 18.
Bit
7 to 0
RAM_byte - 8-bit RAM register (address 03h) bit description
Symbol
Value
Description
B[7:0]
00000000[1] to
RAM content
11111111
[1]
Default value.
8.3 Time and date registers
Most of the registers are coded in the BCD format to simplify application use.
8.3.1 Register Seconds
Table 19.
Seconds - seconds register (address 04h) bit description
Bit
Symbol
7
OS
6 to 4
[1]
PCF85063TP
Product data sheet
Place value Description
oscillator stop
SECONDS
3 to 0
Value
0
-
clock integrity is guaranteed
1[1]
-
clock integrity is not
guaranteed; oscillator has
stopped or has been
interrupted
0[1] to 5
ten’s place
0[1] to 9
unit place
actual seconds coded in BCD
format, see Table 20
Default value.
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NXP Semiconductors
Tiny Real-Time Clock/calendar
Table 20.
Seconds coded in BCD format
Seconds value in
decimal
Digit (unit place)
Bit 6
Bit 3
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
00[1]
0
0
0
0
0
0
0
01
0
0
0
0
0
0
1
02
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
09
0
0
0
1
0
0
1
10
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
58
1
0
1
1
0
0
0
59
1
0
1
1
0
0
1
[1]
8.3.1.1
Upper-digit (ten’s place)
Default value.
OS: Oscillator stop
When the oscillator of the PCF85063TP is stopped, the OS flag is set. The oscillator can
be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to
ground. The oscillator is considered to be stopped during the time between power-on and
stable crystal resonance. This time can be in the range of 200 ms to 2 s depending on
crystal type, temperature, and supply voltage.
The flag remains set until cleared by command (see Figure 10). If the flag cannot be
cleared, then the oscillator is not running. This method can be used to monitor the
oscillator and to determine if the supply voltage has reduced to the point where oscillation
fails.
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Fig 10. OS flag
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
8.3.2 Register Minutes
Table 21.
Minutes - minutes register (address 05h) bit description
Bit
Symbol
Value
Place value Description
7
-
0
-
unused
MINUTES
0[1]
ten’s place
actual minutes coded in BCD
format
6 to 4
[1]
to 5
0[1] to 9
3 to 0
unit place
Default value.
8.3.3 Register Hours
Table 22.
Hours - hours register (address 06h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
00
-
12 hour
mode[1]
5
AMPM
4
unused
AM/PM indicator
HOURS
3 to 0
24 hour
mode[1]
5 to 4
HOURS
3 to 0
0[2]
-
AM
1
-
PM
0[2] to 1
ten’s place
0[2]
unit place
to 9
0[2] to 2
ten’s place
0[2]
unit place
to 9
[1]
Hour mode is set by the 12_24 bit in register Control_1.
[2]
Default value.
actual hours in 12 hour mode
coded in BCD format
actual hours in 24 hour mode
coded in BCD format
8.3.4 Register Days
Table 23.
Days - days register (address 07h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
00
-
unused
5 to 4
DAYS[1]
0[2] to 3
ten’s place
actual day coded in BCD format
0[3]
unit place
3 to 0
to 9
[1]
If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCF85063TP
compensates for leap years by adding a 29th day to February.
[2]
Default value.
[3]
Default value is 1.
8.3.5 Register Weekdays
Table 24.
PCF85063TP
Product data sheet
Weekdays - weekdays register (address 08h) bit description
Bit
Symbol
Value
Description
7 to 3
-
00000
unused
2 to 0
WEEKDAYS
0 to 6
actual weekday values, see Table 25
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Tiny Real-Time Clock/calendar
Table 25.
Weekday assignments
Day[1]
Bit
2
1
0
Sunday
0
0
0
Monday
0
0
1
Tuesday
0
1
0
Wednesday
0
1
1
Thursday
1
0
0
Friday
1
0
1
Saturday[2]
1
1
0
[1]
Definition may be reassigned by the user.
[2]
Default value.
8.3.6 Register Months
Table 26.
Months - months register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7 to 5
-
000
-
unused
4
MONTHS
0 to 1
ten’s place
0 to 9
unit place
actual month coded in BCD
format, see Table 27
3 to 0
Table 27.
Month assignments in BCD format
Month
January[1]
Product data sheet
Digit (unit place)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
February
0
0
0
1
0
March
0
0
0
1
1
April
0
0
1
0
0
May
0
0
1
0
1
June
0
0
1
1
0
July
0
0
1
1
1
August
0
1
0
0
0
September
0
1
0
0
1
October
1
0
0
0
0
November
1
0
0
0
1
December
1
0
0
1
0
[1]
PCF85063TP
Upper-digit
(ten’s place)
Default value.
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NXP Semiconductors
Tiny Real-Time Clock/calendar
8.3.7 Register Years
Table 28.
Bit
7 to 4
Years - years register (0Ah) bit description
Symbol
Value
Place value Description
YEARS
0[1]
to 9
ten’s place
0[1]
to 9
unit place
3 to 0
[1]
actual year coded in BCD format
Default value.
8.4 Setting and reading the time
Figure 11 shows the data flow and data dependencies starting from the 1 Hz clock tick.
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Fig 11. Data flow for the time function
During read/write operations, the time counting circuits (memory locations 04h through
0Ah) are blocked.
The blocking prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read/write access
is serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 12).
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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NXP Semiconductors
Tiny Real-Time Clock/calendar
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Fig 12. Access time for read/write operations
Because of this method, it is very important to make a read or write access in one go, that
is, setting or reading seconds through to years should be made in one single access.
Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time will increment between the two
accesses. A similar problem exists when reading. A roll-over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address (see Table 29 on page 25) for write
(A2h)
2. Set the address pointer to 4 (Seconds) by sending 04h
3. Send a RESTART condition or STOP followed by START
4. Send the slave address for read (A3h)
5. Read Seconds
6. Read Minutes
7. Read Hours
8. Read Days
9. Read Weekdays
10. Read Months
11. Read Years
12. Send a STOP condition
PCF85063TP
Product data sheet
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NXP Semiconductors
Tiny Real-Time Clock/calendar
9. Characteristics of the I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
are interpreted as a control signal (see Figure 13).
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Fig 13. Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14).
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Fig 14. Definition of START and STOP conditions
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 15).
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
23 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
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Fig 15. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered)
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition
Acknowledgement on the I2C-bus is shown in Figure 16.
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Fig 16. Acknowledgement on the I2C-bus
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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Tiny Real-Time Clock/calendar
9.5 I2C-bus protocol
9.5.1 Addressing
One I2C-bus slave address (1010001) is reserved for the PCF85063TP. The entire
I2C-bus slave address byte is shown in Table 29.
Table 29.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
LSB
1
0
1
0
0
0
1
R/W
After a START condition, the I2C slave address has to be sent to the PCF85063TP device.
The R/W bit defines the direction of the following single or multiple byte data transfer
(R/W = 0 for writing, R/W = 1 for reading). For the format and the timing of the START
condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I2C-bus
characteristics (see Ref. 12 “UM10204”). In the write mode, a data transfer is terminated
by sending either the STOP condition or the START condition of the next data transfer.
9.5.2 Clock and calendar READ or WRITE cycles
The I2C-bus configuration for the different PCF85063TP READ and WRITE cycles is
shown in Figure 17 and Figure 18. The register address is a 4-bit value that defines which
register will be accessed next. The upper 4 bits of the register address are not used.
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Fig 17. Master transmits to slave receiver (WRITE mode)
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
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For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a repeated
START (Sr).
Fig 18. Master reads after setting register address (WRITE register address; READ data)
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
10. Internal circuitry
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Fig 19. Device diode protection diagram of PCF85063TP
11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
12. Limiting values
Table 30. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
PCF85063TP
Product data sheet
Symbol
Parameter
Conditions
VDD
supply voltage
IDD
supply current
VI
input voltage
VO
output voltage
II
input current
at any input
at any output
on pins SCL, SDA, OSCI
IO
output current
Ptot
total power dissipation
VESD
electrostatic discharge
voltage
Min
Max
Unit
0.5
+6.5
V
50
+50
mA
0.5
+6.5
V
0.5
+6.5
V
10
+10
mA
10
+10
mA
-
300
mW
HBM
[1]
-
5000
V
CDM
[2]
-
1500
V
-
200
mA
65
+150
C
40
+85
C
Ilu
latch-up current
[3]
Tstg
storage temperature
[4]
Tamb
ambient temperature
operating device
[1]
Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.
[2]
Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[3]
Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
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Tiny Real-Time Clock/calendar
13. Characteristics
Table 31. Static characteristics
VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 7 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
interface inactive;
fSCL = 0 Hz
[1]
0.9
-
5.5
V
interface active;
fSCL = 400 kHz
[1]
1.8
-
5.5
V
VDD = 3.3 V
[2]
Supplies
VDD
IDD
supply current
interface inactive;
fSCL = 0 Hz
Tamb = 25 C
-
220
450
nA
-
250
500
nA
Tamb = 85 C
-
470
600
nA
interface active;
fSCL = 400 kHz
-
18
50
A
Tamb = 50 C
[3]
Inputs[4]
VI
input voltage
VSS
-
5.5
V
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
ILI
input leakage current
VI = VSS or VDD
post ESD event
Ci
[5]
input capacitance
0.7VDD
-
VDD
V
-
0
-
A
0.15
-
+0.15
A
-
-
7
pF
Outputs
VOH
HIGH-level output voltage
on pin CLKOUT
0.8VDD
-
VDD
V
VOL
LOW-level output voltage
on pins SDA, INT,
CLKOUT
VSS
-
0.2VDD
V
IOH
HIGH-level output current
output source current;
VOH = 2.9 V;
VDD = 3.3 V;
on pin CLKOUT
1
3
-
mA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V;
VDD = 3.3 V
on pin SDA
3
8.5
-
mA
on pin INT
2
6
-
mA
on pin CLKOUT
1
3
-
mA
PCF85063TP
Product data sheet
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PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
Table 31. Static characteristics …continued
VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 7 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fosc/fosc
relative oscillator frequency
variation
VDD = 200 mV;
Tamb = 25 C
-
0.075
-
ppm
CL(itg)
integrated load capacitance
on pins OSCO, OSCI
CL = 7 pF
4.2
7
9.8
pF
CL = 12.5 pF
7.5
12.5
17.5
pF
-
-
100
k
Oscillator
[6]
series resistance
Rs
[1]
For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V.
[2]
Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.
[3]
Tested on sample basis.
[4]
The I2C-bus interface of PCF85063TP is 5 V tolerant.
[5]
Implicit by design.
[6]
OSCI
OSCO
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: C L  itg  = -------------------------------------------.
 C OSCI + C OSCO 
C
C

DDD
,''
—$
I6&/N+]
Tamb = 25 C; CLKOUT disabled.
(1) VDD = 5.0 V.
(2) VDD = 3.3 V.
Fig 20. Typical IDD with respect to fSCL
PCF85063TP
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DDD
,''
Q$
7HPSHUDWXUHž&
CL(itg) = 7 pF; CLKOUT disabled.
(1) VDD = 5.5 V.
(2) VDD = 3.3 V.
DDD
,''
Q$
7HPSHUDWXUHž&
CL(itg) = 12.5 pF; CLKOUT disabled.
(1) VDD = 5.5 V.
(2) VDD = 3.3 V.
Fig 21. Typical IDD as a function of temperature
PCF85063TP
Product data sheet
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DDD
,''
—$
9''9
Tamb = 25 C; fCLKOUT = 32768 Hz.
(1) 47 pF CLKOUT load.
(2) 22 pF CLKOUT load.
DDD
,''
Q$
9''9
Tamb = 25 C; CLKOUT disabled.
(1) CL(itg) = 12.5 pF.
(2) CL(itg) = 7 pF.
Fig 22. Typical IDD with respect to VDD
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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DDD
,''
Q$
56NŸ
VDD = 3.3 V; CLKOUT disabled.
(1) CL(itg) = 12.5 pF; 50 C; maximum value.
(2) CL(itg) = 7 pF; 50 C; maximum value.
(3) CL(itg) = 12.5 pF; 25 C; typical value.
(4) CL(itg) = 7 pF; 25 C; typical value.
Fig 23. IDD with respect to quartz RS
DDD
ǻIRVF
SSP
9''9
Tamb = 25 C.
(1) CL(itg) = 7 pF.
(2) CL(itg) = 12.5 pF.
Fig 24. Oscillator frequency variation with respect to VDD
PCF85063TP
Product data sheet
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Table 32. I2C-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH
with an input voltage swing of VSS to VDD[1].
Symbol
Parameter
Cb
capacitive load for
each bus line
fSCL
SCL clock frequency
tHD;STA
hold time (repeated)
START condition
tSU;STA
Conditions
Min
Max
Unit
-
400
pF
0
400
kHz
0.6
-
s
set-up time for a
repeated START
condition
0.6
-
s
tLOW
LOW period of the
SCL clock
1.3
-
s
tHIGH
HIGH period of the
SCL clock
0.6
-
s
tr
rise time of both SDA
and SCL signals
20
300
ns
tf
fall time of both SDA
and SCL signals
20  (VDD / 5.5 V) 300
ns
tBUF
bus free time between
a STOP and START
condition
1.3
-
s
tSU;DAT
data set-up time
100
-
ns
tHD;DAT
data hold time
0
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
s
tVD;DAT
data valid time
0
0.9
s
tVD;ACK
data valid
acknowledge time
0
0.9
s
tSP
pulse width of spikes
that must be
suppressed by the
input filter
0
50
ns
[2]
[3][4]
[1]
A detailed description of the I2C-bus specification is given in Ref. 12 “UM10204”.
[2]
I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
[4]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
SURWRFRO
67$57
FRQGLWLRQ
6
W6867$
ELW
06%
$
W/2:
ELW
$
W+,*+
I
ELW
5:
DFNQRZOHGJH
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6723
FRQGLWLRQ
3
6&/
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6'$
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W68'$7
W+''$7
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W9'$&.
W68672
DDD
Fig 25. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %
PCF85063TP
Product data sheet
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14. Application information
9''
6'$
0$67(5
75$160,77(5
5(&(,9(5
6&/
)
Q)
9''
,17
6&/
26&,
26&2
9''
3&)73
6'$
5
966
5
5SXOOXSUHVLVWRU
5
6'$ 6&/
,&EXV
WU
&E
DDD
A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up
supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC
may operate for weeks.
Fig 26. Application diagram for PCF85063TP
PCF85063TP
Product data sheet
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15. Package outline
+:621SODVWLFWKHUPDOHQKDQFHGYHU\YHU\WKLQVPDOORXWOLQHSDFNDJHQROHDGV
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Fig 27. Package outline SOT1069-2 (HWSON8) of PCF85063TP
PCF85063TP
Product data sheet
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© NXP Semiconductors N.V. 2015. All rights reserved.
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Tiny Real-Time Clock/calendar
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
17.1 Tape and reel information
For tape and reel packing information, see Ref. 11 “SOT1069-2_147”.
PCF85063TP
Product data sheet
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18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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Tiny Real-Time Clock/calendar
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 33 and 34
Table 33.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 34.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.
PCF85063TP
Product data sheet
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Tiny Real-Time Clock/calendar
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Footprint information
PCF85063TP
Product data sheet
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41 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+:621SDFNDJH
627
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Fig 29. Footprint information for reflow soldering of SOT1069-2 (HWSON8) of PCF85063TP
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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42 of 52
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF85063TP
Product data sheet
20. Appendix
20.1 Real-Time Clock selection
Table 35.
Selection of Real-Time Clocks
Type name
Alarm, Timer, Interrupt Interface IDD,
Battery Timestamp,
Watchdog
output
typical (nA) backup tamper input
Rev. 4 — 6 May 2015
All information provided in this document is subject to legal disclaimers.
AEC-Q100
compliant
Special features
Packages
PCF85063TP
-
1
I2C
220
-
-
-
basic functions only, no
alarm
HXSON8
PCF85063A
X
1
I2C
220
-
-
-
tiny package
SO8, DFN2626-10,
TSSOP8
PCF85063B
X
1
SPI
220
-
-
-
tiny package
DFN2626-10
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100 s
SO8, TSSOP10,
TSSOP8,
DFN2626-10
2
PCF85263B
X
2
SPI
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s
TSSOP10,
DFN2626-10
PCF85363A
X
2
I2C
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s,
64 Byte RAM
TSSOP10, TSSOP8,
DFN2626-10
PCF85363B
X
2
SPI
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s,
64 Byte RAM
TSSOP10,
DFN2626-10
PCF2123
X
1
SPI
100
-
-
-
lowest power 100 nA in
operation
TSSOP14, HVQFN16
PCF8523
X
2
I2C
150
X
-
-
lowest power 150 nA in
operation, FM+ 1 MHz
SO8, HVSON8,
TSSOP14, WLCSP
PCF8563
X
1
I2C
250
-
-
-
-
SO8, TSSOP8,
HVSON10
PCA8565
X
1
I2C
600
-
-
grade 1
high robustness,
Tamb40 C to 125 C
TSSOP8, HVSON10
PCA8565A
X
1
I2C
600
-
-
-
integrated oscillator caps,
Tamb40 C to 125 C
WLCSP
PCF8564A
X
1
I2C
250
-
-
-
integrated oscillator caps
WLCSP
PCF85063TP
X
Tiny Real-Time Clock/calendar
43 of 52
© NXP Semiconductors N.V. 2015. All rights reserved.
PCF85263A
I2C
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of Real-Time Clocks …continued
Rev. 4 — 6 May 2015
All information provided in this document is subject to legal disclaimers.
Type name
Alarm, Timer, Interrupt Interface IDD,
Battery Timestamp,
Watchdog
output
typical (nA) backup tamper input
AEC-Q100
compliant
Special features
PCF2127
X
1
I2C and
SPI
500
X
X
-
temperature
SO16
compensated, quartz built
in, calibrated, 512 Byte
RAM
PCF2127A
X
1
I2C and
SPI
500
X
X
-
temperature
SO20
compensated, quartz built
in, calibrated, 512 Byte
RAM
PCF2129
X
1
I2C and
SPI
500
X
X
-
temperature
SO16
compensated, quartz built
in, calibrated
PCF2129A
X
1
I2C and
SPI
500
X
X
-
temperature
SO20
compensated, quartz built
in, calibrated
PCA2129
X
1
I2C and
SPI
500
X
X
grade 3
temperature
SO16
compensated, quartz built
in, calibrated
PCA21125
X
1
SPI
820
-
-
grade 1
high robustness,
Tamb40 C to 125 C
NXP Semiconductors
PCF85063TP
Product data sheet
Table 35.
Packages
TSSOP14
PCF85063TP
Tiny Real-Time Clock/calendar
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21. Abbreviations
Table 36.
Acronym
PCF85063TP
Product data sheet
Abbreviations
Description
BCD
Binary Coded Decimal
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
POR
Power-On Reset
RTC
Real-Time Clock
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
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22. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10366 — HVQFN application information
[3]
AN11247 — Improved timekeeping accuracy with PCF85063, PCF8523 and
PCF2123 using an external temperature sensor
[4]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6]
IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9]
JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] SOT1069-2_147 — HWSON8; Reel pack, SMD, 7", packing information
[12] UM10204 — I2C-bus specification and user manual
[13] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and
PCF2123, PCA2125
[14] UM10569 — Store and transport requirements
[15] UM10698 — User manual for I2C-bus RTC demo board OM11059A
PCF85063TP
Product data sheet
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Rev. 4 — 6 May 2015
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23. Revision history
Table 37.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF85063TP v.4
20150506
Product data sheet
-
PCF85063TP v.3
Modifications:
•
•
•
Corrected rise and fall time specification according to the
I2 C
standard, see Table 32
Adjusted Section 8.2.3
Enhanced Section 8.2.2.1
PCF85063TP v.3
20130711
Product data sheet
-
PCF85063TP v.2
PCF85063TP v.2
20130415
Product data sheet
-
PCF85063TP v.1
PCF85063TP v.1
20130122
Objective data sheet
-
-
PCF85063TP
Product data sheet
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NXP Semiconductors
Tiny Real-Time Clock/calendar
24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF85063TP
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
48 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF85063TP
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
49 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3
Registers overview . . . . . . . . . . . . . . . . . . . . . .5
Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .6
First increment of time circuits after STOP bit
release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Register reset values . . . . . . . . . . . . . . . . . . . .10
Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . . 11
Effect of bits MI and HMI on INT generation . .12
CLKOUT frequency selection . . . . . . . . . . . . .12
Offset - offset register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .13
Correction pulses for MODE = 0 . . . . . . . . . . .14
Effect of correction pulses on frequencies for
MODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Correction pulses for MODE = 1 . . . . . . . . . . .15
Effect of correction pulses on frequencies for
MODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RAM_byte - 8-bit RAM register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .17
Seconds - seconds register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Seconds coded in BCD format . . . . . . . . . . . .18
Minutes - minutes register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Hours - hours register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Days - days register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Weekdays - weekdays register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .19
Weekday assignments . . . . . . . . . . . . . . . . . . .20
Months - months register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Month assignments in BCD format . . . . . . . . . .20
Years - years register (0Ah) bit description. . . .21
I2C slave address byte . . . . . . . . . . . . . . . . . . .25
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .28
Static characteristics . . . . . . . . . . . . . . . . . . . .29
I2C-bus characteristics . . . . . . . . . . . . . . . . . . .34
SnPb eutectic process (from J-STD-020D) . . .40
Lead-free process (from J-STD-020D) . . . . . .40
Selection of Real-Time Clocks . . . . . . . . . . . . .43
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .45
Revision history . . . . . . . . . . . . . . . . . . . . . . . .47
PCF85063TP
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
50 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Block diagram of PCF85063TP . . . . . . . . . . . . . . .2
Pin configuration for HWSON8 (PCF85063TP) . . .3
Handling address registers . . . . . . . . . . . . . . . . . .4
STOP bit functional diagram . . . . . . . . . . . . . . . . .8
STOP bit release timing . . . . . . . . . . . . . . . . . . . . .9
Software reset command . . . . . . . . . . . . . . . . . . .10
INT example for MI . . . . . . . . . . . . . . . . . . . . . . . 11
Offset calibration calculation workflow . . . . . . . . .16
Result of offset calibration . . . . . . . . . . . . . . . . . .17
OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Data flow for the time function . . . . . . . . . . . . . . .21
Access time for read/write operations . . . . . . . . .22
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Definition of START and STOP conditions. . . . . .23
System configuration . . . . . . . . . . . . . . . . . . . . . .24
Acknowledgement on the I2C-bus . . . . . . . . . . . .24
Master transmits to slave receiver
(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Master reads after setting register address
(WRITE register address; READ data) . . . . . . . .26
Device diode protection diagram of
PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Typical IDD with respect to fSCL . . . . . . . . . . . . . .30
Typical IDD as a function of temperature . . . . . . .31
Typical IDD with respect to VDD . . . . . . . . . . . . . .32
IDD with respect to quartz RS . . . . . . . . . . . . . . . .33
Oscillator frequency variation with respect
to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
I2C-bus timing diagram; rise and fall times
refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .35
Application diagram for PCF85063TP . . . . . . . . .36
Package outline SOT1069-2 (HWSON8) of
PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Footprint information for reflow soldering of
SOT1069-2 (HWSON8) of PCF85063TP . . . . . .42
PCF85063TP
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
51 of 52
PCF85063TP
NXP Semiconductors
Tiny Real-Time Clock/calendar
28. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.3
8.2.3.1
8.2.3.2
8.2.3.3
8.2.4
8.3
8.3.1
8.3.1.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.4
9
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
10
11
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Registers organization . . . . . . . . . . . . . . . . . . . 5
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 6
Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 6
EXT_TEST: external clock test mode . . . . . . . . 7
STOP: STOP bit function . . . . . . . . . . . . . . . . . 8
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11
MI and HMI: minute and half minute interrupt. 11
TF: timer flag . . . . . . . . . . . . . . . . . . . . . . . . . 12
COF[2:0]: Clock output frequency . . . . . . . . . 12
Register Offset . . . . . . . . . . . . . . . . . . . . . . . . 13
Correction when MODE = 0 . . . . . . . . . . . . . . 14
Correction when MODE = 1 . . . . . . . . . . . . . . 14
Offset calibration workflow . . . . . . . . . . . . . . . 16
Register RAM_byte . . . . . . . . . . . . . . . . . . . . 17
Time and date registers . . . . . . . . . . . . . . . . . 17
Register Seconds . . . . . . . . . . . . . . . . . . . . . . 17
OS: Oscillator stop . . . . . . . . . . . . . . . . . . . . . 18
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 19
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 19
Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 19
Register Months . . . . . . . . . . . . . . . . . . . . . . . 20
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 21
Setting and reading the time. . . . . . . . . . . . . . 21
Characteristics of the I2C-bus interface . . . . 23
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
START and STOP conditions . . . . . . . . . . . . . 23
System configuration . . . . . . . . . . . . . . . . . . . 23
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock and calendar READ or WRITE cycles . 25
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12
13
14
15
16
17
17.1
18
18.1
18.2
18.3
18.4
19
20
20.1
21
22
23
24
24.1
24.2
24.3
24.4
25
26
27
28
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Tape and reel information . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Footprint information . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock selection . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
36
37
38
38
38
39
39
39
39
40
41
43
43
45
46
47
48
48
48
48
49
49
50
51
52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 6 May 2015
Document identifier: PCF85063TP
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