STR-L400 Series Application Note STR-L400 Series Application Note Rev. 1.2 (Rev.1.2) SANKEN ELECTRIC CO., LTD. http://www.sanken-ele.co.jp Copy Right: SANKEN ELECTRIC CO., LTD. Page.1 STR-L400 Series Application Note Rev. 1.2 Contents 1. General Descriptions ------------------------------------------ 4 2. Features and Product Lineup ------------------------------------------ 5 3. Functional Block Diagram and Terminal List ------------------------------------------ 6 4. Package Information ------------------------------------------ 7 5. Electrical Characteristics ------------------------------------------ 8 6. Typical Application Circuit ------------------------------------------ 10 7.1 Startup Operation ------------------------------------------ 11 7.2 Constant Voltage Control Circuit Operation ------------------------------------------ 13 7.3 Bottom-ON Timing (Quasi-resonant Signal) ------------------------------------------ 15 7. Functional Descriptions 7.4 Types of Delay Circuit ------------------------------------------ 7.5 Latch Circuit 7.6 Overvoltage Protection (OVP) 19 ----------------------------------------------------------------------------------- 20 20 7.7 Thermal Shutdown (TSD) ------------------------------------------ 21 7.8 Overcurrent Protection (OCP) ------------------------------------------ 21 8.1 External Components ------------------------------------------ 23 8.2 Control of Switching Speed ------------------------------------------ 23 8.3 Transformer Design ------------------------------------------ 24 8.4 Phase Compensation ------------------------------------------ 26 8.5 Component Layout and Trace Design ------------------------------------------ 26 8. Design Notes Copy Right: SANKEN ELECTRIC CO., LTD. Page.2 STR-L400 Series Application Note Rev. 1.2 !WARNING! ● Sanken reserves the right to make changes without further notice to any products herein in the interest of improvements in the performance, reliability, or manufacturability of its products. Before placing order, Sanken advises its customers to obtain the latest version of the relevant information to verify that th e information being relied upon is current. ● Application and operation examples described in this application note are provided for a supplementary purpose only. Conditions in actual use and variations in additional parts are not considered. When using the products herein, the applicability and suitability of such products for the intended purpose or object shall be reviewed at the user’s responsibility. ● Application and operation examples described in this application note are given for reference only and Sanken assumes no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of Sanken, or any third party which may result from its use. ● Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to society due to device failure or malfunction. ● This publication shall not be reproduced in whole or in part without prior written approval form Sanken. Copy Right: SANKEN ELECTRIC CO., LTD. Page.3 STR-L400 Series Application Note Rev. 1.2 1. General Descriptions The STR-L400 series devices comprise an integrated MOSFET and a controller chip for quasi-resonant switching power supply applications. The quasi resonant operation and PRC operation are available in normal operation. * PRC (Pulse Ratio Control) ---Control system of OFF time fixed and ON time control (Sanken designation) The SIP10L pin full mold package of low-profile and with creeping distance between high and low voltage of 6.5 mm or longer (lead terminal on substrate) (Sanken’s designation: STA package) is used, thus a power supply system with high cost performance, low part count and enhanced protection functions can be easily composed. Copy Right: SANKEN ELECTRIC CO., LTD. Page.4 STR-L400 Series Application Note Rev. 1.2 2. Features and Product Lineup Features and Advantages - SIP10L full mold package (STA10L package, 2.54mm pitch) Creeping distance of 6.5mm of lead terminal on the substrate between high voltage pin and low voltage pin (lead terminal on substrate) Height from substrate: 12mm or lower Most suitable for auxiliary power supply for white goods (home electric appliances) - Current mode control method - Built-in oscillator for low frequency operation (it reduces the stress of components at startup or short circuit of output by operating at low frequency (about 20 kHz) of 50μs OFF time until quasi resonant signal is established) - Quasi resonant operation function - Input compensation function at overcurrent point (compensation of variation of overcurrent operation is available by adding 3 components) - Protection functions Overcurrent Protection (OCP) Pulse-by-pulse Overvoltage Protection (OVP) Latch-off * Thermal Shutdown (TSD) Latch-off * *Latch-off: this is an operation to continue the oscillation stop for protection. - Two-chip structure guarantees avalanche energy (simplified surge absorbing circuit) Product Lineup MOSFET RDS(ON) POUT *1 VDSS(MIN) (Max) AC100V/AC230V STR-L451 650V 3.95Ω 30W / 74W STR-L472 900V 7.70Ω － / 35W Product No. *1: The maximum output power is derived from thermal specifications. The actual output power may be available around 120 - 140% of the above values, respectively, but will be limited by ON duty setting on transformer design or lower output voltage. Copy Right: SANKEN ELECTRIC CO., LTD. Page.5 STR-L400 Series Application Note Rev. 1.2 3. Functional Block Diagram and Terminal Function Block Diagram 8 VIN OVP UVLO ＋ REG － ＋ － Latch Internal Bias Delay TSD ＋ － REG PWM Latch OSC D 1～4 S 6 S Drive R Q INH INH Latch Comp. － ＋ Q S OCP R Comp. Icont OCP 9 /FB － ＋ GND 7,10 Terminal List Table Terminal Symbol Functions 1-4 D MOSFET drain 6 S MOSFET source 7,10 GND Ground 8 VIN Control circuit power supply input 9 OCP/FB No. Overcurrent detection signal input / Constant voltage control signal input Copy Right: SANKEN ELECTRIC CO., LTD. Page.6 STR-L400 Series Application Note Rev. 1.2 4. Package information - SIP10L (Sanken designation: STA10L) - The lead forming shown below is No. LF 428 b a (Between roots) (Between roots) a. Type Number Terminal material: Cu a. 品名標示 STRL4** 端子の材質: Cu b. Lot Number b. ロット番号 Terminal processing:端子の処理: Solder dipNiメッキ＋半田ディップ 1st letter The last digit of year Product weight: around 2.6g 約2.6g 第1文字 西暦年号下一桁 製品重量: nd 第2文字 製造月 2 letter Month 単位: mm Unit: mm 1～9月 アラビア数字 January to September by Arabic number shows the spot 注記where the gate burr with 10月 O October by O 11月 部は高さ0.3maxのゲートバリ発生個所をしめす。 N the height of 0. 3 mm max. is produced. 12月 D November by N 第3、4文字 製造日 December by D 01～31 アラビア数字 3rd & 4th letter Day 01 – 31: Arabic Numerical Copy Right: SANKEN ELECTRIC CO., LTD. Page.7 STR-L400 Series Application Note Rev. 1.2 5. Electrical Characteristics The following tables provide electrical characteristics for the STR-L400 series. The STR-L472 is used as an example. Refer to the specification of the individual devices for details. Absolute Maximum Ratings valid at Ta=25°C unless otherwise specified. Parameter Terminal Symbol Rating Unit Note Single pulse Drain Current *1 1–6 IDPeak 2.7 A Maximum Switching Current *1 1–6 IDMAX 2.7 A V6-10=0.82V Ta= -20 - +125°C Single pulse Avalanche Energy *1 1–6 EAS 50 mJ VDD=30V,L=20mH ILPeak= 2.2A Supply Voltage for Control 8 – 10 VIN 35 V 9 – 10 Vth 6 V Circuit OCP/FB Terminal Voltage Power Dissipation in MOSFET *1 1–6 With infinite 12 PD1 W 2.5 Power Dissipation in Control 8 – 10 Circuit MIC) PD2 0.14 heat sink Without heat sink W Recommended Internal Frame Temperature in ― Operation TF -20 - +125 °C internal frame temperature TF= 105°C (Max) Operating Ambient Temperature ― TOP -20 - +125 °C Storage Temperature ― Tstg -40 - +125 °C Channel Temperature ― Tch +150 °C *1 Refer to individual device datasheet for details; value differs among devices. * Current characteristics are defined based on IC as Sink:+, Source:－. Copy Right: SANKEN ELECTRIC CO., LTD. Page.8 STR-L400 Series Application Note Electrical Characteristics in MOSFET Rev. 1.2 valid at Ta=25°C unless otherwise specified. Rating Parameter Drain-source Voltage Terminal *2 Drain Leakage Current Symbol Unit MIN TYP MAX 1–6 VDSS 900 ― ― V 1–6 IDSS ― ― 300 A Note ON Resistance *2 1–6 RDS(ON) ― ― 7.7 Ω Switching Time *2 1–6 tf ― ― 250 ns Thermal Resistance *2 ― θch-F ― ― 5.05 °C/W Channel to internal frame *2 Refer to individual device datasheet for details; value differs among devices. Control Circuit Electrical Characteristics valid at Ta=25°C, VCC=20V unless otherwise specified. Parameter Terminal Symbol MIN Rating TYP MAX Unit Operation Start Voltage 8 – 10 VIN(ON) 15.8 17.6 19.4 V Operation Stop Voltage 8 – 10 VIN(OFF) 9.1 10.1 11.1 V Circuit Current in Operation 8 – 10 IIN(ON) – – 5 mA Circuit Current in Non-operation 8 – 10 IIN(OFF) – – 50 µA – tOFF(MAX) 41 – 57 µs 9 – 10 tth(2) – – 1.0 µs – tOFF(MIN) – – 1.5 µs OCP/FB Terminal Threshold Voltage 1 9 – 10 Vth(1) 0.70 0.76 0.82 V OCP/FB Terminal Threshold Voltage 2 9 – 10 Vth(2) 1.3 1.5 1.7 V OCP/FB Terminal Drawing Current 9 – 10 IOCP/FB 1.0 1.35 1.5 mA OVP Operation Power Supply Volta ge 8 – 10 VIN(OVP) 23.2 25.5 27.8 V *3 8 – 10 IIN(H) – – 70 µA *3,4 8 – 10 VIN(La.OFF) 7.9 – 10.5 V – Tj(TSD) 135 – – °C Maximum OFF Time Minimum Qua si-resona nt Signa l Input Time Minimum OFF Time Latch Circuit Holding Current Latch Circuit Release Power Supply Voltage Thermal Shutdown Operation Temperature *3 Latch circuit is activated by overvoltage protection (OVP) and thermal shutdown (TSD). *4 VIN(OFF) > VIN(La.OFF) *5 Current characteristics are defined based on IC as Sink:+, Source:－. Copy Right: SANKEN ELECTRIC CO., LTD. Page.9 STR-L400 Series Application Note Rev. 1.2 6. Typical Application Circuit D1 T1 D5 VAC VOUT PC1 C1 R7 C6 R9 P Rs S D2 STR-L400 Z1 1 2 3 4 8 PC1 VIN Z2 R2 R6 D3 D R3 Cont． D4 OCP /FB 9 S 6 GND GND 10 7 R4 R OCP C5 C3 Fig.6 Typical application circuit Copy Right: SANKEN ELECTRIC CO., LTD. C7 R11 R10 GND C2 D CV R8 Page.10 STR-L400 Series Application Note Rev. 1.2 7. Functional Descriptions 7.1 Startup Operation Fig.7-1 shows VIN terminal peripheral circuit. C1 P The startup circuit detects VIN terminal voltage to effect the start/stop Rs operation of the IC. At startup of the power supply, C2 is charged via a startup resistor RS and when VCC terminal voltage rises up to operation start power supply voltage VIN (ON) = 17.6V (TYP), the IC starts operation. 1～4 D/ST VIN The RS value is set so that the current of 100μA or higher flows in consideration of margin of the latch circuit holding current IIN (H) = 70μA D2 8 C2 GND R2 VD D 7,10 (MAX). If the RS value is too large, the charging time of C2 is prolonged after AC input and as a result, the startup time will be long. Therefore, it is STR-L400 Fig. 7-1 VIN7-1 terminal peripheral circuit Fig. VIN 端子周辺回路 also required to check the C2 capacitance. When the power supply specifications are standard ones, C2 is estimated to be 10 – 47μF , Rs to be 100 – 220kΩ at AC100V input and universal input, and to be 470 – 820kΩ at AC230V input. Fig.7-2 shows the relation of VIN terminal voltage and circuit current IIN. When VIN terminal voltage reaches VIN (ON) = 17.6V(TYP), the control circuit starts operation and the circuit current increases. After the control circuit operation, when VIN terminal voltage drops below the shutdown voltage VIN(OFF) = 10.1V(TYP), the control circuit stops operation by undervoltage lock out (UVLO) circuit and reverts to the state before startup. After the control circuit operation, the voltage that is rectified from auxiliary winding D in Fig.7-1 becomes the power source to VIN terminal. The auxiliary winding voltage needs to be adjusted to approximately 18V, taking into account the turn’s ratio of auxiliary winding D, so that VIN terminal voltage becomes: VIN ( OFF ) = 11.1V ( MAX ) < VIN < VIN ( OVP ) = 23.2V ( MIN ) within the limits for input and output deviation. IIN VIN IIN(ON)= 5mA (MAX) VIN(ON)= 17.6V (TYP) Sto Startu IC operation start point Proper startup VIN(OFF)=10.1V (TYP) Improper startup IIN(OFF)= 50μA (MAX) 10.1V (TYP) VIN(OFF) 14V 17.6V (TYP) VIN(ON) VIN Time Fig.7-3 VIN terminal voltage waveform at startup Fig.7-2 VIN Terminal Voltage - Circuit Current IIN An example of the waveform of VIN terminal voltage is shown in Fig. 7-3. Copy Right: SANKEN ELECTRIC CO., LTD. Page.11 STR-L400 Series Application Note Rev. 1.2 When the VIN terminal voltage reaches VIN (OFF) to result in startup failure as shown in Fig.7-3, the capacitance of C2 should be increased. As the capacitance is increased, the startup time is prolonged. Therefore, it should be checked whether the long startup time does not give any trouble to the operation or not. In actual power supply circuits, there are cases in which VIN voltage fluctuates in proportion to the secondary output current IOUT, (see Fig.7-4) to effect overvoltage protection (OVP). This happens because C2 is charged to a peak by the transient surge voltage that is generated at the moment power MOSFET turns off. To prevent this, it is effective to add some value R2, of several ohms to several tenths of an ohm, in series with rectification diode D2 (see Fig.7-5). The optimal value of R2 shall be determined using a transformer matching the application, because the proportion of VIN voltage versus the transformer output voltage differs according to transformer structural design. The proportion of change between VIN voltage versus the transformer output voltage becomes worse if: - The coupling between the primary winding and the secondary winding of transformer get worse(low output voltage, large current load specifications etc.). - The coupling between the auxiliary winding D and the stabilizing output winding (a winding of the circuit that controls a constant voltage) gets worse. VIN Without R2 D2 R2 8 VIN STR-L400 D C2 Added GND With R2 7,10 IOUT Fig. 7-5 VIN terminal peripheral circuit that is insusceptible to output current IOUT Fig. 7-4 Output current IOUT by R2 - VIN Terminal Voltage For transformer design, Fig.7-6 and 7-7 show reference examples of the position of auxiliary winding D. - Separate the auxiliary winding D from the primary winding P1 and P2 with wider distance (Fig. 7-6 winding structure example 1). The primary winding is divided into two as P1 and P2 (sandwiched windings) - Sandwich the auxiliary winding D with the secondary stabilizing output winding S1 (Fig. 7-7 winding structure example 2). Only S1 is a stabilized output winding (output line winding controlled to constant current) out of two output winding S1 and S2. Copy Right: SANKEN ELECTRIC CO., LTD. Page.12 STR-L400 Series Application Note Core Bobbin Rev. 1.2 Core Bobbin Barrier tape Barrier tape P1 S1 P2 S2 D P1 S1 D S2 S1 P2 Barrier tape Barrier tape Pin side P1, P2: Pin side Primary winding P1, P2: S1: Secondary control winding S1: Secondary control winding S2: Secondary output winding S2: Secondary output winding D: Auxiliary winding for VCC D: Auxiliary winding for VCC Fig. 7-6 Winding Structure 1 7.2 Primary winding Fig. 7-7 Winding Structure 2 Constant Voltage Control Circuit Operation The output voltage is controlled to constant voltage by the current mode control (peak current mode control) that has superior transient responsibility and stability. Fig. 7-8 shows a FB/OLP terminal peripheral circuit and Fig. 7-9 shows a constant voltage control. The feedback current according to a load generates the voltage drop VR4 in R4 through a photo coupler PC1. The constant voltage control is done in the current control mode where OCP/FB terminal voltage which superimposes VR4 on voltage fall VROCP generated at a detection resistor by drain current, is compared with OCP/FB terminal threshold voltage 1Vth (1) = 0.76V (TYP) by an OCP comparator (OCP Comp) in the IC. In the current mode control, the voltage of VR4 rises at light load and the OCP comparator (OCP Comp) malfunctions due to the steep surge current generated at turn-on of the power MOSFET, resulting in turning - off of the power MOSFET. In order to prevent this malfunction, the STR-L400 series incorporates an active low pass filter circuit. Until the power MOSFET turns on, the OCP /FB terminal is drawn at the constant current of OCP/FB terminal drawing current IOCP/FB = 1.35 mA to decrease the bias amount by half. The surge voltage generated at turn-on of the power MOSFET is absorbed by C5 by using this circuit to assure stable operation up to light load. Typical constants of R4, R6 and C5 are estimated to be R4 =680Ω, R6 = 3.3kΩ and C5 = 100p – 470 pF respectively. When C5 capacitance is too large, the response of OCP is delayed, therefore it should be noted that the drain current peak may be increased at the transient state such as power supply startup. When malfunction occurs, the constants should be checked in reference to the actual operation. The operation mode of STR-L400 series is switched to either one of the following two modes according to the state whether quasi resonant signal is present or not. - PRC (Pulse Ratio Control) operation - Quasi resonant operation Copy Right: SANKEN ELECTRIC CO., LTD. Page.13 STR-L400 Series Application Note Rev. 1.2 D2 R2 PC1 D3 C2 D R3 STR-L400 S GND 7 10 6 R OCP R6 D4 OCP /FB 9 R4 VR OCP C5 C3 Fig. peripheral circuit 図 7-8 OCP/FB OCP/FBterminal 端子周辺回路 From latch output Latch出力より Timer reset ﾀｲﾏｰﾘｾｯﾄ OFF signalOFF信号出力 output OFFﾀｲﾏｰ回路 OFF timer circuit PWM Latch D 1～4 PC1 R6 DRIVE D4 S R Q INH Comp. R 6 R4 9 － ＋ INH Latch Q S S OCP /FB Flyback voltage of 補助巻線の ﾌﾗｲﾊﾞｯｸ電圧winding Auxiliary OCP Comp. C5 R OCP Vth(1) 0.76V(TYP) VROCP － ＋ VR4 GND 7,10 OnON幅ｺﾝﾄﾛｰﾙ width control 図 7-9 定電圧制御動作 Fig. 7-9 Constant voltage control operation 7.2.1 PRC Operation If there exists no quasi resonant signal or it is not yet established (OCP/FB terminal voltage 2Vth (2) = 1.5V (TYP) or lower), operation is performed by the maximum OFF time tOFF (MAX) = 50μs (TYP) fixed, ON time control. In the case that the power MOSFET turns on, after the OFF time internally fixed by the OFF timer circuit in Fig. 7-9, the Q of Latch is latched to L and the power MOSFET turns on when the gate drive conditions are met. In the case that the power MOSFET turns off, the OCP/FB terminal voltage exceeds the OCP/FB threshold voltage 1Vth (1) = 0.76V (TYP) by the OCP comparator (OCP Comp) and the Q of Latch is latched to H to turn off the drive circuit and turn off the power MOSFET. Since OFF time is 50μs (TYP) fixed, the switching frequency at PRC operation is about 20kHz to decrease the stress of components at startup or output short circuit, when quasi resonant signal is not yet established. The power consumption at such minimal load as standby load can be decreased by adding a circuit which cuts the quasi resonant signal by external signals. 7.2.2 Quasi Resonant Operation When OCP/FB terminal voltage exceeds Vth(2) = 1.5V (TYP) due to the quasi resonant signal generated by the Copy Right: SANKEN ELECTRIC CO., LTD. Page.14 STR-L400 Series Application Note Rev. 1.2 auxiliary winding, the OFF timer circuit in the IC is switched to the minimum OFF time tOFF (MIN) = 1.5μs (MAX) and the power MOSFET continues to be off until the OCP/FB terminal voltage becomes Vth (1) = 0.76V (TYP) or lower. The quasi resonant operation is performed by this operation. Refer to 7.3 Bottom timing (quasi resonant signal) for quasi resonant operation. 7.3 Bottom-ON Timing (Quasi-resonant Signal) As shown in Fig. 7-10, the flyback system (which provides energy to the secondary side, when the power MOSFET is OFF) performs free vibration at a frequency where the drain voltage VDS is determined by the capacitor Cv between the transformer LP and the drain source after releasing energy to the secondary side. Ef EIN: DC voltage LP NP NS Ef VO Ef: Flyback voltage IＤ IOFF CO Np Vo VF Ns NP: Primary winding NS: Secondary winding EIN VO: Output voltage VF: Forward voltage drop of diode CV Fig. 7-10 Flyback system ID: Drain current of power MOSFET IOFF: Current flowing across secondary diode when power MOSFET is OFF. CV: Voltage resonant capacitor LP: Excitation inductance Turning- ON of the power MOSFET at the bottom point of free vibration of VDS is called bottom-ON and Fig. 7-11 shows the VDS waveform at ideal bottom-ON. In the quasi resonant operation, turning-ON is performed at VDS bottom point to reduce switching loss and switching noise, resulting in the realization of high efficiency and low noise. The delay timing which turns the power MOSFET on during the period of free vibration of VDS is made from the auxiliary winding voltage synchronized with VDS waveform. Copy Right: SANKEN ELECTRIC CO., LTD. Page.15 STR-L400 Series Application Note Rev. 1.2 Half cycle of vibration tONDLY t ONDLY ≒ Lp CV EIN VDS D1 Ef GND C1 Bottom point P IOFF Rs GND D2 1～4 D ID tON 3.2 - 3.6V GND OCP/FB 端子 OCP/FB terminal 絶対最大定格 Absolute maximum rating PC1 VIN C2 R6 CV R2 D3 D R3 STR-L400 D4 OCP /FB 9 Recommended 推奨電圧voltage OCP/FB OCP/FB terminal 端子電圧 voltage 8 S Vth(2) Vth(1) 6 GND 7,10 R4 C5 C3 R OCP GND Fig. 7-11 Ideal bottom-on: the turn-on timing is at the Fig. 7-12 図 Quasi-resonance 7-12 擬似共振と遅延回路 and delay circuit bottom point of VDS waveform D3, D4, R3 and C3 between the auxiliary winding D and OCP/FB terminal shown in Fig. 7-12 compose the delay circuit. After turn-off of the power MOSFET, when OCP/FB terminal voltage is increased to OCP/FB threshold voltage 2 Vth (2) = 1.5V (TYP) or higher by the auxiliary winding voltage, the INH comparator in the IC is operated to continue the OFF state of power MOSFET until it falls to the OCP/FB terminal threshold voltage 1 Vth (1) = 0.76V (TYP). When the energy of the transformer has been discharged, the auxiliary winding voltage begins to fall. C3 and C5 voltages are discharged by the synthesized impedance of the active low pass filter circuit and R4 in the IC and when the OCP/FB terminal voltage falls below Vth (1), the power MOSFET turns on. The discharging period is equivalent to the delay time. C3 is adjusted by observing the operation waveform in a manner that the delay time becomes bottom-ON. The malfunction of quasi resonant operation is prevented by the voltage difference between Vth (1) and Vth (2) and the active low pass filter circuit. Quasi resonant signal voltage of OCP/FB terminal: - In the case that it is too low: The startup failure occurs if the switching from PRC operation to quasi resonant operation is delayed, the rise of the output voltage is delayed and the VIN terminal voltage falls to the operating power supply stop voltage. - In the case that it is too high: The power MOSFET may turn ON/OFF at high frequency due to malfunction at startup of power supply. If the Copy Right: SANKEN ELECTRIC CO., LTD. Page.16 STR-L400 Series Application Note Rev. 1.2 channel temperature exceeds the maximum rating, the MOSFET is damaged. - In the case that it includes large ringing waveforms: Fig. 7-13 shows the BD terminal waveform using a transformer with poor coupling. Vth(2)= 1.5V(TYP) Vth(1)= 0.76V(TYP) 0V Fig.7-13 BD terminal waveform using a poor coupling transformer If the turn ratio of primary winding and secondary control winding (NP/NS) is extremely large (in the low voltage and high current load specifications), a surge voltage may be generated on BD terminal voltage thought auxiliary winding in MOSFET turning off, and the power MOSFET may be switched with high frequency by the detection of ringing voltage as a quasi-resonant signal. When high frequency operation occurs, such adjustments as connection of R4, R5 close to of OCP/FB terminal GND terminal, separation of OCP/FB terminal - GND pattern loop from high current pattern, use of winding method for lessening coupling force of primary and secondary windings or adjustment of constants of clamp snubber should be made to avoid high frequency operation. In addition, the probe which confirms the operation waveform of the OCP/FB terminal should be connected close to OCP/FB terminal and GND terminal. The quasi resonant signal of OCP/FB terminal is adjusted as follows: - Selection of delay circuit It is selected from 7.4 Types of delay circuit” according to power supply specifications. The following adjustments will be explained with a circuit example B (basic circuit with the most wide application range) of 7.4 Types of delay circuits. - Amplitude of quasi resonant signal and effective period Recommended waveforms are shown in Fig. 7-14. The current IS flowing across R3 at quasi resonant operation is as shown in the following formula (1) since the constant current 1.35mA of R4 and active low pass filter circuit is connected if the recommended value is 3.4V. ROCP is not considered in the calculation formula since it is much smaller than R4 and negligible. 3.4V + 1.35m A R4 VD－3.4V－2 × VF R3 = IS Is = (1) In this formula, VD is auxiliary winding voltage and VF is forward voltage drop of D3 and D4 ≈ 0. 7V. R3 should be determined in consideration of the following for the adjustment of quasi resonant signal. Copy Right: SANKEN ELECTRIC CO., LTD. Page.17 STR-L400 Series Application Note Rev. 1.2 Amplitude should be adjusted to be 3.2 - 3. 6V at AC input voltage MIN, Po = MAX. OCP/FB terminal voltage requires the setting of the absolute maximum rating of 6V or lower. The effective period requires time of 1μs or longer so as to assure Vth (2) = 1.7V at the AC input voltage MIN, Po = MIN. If the period is short, the quasi resonant operation may be unable to follow up in the case of the power supply specifications of higher switching frequency. When the effective period cannot be adjusted, it is required to review the circuit type D in 7.4 Types of delay circuits or to consider the increase of inductance of transformers for lowering the switching frequency. It should be confirmed that there is no malfunction due to noise and that operation is performed with the OFF time of about 50μs during the PRC operation period at power supply startup (The OFF time gets shorter if the noise enters the OCP/FB terminal). Recommended Amplitude tOFF1≒50μs 3.2V - 3.6V tOFF2≒50μs 1μs or longer Vth(2)=1.7V(MAX) Vth(1)=0.76V(TYP) Fig. 7-15 Drain current waveform in power supply startup Fig. 7-14 OCP/FB terminal voltage waveform In order to adjust the bottom point of VDS, actual waveforms of VDS, VOCP/FB (OCP/FB terminal voltage waveform) and ID Ideal bottom-on should be observed to adjust the delay time tONDLY in a manner that the ideal bottom-ON in Fig. 7-16 (turning ON at bottom of VDS) is achieved. When turn-ON is earlier than the bottom point (Fig. 7-17) on the ﾀｰン ON がﾎﾞﾄﾑ点に Adjustment in the case of 合わない場合の調整 non-conformity of turn-on condition that AC input voltage and Po are maximum, the with the bottom point capacitance of C3 initially connected should be increased and after confirming the bottom point, it should be adjusted so that the turn-ON is made in conformity with the bottom point of VDS. Fig. 7-16 Bottom-ON setting When turn-ON is later than the bottom point (Fig. 7-18) on the condition that AC input voltage and Po are maximum, the capacitance of C3 initially connected should be decreased and after confirming the bottom point, it should be adjusted so that the turn-ON is made in conformity with the bottom point of VDS. Copy Right: SANKEN ELECTRIC CO., LTD. Page.18 STR-L400 Series Application Note Rev. 1.2 Natural frequency fR fR Earlier turn on Later turn on than bottom point than bottom point 1 2 Lp CV VDS Bottom point Bottom point IOFF ID tON tON VOCP/FB Vth(2) Vth(1) Auxiliary winding Voltage GND Fig. 7-17 Example of earlier turn on Fig. 7-18 Example of later turn on than bottom point of VDS than bottom point of VDS In the case that turn-on is not in conformity with the bottom point of VDS at adjustment, it should be set prior to the bottom point as stipulated in Fig. 7-16 (Adjustment in the case of non-conformity of turn-on with the bottom point). When it is set after the bottom point, oscillation may be unstable. 7.4 Types of Delay Circuit The delay circuit structure is shown in Fig. 7-19. - Type A circuit: This is a circuit with few components and the highest attenuation effect of surge voltage. However, since the loss of R3 becomes large, the capacitance of C3 cannot be increased. Therefore, this circuit is not suitable for a power supply with high natural frequency or a narrow input power supply. - Type B circuit Longer time can be set compared to type A. This type is the most widely applicable and typical circuit with the high attenuation effect of surge voltage. - Type C circuit As the electric charges of C3 are discharged by R3’, change in delay time due to feedback current is small in this circuit. This type of circuit is suitable in the case of sudden change of load or for the universal input power supply requiring the wide adjustment range of delay time. It is necessary to compensate the value of R3 since the current Copy Right: SANKEN ELECTRIC CO., LTD. Page.19 STR-L400 Series Application Note Rev. 1.2 flowing across R3 by R3’ is bypassed. - Type D circuit This type of circuit has the lowest part count and can follow up to the switching frequency of about 300kHz. However, the delay time cannot be adjusted. This type of circuit is suitable in the case that 1/2 of natural frequency conforms to the delay time ( π LP × CV ≈ 1.5μs or so), or slight increase of switching loss does not create any problem although the turn-on timing of the power MOSFET is not in conformity. This circuit is also appropriate for AC100V series power supply with small output power or a universal input power supply with high natural frequency and small output power. Auxiliary winding 補助巻線 Auxiliary winding 補助巻線 Auxiliary winding 補助巻線 D3 補助巻線 Auxiliary winding D3 D3 D4 R3 OCP/FB R3 D4 OCP/FB OCP/FB C3 C3 Type回路例A A circuit R3 D4 Type B circuit 回路例B R3 OCP/FB C3 R3' Type回路例C C circuit Type D circuit 回路例D Fig. 7-19 Types of delay circuit 7.5 Latch Cirtcuit The latch circuit stops switching operation (latch off) in each Vcc operation of overcurrent protection (OVP) and thermal shutdown (TSD) circuit. When the latch circuit is operated and the switching operation is stopped, the VIN terminal voltage begins to fall and when the VIN terminal voltage falls to VIN (OFF) =10.1V (TYP), the circuit 17.6V (TYP) 10.1V (TYP) Low回路電流小 circuit current current becomes 50μA or less and the VIN terminal voltage 回路電流大 High circuit current commences to rise. Then, when it reaches the operation start power supply voltage VIN (ON) =17.6V (TYP), the circuit current is increased and the VIN terminal voltages falls. VIN terminal voltage waveform at latch circuit operation rises and 時間 Time Fig. 7-20 VIN terminal voltage waveform in latch falls between 10.1V (TYP) and 17.6V (TYP) as shown in Fig. 7-20 to prevent the abnormal rise of the VIN terminal voltage. Though the latch circuit holding current IIN (H) is 70μA (MAX) at VIN = 9.8V (TYP), a startup resistor RS which can flow 100μA or higher should be set with margin considered. The latch circuit is released by shutting-down the AC input and reducing VIN terminal voltage to VIN(La.OFF)= 7.9V(MIN) or lower. 7.6 Overvoltage Protection (OVP) When the voltage of OVP operation power voltage VIN(OVP)= 25.5V(TYP) or higher is applied between VIN Copy Right: SANKEN ELECTRIC CO., LTD. Page.20 STR-L400 Series Application Note Rev. 1.2 terminal and GND terminal, the overvoltage protection function operates and the switching operation stops in latch mode. If VIN terminal voltage is supplied from the auxiliary winding of transformer, the secondary overvoltage can be detected, in output voltage detection circuit open or others, because VIN terminal voltage is proportional to output voltage. In this case, the secondary output voltage in the operation of overvoltage protection is calculated according to the following formula (2). OUT ( OVP ) V 7.7 Output voltage in normal operation 通常動作時出力ooooooo 電圧 25.5V(TYP) VIN通常動作時 terminal voltageV inINnormal operation 端子電圧 --- (2) Thermal Shutdown (TSD) The switching operation is stopped in latch mode when the temperature of IC control circuit reaches the thermal protection operation temperature Tj(STD)=135°C (MIN) or higher. 7.8 Overcurrent Protection (OCP) The overcurrent protection circuit (OCP) detects the peak limits the power. The power MOSFET drain current is detected by the current detection resistor ROCP between OCP/FB terminal and GND terminal, and the power MOSFET turns off when the voltage drop of ROCP reaches the OCP/FB terminal threshold voltage 1Vth(1)= 0.76V(TYP). (V)(V) VoutVOUT Output voltage 出力電圧 power MOSFET drain current by pulse-by-pulse method and Difference in overcurrent point by AC 入力補正によりAC入力電圧による input voltage is reduced by input 過電流点の差が低減される compensation AC入力電圧 AC input が高い場合 voltage is AC input AC入力電圧 high voltage is が低い場合 low Output current IIout (V) OUT (V) 出力電流 Fig. 7-21図 Output 7-21 over 出力過負荷特性 load characteristics When the output voltage falls in the overload state, the auxiliary winding voltage also falls proportionally. When VIN terminal voltage falls below the operation stop voltage VIN (OFF), the switching operation is stopped and the circuit current is decreased and as a result, VIN terminal voltage commences to rise. When it reaches the operation start power supply voltage VIN (ON) = 17.6V (TYP), the control circuit is again operated to perform intermittent operation by UVLO. Since the coupling of transformer of multi output windings is poor, the auxiliary winding voltage may not fall and intermittent operation may not be performed even if the output voltage falls in the overload state. In this case, it is required to review the construction of the transformer for enhancing the coupling between the secondary side winding and the auxiliary winding. 7.8.1 Overcurrent Input Compensation For the compensation of overcurrent by AC input voltage, the overcurrent in high input voltage is operated at earlier timing by RA, RB and DZ in Fig. 7-22 and the difference from the low input voltage can be reduced as shown in Fig. 7-21. Copy Right: SANKEN ELECTRIC CO., LTD. Page.21 STR-L400 Series Application Note Rev. 1.2 For the compensation of overcurrent input, the surge voltage generated from the transformer is reduced to suppress the drain current peak of power MOSFET to a low level and the stress of the secondary side rectifier diode and the power MOSFET at startup of power supply and overload can be decreased. EIN(MAX － ) EIN(MIN ) IDP(MAX) R A = 680Ω × × 0.76V IDP(MAX － ) IDP(MIN ) RB = ( 6.8V + 0.76V ) EIN(MIN )－(6.8V + 0.76V) IDP(MAX) : VIN (AC) (MIN), Po = drain current at MAX IDP(MIN) :VIN(AC)(MAX), Po=drain current at MAX Added RA RA 追加 Vin(AC) EIN(MIN) :C1 voltage at VIN (AC) (MIN) C1 EIN(MAX):C1 voltage at VIN (AC) (MAX) P EIN D Added DZ Dz追加 Vz =Vz=6.8V 6.8V 8 V IN D 1～4 STR-L400 6 S OCP/FB 9 680 R4 C5 GND ROCP RB 追加 Added RB 7,10 Fig. 7-22 Overcurrent input compensation circuit Copy Right: SANKEN ELECTRIC CO., LTD. Page.22 STR-L400 Series Application Note Rev. 1.2 8. Design Notes 8.1 External Components Take care to use properly rated, including derating as necessary and proper type of components. - Input and output electrolytic capacitors. Apply proper derating against ripple current, voltage, and temperature rise. Use of high ripple current and low impedance types, designed for switch mode power supplies, is recommended. - Transformer. Apply proper derating against core temperature rise from core loss and copper loss. - A high frequency switching current flows to Current sensing resistor R1 (ROCP), and may cause poor operation if a high inductance resistor is used. Choose a low inductance and surge-proof type. 8.2 Control of Switching Speed As the source terminal (pin 6) of STR-L400 series is independent, it is possible to reduce the switching noise by inserting a ferrite bead FB into this pin and adjusting the switching speed. When the ferrite bead FB is inserted, the switching speed is dropped not only at the turn-on of the power MOSFET, but also at the turn-off thereof, possibly resulting in the increase of switching loss. Therefore, the drop in switching speed at turn-off can be prevented by inserting the diode D6 shown in Fig. 8-1. For a diode to be inserted, either a small-signal switching diode with small junction capacitance at high speed or a Schottky barrier diode (Sanken’s AK03 etc.) should be used. STR-L400 OCP GND S /FB 6 7,10 9 FB Added D6 R OCP R4 V6−10 C5 Fig. 8-1 Circuit example of insertion between source terminal and GND terminal Fig. 8-2 Voltage curve between pin 6 and pin 10. When the ferrite bead FB for speed control is inserted, the voltage fall will occur for this insertion. The voltage fall between the source terminal (pin 6) and the ground terminal (pin 10) is increased and the VGS voltage between gate and source of the power MOSFET falls and the drive voltage also falls. Since the maximum switching current* of power MOSFET is reduced, the voltage between the source terminal and the ground terminal should be measured and the maximum switching current should be derated from the maximum switching current derating curve described in the product specifications. It should be confirmed that the voltage fall between the source terminal (pin 6) and the ground terminal (pin 10) and the maximum switching current are within the maximum switching current derating curve in normal operation and overcurrent protection operation. * The maximum switching current: Copy Right: SANKEN ELECTRIC CO., LTD. Page.23 STR-L400 Series Application Note Rev. 1.2 This is drain current is determined by the drive voltage in the IC and Tth of power MOSFET. When the voltage fall between the source terminal (pin 6) and the ground terminal (pin 10) occurs due to pattern drawing etc., the maximum switching current is decreased by the V6 – 10 in Fig. 8-2. Therefore, it should be used within the maximum switching current derating curve described in the product specifications. 8.3 Transformer Design D1 VAC The designing of transformers is basically the same T1 Lp Rs (Ringing Choke Converter: self-exciting type D2 flyback converter). Z1 1～4 D However, as the duty is varied to the extent that the PC1 8 VIN P S Np Ns C6 R9 D3 D D4 OCP /FB S When the ON Duty obtained by the ratio of the primary winding NP and the secondary winding Ns 9 GND 6 7,10 R4 R OCP C5 C3 is expressed as DON, Lp is obtained from the Fig. 8-3 Circuit example following formula (3). LP Ein( MIN ) DON 2 2 PO f O Ein ( MIN ) π f D Cv O ON η 1 (3) 2 LP is calculated under the following conditions: Po: Maximum output power fo: Minimum oscillating frequency η1: Conversion efficiency of transformer DON: ON Duty at Vin (AC) MIN⇒ DON = Ef Ein( MIN ) + Ef Ein (MIN): Voltage between C1’s at Vin (AC) MIN Ef: Flyback voltage ⇒ Ef Np Vout VF Ns VF: Forward voltage drop of D5 Each parameter such as drain current peak I IDP is calculated from the following formula. t ONDLY π LP Cv Don' 1 f O t ONDLY Don P 1 Iin O η2 Ein(MIN) 2 Iin I DP Don' Copy Right: SANKEN ELECTRIC CO., LTD. Page.24 R8 Z2 R2 R3 STR-L400 the compensation of the duty is required. R7 C7 R11 R10 GND C2 R6 CV VOUT PC1 as the power supply transformers of RCC method turn-on is delayed by the quasi resonant operation, D5 C1 (4) (5) (6) (7) STR-L400 Series Application Note Rev. 1.2 LP AL Value Np Vout VF Ns Ef Np (8) (9) tONDLY: Delay time Iin: Average input current η2: Conversion efficiency of power supply IDP: Switching current peak Don´: ON Duty after compensation With respect to the AL-Value of transformer ferrite core, the AL-Value which never causes magnetic saturation should be selected in consideration of NI-Limit (AT) value that is calculated from NP and IDP. The calculated NI-Limit value (= IDP x Np) is required to be always within the area of the NI-Limit vs. AL-Value characteristic curve (shaded area) in the Fig.8-3. When the ferrite core which meets the relation of the NI-limit vs. AL-Value is selected, it is recommended to set the calculated NI-Limit value in a manner that it is around 30% lower than the NI-Limit in the core data in consideration of design margin to the variation of temperature etc. NI-Limit(AT) Magnetic saturation point Magnetic saturation margin = around 30% Example of NI-Limit selection point AL-Value(nH/T2) Fig. 8-3 NI-Limit vs. AL-Value Characteristics of Core Therefore, the NI-Limit is set to the value in consideration of saturation margin from the following formula. NI Np I DP (130%) (10) The minimum oscillation frequency fo is calculated from the ON Duty after compensation by the following formula. 2 2 PO 2 PO 4 π Ein(MIN) Don Cv η1 η1 Lp fO 2 Ein(MIN) π Don Cv 2 (11) Points to be considered in designing the transformer winding The high-frequency element is included in switching current, and the skin effect may affect. Therefore, the winding wire diameter used for transformer shall be selected so that the current density is in the range of 3 to 4A/mm2, considering the root mean square value of operating current. When the additional measures against temperature are needed due to the skin effect or others, the following should be examined in order to increase the winding wire surface area. Copy Right: SANKEN ELECTRIC CO., LTD. Page.25 STR-L400 Series Application Note - Increase the number of winding wire - Use the litz wire - Enlarge the wire diameter 8.4 Rev. 1.2 Phase Compensation Fig.8-4 shows the circuit diagram for the secondary error amplifier, using a general shunt regulator. As for the phase compensation capacitor, C7, the capacitance shall be adjusted in the range of 0.047 - 0.47μF, and finally determined on actual operations. In normal operation, no additional component is required for phase compensation. However, only the compensation of the secondary side may not be sufficient when the output load specification is a dynamic load with large amplitude or the ripple current of secondary side smoothing capacitor is large. When the compensation of the secondary side is not sufficient, C8 and D6 should be added as shown in Fig. 8-5 to assure the stability. C8 is estimated to 0.01μF - 0.1μF and when the C8 is added, D6 which prevents the current from flowing in the reverse direction should be added. added in case of unstable operation D2 1～4 D 8 VIN PC1 C8 C2 V OUT D5 R7 C6 R8 S CV PC1 D6 STR-L400 D D4 OCP /FB R11 S R10 9 GND 6 Z2 D3 R3 R6 R9 C7 R2 R OCP 7,10 R4 C5 C3 GND Fig.8-4 Peripheral circuit around shunt regulator (Z2) 8.5 Fig.8-5 OCP/FB terminal peripheral circuit Component Layout and Trace Design PCB circuit trace design and component layout affect proper functioning during malfunctions, EMI noise, and power dissipation. Therefore, where high frequency current traces form a loop, as in Fig.8-6, the design with the wide, short patterns, small circuit loops and the low line impedance is required. In addition, local GND and earth ground traces affect radiated EMI noise, thus the same measures should be taken into account. Copy Right: SANKEN ELECTRIC CO., LTD. Page.26 Fig.8-6 High frequency current loops (hatched areas) STR-L400 Series Application Note Rev. 1.2 Switching mode power supplies consist of current traces of high frequency and high voltage, thus trace design and component layouts should be done to comply with all safety guidelines. Furthermore, in the case where a power MOSFET is being used as the switching device, take into account the positive thermal coefficient of RDS(on) when preparing a thermal design. Fig. 8-7 shows the example of peripheral circuit connection. (1) Around source terminal (S) (S terminal - ROCP - C1 - T1(P winding) - D terminal) This is the main circuit containing the switching current, and thus it should be as wide and as short as possible. In case the distance between C1 and the device is lengthy, an isolation capacitor near the device or the transformer is recommended. The capacitors may be either electrolytic or film type capacitors, 0.1μF, in the range considered maximum input voltage. (2) Around GND terminal (GND terminal - C2(- side) - T1(D winding wire) - R2 – D2 - C2(+ side) - VIN terminal) This circuit also needs to be as wide and short as possible. In case the distance between C2 and the device is not short, placing a 0.1 – 1.0μF / 50V film capacitor between VIN and GND terminals is recommended. (3) Current Detection Resistance around ROCP Place ROCP close to source (S) terminal. In order to avoid the influence of common impedance or switching current on the control circuit, the main circuitry and control system ground should be connected near ROCP and from ROCP to the GND terminal by using the dedicated pattern (Position A in Fig. 8-7). The typical connection of secondary side rectification is shown in Fig. 8-7. (1) Secondary side rectifier smoothing circuit (T1 (S winding) – D3 – C7): This pattern trace should be as thick and short as possible. If the rectification pattern is thin and long, the element of the parasitic leakage inductance is increased and the surge voltage at turn-off of MOSFET is increased. The pattern design that the secondary side rectification pattern is taken into consideration achieves the wider withstand margin of power MOSFET and the reduction of stress and dissipation of the clamp snubber circuit. Copy Right: SANKEN ELECTRIC CO., LTD. Page.27 STR-L400 Series Application Note Rev. 1.2 Clamp snubber T1 D5 P C1 STR-L400 D2 PC1 Z1 1 2 3 4 D 8 VIN C2 S R2 D3 C6 D R3 R6 CV Cont. O.C.P D4 /F.B Main circuit pattern Control system GND pattern Secondary rectification pattern 9 S 6 ROCP C3 GND GND 7 10 R4 C5 A C11 Fig. 8-7 Example of IC peripheral circuit connection Copy Right: SANKEN ELECTRIC CO., LTD. Page.28