Data Sheet

PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
Rev. 02 — 11 May 2010
Product data sheet
1. General description
The PCA24S08 provides 8192 bits of serial Electrically Erasable and Programmable
Read-Only Memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are
received and transmitted via the serial I2C-bus.
Access permissions limiting reads or writes are set via the I2C-bus to isolate blocks of
memory from improper access.
The PCA24S08 is intended to be pin compatible with standard 24C08 serial EEPROM
devices except for pins 1, 2, and 3, which are address pins in the standard part. Other
exceptions to the PCA24S08 serial EEPROM data sheet are noted in Section 6.6.
All bits are sent to or read from the device, most significant bit first, in a manner consistent
with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed
with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 kbit (128 bytes) each. Within each
block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In
addition to these 8 kbits, there are two more 128-bit pages that are used to store the
access protection and ID information. There are a total of 8448 bits of EEPROM memory
available in the PCA24S08.
Access protection (both read and write) is organized on a block basis for block 1 through
block 7 and on a page and a block basis for block 0. Protection information for these
blocks and pages is stored in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array. See Section 6.4 for more details.
The ID value is located in the ID page of the EEPROM, the second of the additional
16 byte pages.
Writes from the serial interface may include from one byte to 16 bytes at a time,
depending on the protocol followed by the bus master. All page accesses must be
properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year
data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ‘1’.
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
2. Features and benefits
„ Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes each
„ I2C-bus interface logic
„ Compatible with 24C08 serial EEPROM, and alternate source of Atmel AT24RF08C
without the RF interface
„ Write operation:
‹ Byte write mode
‹ 16-byte page write mode
„ Read operation:
‹ Sequential read
‹ Random read
„ Programmable access protection to limit reads and writes
„ Lock/unlock function
„ Write protect feature protecting the full memory array against write operations
„ Self timed write cycle
„ Internal power-on reset
„ High reliability:
‹ Ten years non-volatile data retention time
‹ 100,000 write cycle endurance
„ Low power CMOS technology
„ Operating power supply voltage range of 2.5 V to 3.6 V
„ 0 Hz to 400 kHz clock frequency
„ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
„ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
„ Packages offered: SO8, TSSOP8
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C
Type number
Topside
mark
Package
Name
Description
Version
PCA24S08D
P24S08
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
PCA24S08DP
PS08
TSSOP8
plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
2 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
4. Block diagram
PCA24S08
SDA
INPUT
FILTER
SCL
WP
I2C-BUS CONTROL LOGIC
PROT
EEPROM
8 PAGES
(8 × 128 BYTES EACH)
BYTE
COUNTER
SEQUENCER
DIVIDER
(÷ 128)
ACCESS
PROTECTION
BYTE LATCH
(8 BYTES)
VDD
ADDRESS
POINTER
IDENTIFICATION
NUMBER
EE
CONTROL
TIMER
(÷ 16)
POWER-ON RESET
OSCILLATOR
002aae847
VSS
Fig 1.
Block diagram
PCA24S08_2
Product data sheet
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PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
5. Pinning information
5.1 Pinning
n.c.
1
8
VDD
n.c.
2
7
WP
PROT
3
6
SCL
PROT
3
VSS
4
5
SDA
VSS
4
PCA24S08D
n.c.
1
8
VDD
n.c.
2
7
WP
6
SCL
5
SDA
002aae846
002aae845
Fig 2.
PCA24S08DP
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
n.c.
1, 2
not connected
PROT
3
active LOW protect reset input
VSS
4
ground supply voltage
SDA
5
serial data; open-drain I/O
SCL
6
serial clock; open-drain input
WP
7
active HIGH write protect input
VDD
8
supply voltage
6. Functional description
Refer to Figure 1 “Block diagram”.
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA24S08 is shown in Figure 4.
1
0
1
0
fixed
1
B2
B1 R/W
sofware
selectable
002aae789
Fig 4.
Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1
in the slave address represent the 2 most significant bits of the word to be addressed. The
third device address bit in the I2C-bus protocol that is usually matched to A2 (pin 3) on a
standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h
through AFh (hex) are used to access the memory on the chip.
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
4 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
6.2 Write operations
Write operations on the device can be performed only when WP is held LOW. When the
WP pin is held HIGH, content of the full memory is protected (Block 0 to Block 7,
APP registers, ID Page), and no write operation is allowed.
6.2.1 Byte/word write
Write command may be used to set the address for a subsequent Read command. For a
write operation, the PCA24S08 requires a second address field. The address field
associated with the two software selectable bits in the slave address is a word address
providing access to the 1024 bytes of memory, as shown in Figure 5. Upon receipt of the
word address, the PCA24S08 responds with an acknowledge and awaits the next 8 bits of
data, again responding with an acknowledge. Word address is automatically incremented.
BYTE 0
0
0
0
0
PAGE 0
0
0
0
BYTE 15
1
BLOCK 0
0
0
1
1
1
0
BYTE 0
0
0
0
0
PAGE 7
1
1
1
BYTE 15
1
1
1
1
BYTE 0
0
0
0
0
PAGE 0
0
0
0
BYTE 15
1
BLOCK 7
1
1
1
1
1
1
BYTE 0
0
0
0
0
PAGE 7
1
1
1
BYTE 15
1
1
0
1
0
1
B2
B1 R/W
B0
fixed
block number
Fig 5.
PCA24S08_2
Product data sheet
P2
P1
page
number
P0
A3
A2
A1
1
1
1
A0
byte
address
002aae790
Memory addressing
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PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
Figure 6 shows how the memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by generating a STOP
condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I2C-bus is
free for another transmission. Up to 16 bytes of data can be written in the slave writing
sequence (E/W cycle).
auto-increment
word address
word
address
S
1
0
1
START condition
0
1
B2 B1
auto-increment
word address
word address
0
A B0 P2 P1 P0 A3 A2 A1 A0 A
R/W acknowledge
from slave
acknowledge
from slave
DATA
A
acknowledge
from slave
DATA
A
P
acknowledge
from slave
STOP condition
002aae791
Fig 6.
Auto-increment memory word address (2 byte write)
The general command encoding used by the serial port for EEPROM accesses is shown
in Figure 11, where B[2:0] is the block number, P[2:0] is the page number within the block
and A[3:0] is the byte address within the page. Bits denoted as ‘X’ are ignored by the
device.
6.2.2 Page write
The PCA24S08 is capable of a 16-byte page write operation. It is initiated in the same
manner as the byte write operation. The master can transit 16 data bytes within one
transmission. After receipt of each byte, the PCA24S08 will respond with an acknowledge.
The typical E/W time in this mode is 5 ms.
After the receipt of each data byte, the four low-order bits of the word address are
internally incremented. The six high-order bits of the address remain unchanged. The
slave acknowledges the reception of each data byte with an ACK. The I2C-bus data
transfer is terminated by the master after the 16th byte of data with a STOP condition.
After a write to the last byte in a page, the internal address is wrapped around to point to
the beginning of that page. If the master transmits more than 16 bytes prior to generating
the STOP condition, no acknowledge will be given on the 17th (and following) data bytes
and the whole transmission will be ignored and no programming will be done. As in the
byte write operation, all inputs are disabled until completion of the internal write cycles.
After this STOP condition, the E/W cycle starts and the I2C-bus is free for another
transmission.
During the E/W cycle the slave receiver does not acknowledge if addressed via the
I2C-bus.
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
6 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
auto-increment
word address
word
address
S
1
0
1
0
1
word address
B2 B1
0
A B0 P2 P1 P0 A3 A2 A1 A0 A
R/W acknowledge
from slave
START condition
auto-increment
word address
DATA
acknowledge
from slave
A
A (cont.)
DATA + 1
acknowledge
from slave
acknowledge
from slave
auto-increment
word address
last byte
(cont.)
DATA + 15
A
P
acknowledge
from slave
STOP condition
002aae792
Fig 7.
Page write operation (16 bytes)
6.3 Read operations
Read operations are initiated in the same manner as write operations with the exception
that the LSB of the slave address is set to logic 1.
The lower 7 bits of the word address are incremented after each transmission of a data
byte during a read. The three MSBs of the word address are not changed when the word
counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128.
After the read of the last byte within a block, the internal serial address wraps around to
point at the beginning of that block.
word address
first part
S
1
0
1
0
1
B2 B1
0
R/W
START condition
word address
second part
A B0 P2 P1 P0 A3 A2 A1 A0 A (cont.)
acknowledge
from slave
acknowledge
from slave
at this moment master transmitter becomes
master receiver and EEPROM slave transmitter
(cont.)
S
1
0
1
0
1
X
X
1
A
DATA
A
n bytes
ReSTART
condition
R/W
auto-increment
word address
auto-increment
word address
acknowledge
from master
acknowledge
from master
DATA
A
P
last byte
no acknowledge
from master
STOP condition
002aae793
Fig 8.
Master reads PCA24S08 slave after setting word address (write word address: read data); sequential read
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
7 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
auto-increment
word address
S
1
0
1
0
1
X
X
1
A
DATA
A
n bytes
START condition
R/W
acknowledge
from slave
auto-increment
word address
DATA
A
P
last byte
acknowledge
from master
no acknowledge
from master
STOP condition
002aae794
Fig 9.
Master read PCA24S08 immediately after first byte (read mode); current address read
6.4 Access protection
Write operation on the Access protection registers can be performed when WP pin is
LOW. If the WP pin is HIGH, all write operations are prohibited from the serial port,
although write commands may be used to set the address for a subsequent read
command.
All access protection bits are stored on a separate page of the EEPROM that is not
accessed using the normal commands of a PCA24S08 memory. See Section 6.4.2.2
“Access Protection Page (APP)” for more detail on this information.
6.4.1 RFID access fields (RF)
Even though the PCA24S08 does not have the RFID capability, RFID access fields (RF)
can be stored in order to keep existing software compatibility. The fields are stored in the
EEPROM and organized as shown in Table 3.
Table 3.
RFID access field organization
MSB
LSB
Function
0
0
no accesses permitted from RFID port
0
1
no accesses permitted from RFID port
1
0
read only from RFID port
1
1
no restrictions for RFID accesses
6.4.2 Protection Bits (PB)
The protection bits fields in the Access Protection Page determine what type of accesses
will be permitted via the serial port for each of the blocks on the chip. If an illegal access is
attempted, the command will be NACKed. The MSB (if clear) prohibits all access to the
block, and the LSB (if clear) prohibits writes. The fields are stored in the EEPROM and are
organized as shown in Table 4.
Table 4.
PCA24S08_2
Product data sheet
PB organization
MSB
LSB
Function
0
0
no accesses permitted in the block
0
1
no accesses permitted in the block
1
0
read only; writes cause a NACK
1
1
read/write; no access constraints for data within this block
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© NXP B.V. 2010. All rights reserved.
8 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
Accessed within the Access Protection Page is an individual CMOS Sticky Bit (SB) for
each of the 8 blocks on the device. When the value of the sticky bit is ‘0’, the Protection
Bits (PB) for the corresponding block may not be changed via the software. These bits are
all set to logic 1 when power is initially applied or when the PROT pin is LOW. These
sticky bits may be written only to a ‘0’ via the serial interface using the standard serial write
operations. Reading the sticky bits does not affect their state.
Because permissions are set individually for each of the blocks, all reads via serial port
will only read bytes within the block that was specified when the current address was
latched in the device (with a write command). The block address bits (B2 or B1) that are
sent with the write command are ignored on a read command.
When a sticky bit is cleared (programmed at 0), the byte containing the sticky bit cannot
be changed anymore. If a write operation to this byte is attempted, it will be normally
acknowledged but no change will happen in the byte value. The device does not go to an
E/W cycle and can be accessed immediately.
If a block is protected and only read operation is allowed (the corresponding APP register
has its PB bits programmed to 10b), a write operation to this block is not acknowledged
(Slave Address and Register pointer only are acknowledged). The device does not go to
an E/W cycle and can be accessed immediately.
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
This applies to:
• EEPROM block 0 to block 7, controlled by PB0 to PB7.
• The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
If a block is protected and neither read operation nor write operation is allowed (the
corresponding APP register has its PB bits programmed to 00b or 01b), a write operation
to this block is not acknowledged (Slave Address and Register pointer only are
acknowledged).
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
A read operation to this block is not allowed.
S – Addr+W – ACK – Reg Pointer – ACK – Sr – Addr+R – NACK
S – Addr+W – ACK – Reg Pointer – ACK – P – S – Addr+R – NACK
This applies to:
• EEPROM block 0 to block 7, controlled by PB0 to PB7.
• The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
9 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
6.4.2.1
Block 0 write protection bits
The PCA24S08 provides a mechanism to divide block 0 into eight 128-bit (16-byte) pages
that can be individually protected against writes. These eight write protection (WPN) bits
are stored within a byte of the access protection page and are organized such that the
LSB protects the first 128 bits, and so on. If a bit in this byte is set to a one and the PB0
field is set to 11b, then writes are permitted on the page corresponding to the WPNx bit. If
the WPNx bit is set to a logic 0 or the PB0 is any value other than 11b, then writes are not
permitted in that page.
The write protection hierarchy for serial accesses is shown in Figure 10. In this drawing
the bits within the boxes to the left of the arrows are the only thing that determine whether
or not the bit in the box to the right of the arrow can be written. Read access control is not
shown in this diagram. Addresses listed in this diagram are for the serial port assuming
that the R/W bit in the command byte is set to ‘0’.
WP
SB0
SBAP
PBAP
A800
Page 0
16 bytes
PB0
A80F
A810
Page 1
16 bytes
WPN0
A81F
WPN1
Block 0
SB1
A870
Page 7
16 bytes
WPN7
A87F
A880
Block 1
128 bytes
PB1
A8FF
AE80
SB7
Block 7
128 bytes
PB7
AEFF
SB0
SB0
PB0 B800
SB1
SB1
PB1 B801
SB7
SB7
PB7 B807
SBAP
Access
Protection
Page
PBAP B808
B809
7 bytes
SBAP
PBAP
ID page
16 bytes
B80F
B810
B81F
002aae842
Fig 10. Write protection example
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
10 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
For example, when SB1 is a 1, the PB1 field can be written to any value by the system.
When the PB1 field is 11b, Block 1 can be written to by the system. Note that the state of
the SB1 bit does not affect whether or not Block 1 can be written.
There is no individual page write protection for any other block other than block 0 within
the device. Within the remaining blocks on the chip, access permissions are controlled on
a block basis (BP bits) or full chip basis (WP pin) only.
6.4.2.2
Access Protection Page (APP)
The serial port may be used to read and write the Access Protection Page (APP) and
ID Page using device access codes B8h and B9h instead of the normal value of A8h
through AFh (hex) that are used to access the rest of the EEPROM memory. The second
byte of write commands (the word address) should be in the range of 00h through 0Fh for
the APP page and 10h through 1Fh for the ID page. This coding is shown in Figure 11.
Reads and writes to these two pages may take place on a single byte basis only.
Multi-byte operations will be NACKed.
As an example, the bit encoding for a single byte read and write command are shown in
Figure 11.
The PCA24S08 will acknowledge all device addresses of B8h or B9h. If the most
significant three its of the word address are not all 0 (indicating an address outside the
Access protection and ID pages), the chip will NACK the access.
Byte 0 through byte 7 of the APP contain 8 identical sets of access control fields (PBx and
SBx) for each of the eight blocks of memory on the chip, which operate according to
Table 4. When the sticky bit in one of these bytes is set, that byte can be written by the
system. Once a sticky bit is reset (written to zero) by the software, the byte containing it
can no longer be modified by the software until the next power cycle. These bytes can
always be read by the system.
Byte 8 contains another PB field (PBAP) as bit 0 and bit 1, and an additional sticky bit
(SBAP) as bit 7. The value of the PBAP bits controls read and write access to the last
7 bytes (byte 9 through byte 15) of the APP and all 16 bytes of the ID page according to
the encoding listed in Section 6.4. The value of the PBAP bits can only be changed, a
write from the serial port, when SBAP is HIGH. This byte can always be read by the
system. Bit 0 through bit 6 of this byte are stored in EEPROM memory and do not change
when the power is cycled or the PROT pin changes state.
Byte 9 contains the eight block 0 write protection bits (WPN) for each page within block 0.
Byte 10 emulates a coil detection feature to keep compatibility with existing software
controlling device.
Even though the PCA24S08 does not have the RFID capability of the AT24RF03C, it
gives a ‘coil non-detected’ information when the detection feature is initiated.
The detection feature uses the Detection Enable bit (DE) and the Detect Coil bit (DC). At
power-up, DE = 0 and DC = 1. Detection is enabled by setting DE bit at 1. Since no coil is
detected, DC is then automatically reset and equal to 0.
DE is a read/write bit; DC is a read-only bit. Attempts to write to this bit will be ignored.
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
11 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
Bit 0 in the same byte emulates a TAMPER bit and is always equal to 0. TAMPER is a
read-only bit. Attempt to write a ‘1’ to this bit will be ignored.
Byte 11 through byte 14 are currently reserved and should not be used by the system.
Byte 14 may not be written by the device at any time.
Byte 11 to byte 13 are read/write bytes that are stored in the EEPROM.
Byte 14 is a read-only byte and the returned value during a read operation is FFh. A write
on it is acknowledged, but the write will be ignored.
1
0
1
1
1
0
0
0
0
0
0
P0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
002aae843
P0 is used to distinguish between
the APP and RFID pages:
0 = APP pages
1 = RFID pages
a. Write operations
1
0
1
1
1
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
002aae844
b. Read operations
Fig 11. Device access examples
Byte 15 contains device revision information stored in the EEPROM. It is set at the wafer
production facility and cannot be changed in the field, so any write to this byte will be
ignored but acknowledged. The value of this byte is 10h.
The memory map for the Access Protection Page is shown in Table 5 “APP memory map”.
In this table, an ‘X’ means that the value is a ‘Don’t care’ upon writing, and that it is
undefined upon reading. The PBx fields are all 2 bits wide, and the Device Revision field
is 8 bits wide. All other fields are 1 bit wide.
With the exception of the 9 Sticky Bits (SB), the two coil detect bits (DE and DC), the
tamper bit (TAMPER), and bytes 14 and 15, all bits within the Access Protection Page are
stored in EEPROM memory. Their state does not change if power is removed or when the
PROT pin is held LOW.
The following page of memory (accessed with A4 = 1) emulate the ID field that would be
transmitted by the device from the RFID port. Bytes within it are accessed with the
address byte at B8h or B9h (write/read). Reading and writing to this page is permitted
when PBAP is 11.
PCA24S08_2
Product data sheet
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Rev. 02 — 11 May 2010
© NXP B.V. 2010. All rights reserved.
12 of 25
PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
Table 5.
APP memory map
X = ‘Don’t care’ upon writing and undefined upon reading.
Address
Bit 7
Bit 6
0
SB0
X
1
SB1
X
2
SB2
3
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RF0
X
X
PB0
RF1
X
X
PB1
X
RF2
X
X
PB2
SB3
X
RF3
X
X
PB3
4
SB4
X
RF4
X
X
PB4
5
SB5
X
RF5
X
X
PB5
6
SB6
X
RF6
X
X
PB6
7
SB7
X
RF7
X
X
PB7
8
SBAP
X
X
X
X
X
9
WPN7
WPN6
WPN5
WPN4
WPN3
WPN2
WPN1
WPN0
10
DE
DC
X
X
X
X
X
TAMPER
11
reserved; R/W
12
reserved; R/W
13
reserved; R/W
14
reserved; read-only
15
device revision
PBAP
6.5 PROT pin
The PROT pin is used as a power good signal. When this pin is held LOW, the serial port
is held in reset and all sticky bits are set to one. When HIGH, activity on the serial bus is
permitted and sticky bits can be set to their values.
6.6 Serial EEPROM exceptions
In general, the two-wire serial interface on the PCA24S08 functions identically to the
24C08. The following exceptions exist, as noted elsewhere in this document.
• Pins 1, 2, and 3 have different usage.
• Access to various blocks may be restricted via the access protection circuitry.
• The two block address bits (B2 and B1) in the command byte are ignored with all read
commands. They are set only via the write command.
• Multi-byte reads do not cross block boundaries, but instead wrap to the beginning of
the block.
• The serial port will be reset whenever the PROT pin is LOW.
• If more than 16 bytes are written to the EEPROM with a page write, overlapping bytes
will have their values corrupted.
• If VDD is 0 V, the device draws current on the SDA, SCL, WP, and PROT pins when
they are brought above 0 V.
PCA24S08_2
Product data sheet
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© NXP B.V. 2010. All rights reserved.
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1024 × 8-bit CMOS EEPROM with access protection
7. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Functional operation under these conditions is not implied.
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
with respect to ground
-
4.6
V
VI
input voltage
SDA, SCL, PROT, WP pins
−0.1 to VDD
+0.3
V
Tstg
storage temperature
−55
+125
°C
Tamb
ambient temperature
−40
+85
°C
8. Static characteristics
Table 7.
Static characteristics
VDD = 2.5 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
VDD
supply voltage
IDD
supply current
Conditions
Min
Typ
Max
Unit
2.5
-
3.6
V
VDD = 3.6 V; fSCL = 100 kHz
EEPROM read
-
50
100
μA
EEPROM write
-
0.325
1.0
mA
Istb
standby current
VDD = 3.6 V; SDA, SCL = VSS
-
11.4
15
μA
II/O
input/output current
PROT, SDA, SCL pins;
VI = VDD or VSS
-
0.25
3.0
μA
II
input current
WP pin; VI = VDD = 5.5 V
-
-
20
μA
VIL
LOW-level input voltage
−0.1
-
VDD × 0.3
V
VIH
HIGH-level input voltage
VDD × 0.7
-
VDD
V
VOL
LOW-level output voltage
IOL = 2.1 mA
-
-
0.4
V
Ci
input capacitance
SCL, PROT, WP not tested
-
-
6
pF
Cio
input/output capacitance
SDA not tested
-
-
8
pF
PCA24S08_2
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1024 × 8-bit CMOS EEPROM with access protection
9. Dynamic characteristics
Table 8.
Dynamic characteristics
CL = 1 TTL gate and 100 pF, except as noted. VDD = 2.5 V to 3.6 V.
Symbol
Parameter
Conditions
fSCL
SCL clock frequency
tBUF
Standard-mode
I2C-bus
Fast-mode I2C-bus
Unit
Min
Max
Min
Max
0
100
0
400
bus free time between a STOP and
START condition
4.7
-
1.3
-
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
μs
tHD;DAT
data hold time
tVD;ACK
data valid acknowledge time
tVD;DAT
data valid time
kHz
μs
0
-
0
-
ns
[1]
-
600
-
600
ns
LOW level
[2]
-
600
-
600
ns
HIGH level
[2]
-
1500
-
600
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
tf
fall time of both SDA and SCL signals
-
300
tr
rise time of both SDA and SCL signals
-
1000
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
-
μs
20 + 0.1Cb
[3]
300
ns
20 + 0.1Cb
[3]
300
ns
50
ns
-
SDA
tr
tBUF
tf
tHD;STA
tSP
tLOW
SCL
tHD;STA
P
S
tSU;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STO
P
002aaa986
Fig 12. Timing diagram for serial interface
PCA24S08_2
Product data sheet
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1024 × 8-bit CMOS EEPROM with access protection
10. EEPROM memory
Table 9.
PCA24S08_2
Product data sheet
EEPROM memory specifications
Parameter
Specification
data retention at operating temperature
10 years (minimum)
endurance per byte
100,000 cycles (minimum)
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11. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 13. Package outline SOT96-1 (SO8)
PCA24S08_2
Product data sheet
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 14. Package outline SOT505-1 (TSSOP8)
PCA24S08_2
Product data sheet
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1024 × 8-bit CMOS EEPROM with access protection
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA24S08_2
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1024 × 8-bit CMOS EEPROM with access protection
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 15) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 11.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 15.
PCA24S08_2
Product data sheet
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 15. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 12.
PCA24S08_2
Product data sheet
Abbreviations
Acronym
Description
ACK
Acknowledge
APP
Access Protection Page
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
E/W
Erase/Write
EEPROM
Electrically Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
NACK
Not Acknowledge
PB
Protection Bit
RF
Radio Frequency
RFID
Radio Frequency IDentification
SB
Sticky Bit
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14. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA24S08_2
20100511
Product data sheet
-
PCA24S08_1
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Pin name “GND” changed to “VSS”
Figure 7 “Page write operation (16 bytes)” modified:
– removed STOP condition (P) following 4th acknowledge (A)
– last bit changed from acknowledge (A) to STOP condition (P)
•
•
Section 6.4.2.2 “Access Protection Page (APP)”: sub-section “Device Access Examples”
changed to Figure 11 “Device access examples”
Table 6 “Limiting values”:
– parameter “voltage on VDD with respect to ground” changed to “VDD, supply voltage” with
“respect to ground” moved to Conditions column
– parameter “voltage on SDA, SCL, PROT, and WP” changed to “VI; input voltage” with “SDA,
SCL, PROT and WP pins” moved to Conditions column
•
Table 7 “Static characteristics”:
– symbol/parameter changed from “IDDR; supply current, EEPROM reads” to “IDD; supply
current” with “EERPOM reads” moved to Conditions column
– under Conditions for IDD, changed “fSDA” to “fSCL”
– symbol/parameter changed from “IDDW; supply current, EEPROM writes” to “IDD; supply
current” and with “EERPOM writes” moved to Conditions column
– symbol/parameter changed from “ILIO; input/output current PROT, SDA, SCL”
to “II/O; input/output current” and with “PROT, SDA, SCL” moved to Conditions column
– symbol/parameter changed from “ILWP; input current on WP” to “II; input current” and with
“WP pin” moved to Conditions column
PCA24S08_1
(9397 750 13015)
PCA24S08_2
Product data sheet
•
Table 8 “Dynamic characteristics”: parameter description for symbol fSCL changed from
“operating frequency” to “SCL clock frequency”
•
•
Added soldering information
Added Table 12 “Abbreviations”
20040510
Product data
-
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-
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
PCA24S08_2
Product data sheet
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NXP Semiconductors
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA24S08_2
Product data sheet
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PCA24S08
NXP Semiconductors
1024 × 8-bit CMOS EEPROM with access protection
17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.5
6.6
7
8
9
10
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Device addressing . . . . . . . . . . . . . . . . . . . . . . 4
Write operations . . . . . . . . . . . . . . . . . . . . . . . . 5
Byte/word write . . . . . . . . . . . . . . . . . . . . . . . . . 5
Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Read operations . . . . . . . . . . . . . . . . . . . . . . . . 7
Access protection . . . . . . . . . . . . . . . . . . . . . . . 8
RFID access fields (RF) . . . . . . . . . . . . . . . . . . 8
Protection Bits (PB) . . . . . . . . . . . . . . . . . . . . . 8
Block 0 write protection bits . . . . . . . . . . . . . . 10
Access Protection Page (APP) . . . . . . . . . . . . 11
PROT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial EEPROM exceptions . . . . . . . . . . . . . . 13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
EEPROM memory . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Soldering of SMD packages . . . . . . . . . . . . . . 19
Introduction to soldering . . . . . . . . . . . . . . . . . 19
Wave and reflow soldering . . . . . . . . . . . . . . . 19
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 May 2010
Document identifier: PCA24S08_2
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