Data Sheet

NVT4857UK
SD 3.0-SDR104 compliant integrated auto-direction control
memory card voltage level translator with EMI filter and ESD
protection
Rev. 1 — 20 November 2015
Product data sheet
1. General description
The device is an SD 3.0-compliant bidirectional dual voltage level translator with
auto-direction control. It is designed to interface between a memory card operating at
1.8 V or 3.0 V signal levels and a host with a nominal supply voltage of 1.2 V to 1.8 V.
The device supports SD 3.0 SDR104, SDR50, DDR50, SDR25, SDR12 and SD 2.0
High-Speed (50 MHz) and Default-Speed (25 MHz) modes. The device has an integrated
voltage selectable low dropout regulator to supply the card-side I/Os, an auto-enable/
disable function connected to the VSD supply pin, built-in EMI filters and robust ESD
protections (IEC 61000-4-2, level 4).
2. Features and benefits
 Supports up to 208 MHz clock rate
 SD 3.0 specification-compliant voltage translation to support SDR104, SDR50,
DDR50, SDR25, SDR12, High-Speed and Default-Speed modes
 1.2 V to 1.8 V host side interface voltage support
 Feedback channel for clock synchronization
 100 mA Low dropout voltage regulator to supply the card-side I/Os
 Low power consumption by push-pull output stage with break-before-make
architecture
 Automatic enable and disable through VSD
 Integrated pull-up and pull-down resistors: no external resistors required
 Integrated EMI filters suppress higher harmonics of digital I/Os
 Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side
 Level shifting buffers keep ESD stress away from the host (zero-clamping concept)
 20-ball WLCSP; pitch 0.4 mm
3. Applications
 Smart phones
 Mobile handsets
 Digital cameras
 Tablet PCs
 Laptop computers
 SD, MMC or microSD card readers
NVT4857UK
NXP Semiconductors
SD 3.0 - SDR104 auto-direction control memory card level translator
4. Ordering information
Table 1.
Ordering information
Type number
NVT4857UK
Topside mark
NV4857
Package
Name
Description
Version
WLCSP20
wafer level chip-size package; 20 bumps (5  4),
size 1.7 x 2.1 x 0.49 mm, 0.4 mm pitch
NVT4857
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature
NVT4857UK
NVT4857UKZ
WLCSP20
REEL 7" Q1/T1 *SPECIAL
MARK CHIPS DP
500
Tamb = 40 C to +85 C
NVT4857UK
NVT4857UKAZ
WLCSP20
REEL 13" Q1/T1 *SPECIAL
MARK CHIPS DP
10000
Tamb = 40 C to +85 C
NVT4857UK
Product data sheet
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Rev. 1 — 20 November 2015
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SD 3.0 - SDR104 auto-direction control memory card level translator
5. Block diagram
VSUPPLY
PMU or DC/DC or LDO
3.0 V 400/800 mA
VSD
NVT4857
VSD
VCCB
I/O STAGE/LDO
VCCA
Cext
CLKA
CLK_FB
DAT1B
CMDA
LEVEL
TRANSLATOR
LOGIC
DAT0B
GND
CLKB
HOST/
BASEBAND
INTERFACE
VSD
DAT0A
SD-CARD
CMDB
DAT3B
DAT1A
DAT2B
DAT2A
DAT3A
CD
SEL
see data sheet
for details
basic push-pull driver
implementation
aaa-013308
Fig 1.
Application diagram
NVT4857UK
Product data sheet
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SD 3.0 - SDR104 auto-direction control memory card level translator
6. Functional diagram
VSD
VSD track mode
SEL
CARD SIDE
1.8 V OR VSD
R5
350 kΩ
VOLTAGE SELECT
+
INTERNAL REFERENCE
1.8 V VOLTAGE
REGULATOR
VLDO
R1
R2
CLKB
CLKA
R1
CLK_FB
Rpu
70 kΩ
R2
R1
Rpu
70 kΩ
CMDB
CMDA
Rpu
70 kΩ
R2
R1
Rpu
70 kΩ
DAT0B
R1
AUTO-DIRECTION CONTROL
DAT0A
Rpu
70 kΩ
DAT1A
R1
Rpu
70 kΩ
R2
DAT1B
Rpu
70 kΩ
R2
DAT2B
Rpu
70 kΩ
DAT2A
Rpu
70 kΩ
R2
R1
DAT3B
Rpu
70 kΩ
DAT3A
VCCA
R4
100 kΩ
R3
100 Ω
CD
GND
aaa-013315
Fig 2.
Functional diagram
NVT4857UK
Product data sheet
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SD 3.0 - SDR104 auto-direction control memory card level translator
7. Pinning information
7.1 Pinning
bump A1
index area
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
transparent top view,
solder balls facing down
aaa-018949
Fig 3.
Pin configuration WLCSP20
DAT2A
VCCA
VSD
DAT2B
DAT3A
CD
VCCB
DAT3B
CMDA
GND
GND
CMDB
DAT0A
CLKA
CLKB
DAT0B
DAT1A
CLK_FB
SEL
DAT1B
aaa-013317
Fig 4.
NVT4857UK pinout transparent top view
Table 3.
NVT4857UK
Product data sheet
Pin allocation table
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
A1
DAT2A
A2
VCCA
A3
VSD
A4
DAT2B
B1
DAT3A
B2
CD
B3
VCCB
B4
DAT3B
C1
CMDA
C2
GND
C3
GND
C4
CMDB
D1
DAT0A
D2
CLKA
D3
CLKB
D4
DAT0B
E1
DAT1A
E2
CLK_FB
E3
SEL
E4
DAT1B
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SD 3.0 - SDR104 auto-direction control memory card level translator
7.2 Pin description
Table 4.
NVT4857UK
Product data sheet
Pin description
Symbol [1]
Pin
Type [2]
Description
DAT2A
A1
I/O
data 2 input or output on host side
VCCA
A2
S
supply voltage from host side
VSD
A3
S
supply voltage
DAT2B
A4
I/O
data 2 input or output on memory card side
DAT3A
B1
I/O
data 3 input or output on host side
CD
B2
O
card detect switch biasing output
VCCB
B3
S
internal supply decoupling (VLDO)
DAT3B
B4
I/O
data 3 input or output on memory card side
CMDA
C1
I/O
command input or output on host side
GND
C2
S
supply ground
GND
C3
S
supply ground
CMDB
C4
I/O
command input or output on memory card side
DAT0A
D1
I/O
data 0 input or output on host side
CLKA
D2
I
clock signal input on host side
CLKB
D3
O
clock signal output on memory card side
DAT0B
D4
I/O
data 0 input or output on memory card side
DAT1A
E1
I/O
data 1 input or output on host side
CLK_FB
E2
O
clock feedback output on host side
SEL
E3
I
card side I/O voltage level select
DAT1B
E4
I/O
data 1 input or output on memory card side
[1]
The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.
[2]
I = input, O = output, I/O = input and output, S = power supply
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SD 3.0 - SDR104 auto-direction control memory card level translator
8. Functional description
8.1 Level translator
The bidirectional level translator shifts the data between the I/O supply levels of the host
and the memory card. The voltage translator has to support several clock and data
transfer rates at the signaling levels specified in the SD 3.0 standard specification.
Table 5.
Supported modes
Bus speed mode
Signal level (V)
Clock rate (MHz)
Data rate (MB/s)
Default-Speed
3.3
25
12.5
High-Speed
3.3
50
25
SDR12
1.8
25
12.5
SDR25
1.8
50
25
SDR50
1.8
100
50
SDR104
1.8
208
104
DDR50
1.8
50
50
8.2 Enable and direction control
The device contains an auto-enable feature. If VSD rises above 2.65 V, the LDO and the
level translator logic is enabled automatically. As soon as VSD drops below the VSDdisable,
as specified in Table 10, the LDO and the card side drivers and the level translator logic is
disabled. All host side pins excluding CLKA1 are configured as inputs with a 70 k resistor
pulled up to VCCA.
8.3 Integrated voltage regulator
The low dropout voltage regulator delivers supply voltage for the voltage translators and
the card-side input/output stages. It has to support 1.8 V and 3 V signaling modes as
stipulated in the SD 3.0 specification. The switching time between the two output voltage
modes is compliant with SD 3.0 specification. Depending on the signaling level at pin
SEL, the regulator delivers 1.8 V (SEL = HIGH) or 3.0 V (SEL = LOW).
Table 6.
SD card side voltage level control signal truth table
Input
Output
SEL[1]
VCCB
Pin[2]
Function
H
1.8 V
DAT0B to DAT3B, CLKB
low supply voltage level (1.8 Vtyp)
L
tracking VSD
DAT0B to DAT3B, CLKB
high supply voltage level (tracking VSD)
[1]
H = HIGH; L = LOW; X = don‘t care
[2]
Host-side pins are not influenced by SEL.
An external capacitor is needed between the regulator output pin VCCB and ground for
proper operation of the integrated voltage regulator. See Table 8 for recommended
capacitance and equivalent series resistance. It is recommended to place the capacitor
close to the VSD and VCCB pin and maintain short connections of both to ground.
1.
CLKA is a pure high-ohmic input. Please refer to Figure 2 “Functional diagram” for more detail.
NVT4857UK
Product data sheet
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SD 3.0 - SDR104 auto-direction control memory card level translator
8.4 Feedback clock channel
The clock is transmitted from the host to the memory card side. The voltage translator and
the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing
margin for data read back from memory card, especially at higher data rates. Therefore, a
feedback path is provided to compensate the delay. The reasoning behind this approach
is the fact that the clock is always delivered by the host, while the data in the timing critical
read mode comes from the card.
8.5 EMI filter
All input/output driver stages are equipped with EMI filters to reduce interferences towards
sensitive mobile communication.
8.6 ESD protection
The device has robust ESD protections on all memory card pins as well as on the VSD pin.
The architecture prevents any stress for the host: the voltage translator discharges any
stress to supply ground.
Pin Card Detection (CD) might be pulled down by the memory card which has to be
detected by the host. The pin is equipped with International Electrotechnical
Commission (IEC) system-level ESD protection and pull-up resistor connected to the host
supply VCCA.
NVT4857UK
Product data sheet
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SD 3.0 - SDR104 auto-direction control memory card level translator
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
4 ms transient
on pin VSD
0.5
+4.6
V
on pin VCCA
0.5
+4.6
V
VI
input voltage
4 ms transient at I/O pins
0.5
+4.6
V
Ptot
total power dissipation
Tamb = 40 C to +85 C
-
1000
mW
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
40
+85
C
VESD
Ilu(IO)
[1]
electrostatic discharge
voltage
IEC 61000-4-2, level 4, all memory card-side pins,
VSD and CD to ground
[1]
contact discharge
8
+8
kV
air discharge
15
+15
kV
Human Body Model (HBM)
JEDEC JESD22-A114F; all pins
2000
+2000
V
Charge Device Model (CDM) JEDEC
JESD22-C101E; all pins
500
+500
V
100
+100
mA
input/output latch-up current JESD 78B: 0.5  VCC < VI < 1.5  VCC;
Tj < 125 C
All system level tests are performed with the application-specific capacitors connected to the supply pins VSUPPLY, VLDO and VCCA.
10. Recommended operating conditions
Table 8.
Operating conditions
Symbol Parameter
supply voltage
VCC
Conditions
Min
Typ
Max
Unit
2.9
-
3.6
V
1.1
-
2.0
V
0.3
-
VCCA + 0.3
V
memory card side
0.3
-
VO(LDO) + 0.3 V
[1]
on pin VSD
on pin VCCA
input voltage
VI
[2]
host side
Cext
external
capacitance
recommended capacitor at pin VCCB
-
2.2
-
F
ESR
equivalent series
resistance
at pin VLDO
0
-
50
m
Cext
external
capacitance
recommended capacitor at pin VSD
-
0.1
-
F
recommended capacitor at pin VCCA
-
0.1
-
F
[1]
By minimum value the device is still fully functional, but the voltage on pin VLDO might drop below the recommended memory card
supply voltage.
[2]
The voltage must not exceed 3.6 V.
NVT4857UK
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SD 3.0 - SDR104 auto-direction control memory card level translator
Table 9.
Integrated resistors
Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Rpd
pull-down resistance
pull-up resistance
Rpu
Conditions
Min
series resistance
[1]
Max
Unit
R3; tolerance 30 %
70
100
130

R5
200
350
500
k
all data lines and CMDx
49
70
91
k
70
100
130
k
R4
Rs
Typ
host side; R1; tolerance 30 %
[1]
-
22.5
-

card side; R2; tolerance 30 %
[1]
-
15
-

Guaranteed by design.
11. Static characteristics
Table 10. Static characteristics
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 2.2 F at pin VCCB; unless otherwise specified.
Min
Typ[2]
Max
Unit
2.25
2.45
2.65
V
VSDdisable device disable voltage level VCCA 1.0 V, VSD falling edge
2.2
2.4
2.6
V
VSDen
-
50
-
mV
SEL = LOW;3.0 V  VSD  3.6 V;
IO < 100 mA
VSD-0.2
VSD-0.1
VSD
V
SEL = HIGH; VSD  2.9 V; IO < 100 mA
1.7
1.8
1.95
V
-
-
100
mA
Symbol
Parameter
Conditions
Automatic enable feature: VSD
VSDen
device enable voltage level VCCA 1.0 V, VSD rising edge
VSDen hysteresis voltage
Supply voltage regulator for card-side I/O pin: VCCB
VO(LDO)
IO(LDO)
regulator/switch output
voltage
regulator/switch output
current
Host-side input signals: CMDA and DAT0A to DAT3A, CLKA; 1.1 V  VCCA  2.0 V
VIH
HIGH-level input voltage
0.75 
VCCA
-
VCCA +
0.3
V
VIL
LOW-level input voltage
0.3
-
0.25 
VCCA
V
Host-side control signals; 1.1 V  VCCA  2.0 V
SEL
VIH
HIGH-level input voltage
0.75 
VCCA
-
VCCA +
0.3
V
VIL
LOW-level input voltage
0.3
-
0.25 
VCCA
V
Host-side output signals: CLK_FB, CMDA and DAT0A to DAT3A; 1.1 V  VCCA  2.0 V
VOH
VOL
HIGH-level output voltage
for CLK_FB
IO = 2 mA; VI = VIH (card side)
0.8 
VCCA
-
-
V
HIGH-level output voltage
for CMDA, DATxA
IO = 2 A; VI = VIH (card side)
0.8 
VCCA
-
-
V
LOW-level output voltage
IO = 2 mA; VI = VIL (card side)
-
-
0.15 
VCCA
V
NVT4857UK
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SD 3.0 - SDR104 auto-direction control memory card level translator
Table 10. Static characteristics …continued
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 2.2 F at pin VCCB; unless otherwise specified.
Symbol
Min
Typ[2]
Max
SEL = LOW (3.0 V card interface)
0.625 
VO(LDO)
-
VO(LDO) + V
0.3
SEL = HIGH (1.8 V card interface)
0.625 
VO(LDO)
-
VO(LDO) + V
0.3
SEL = LOW (3.0 V card interface)
0.3
-
0.3 
VO(LDO)
V
SEL = HIGH (1.8 V card interface)
0.3
-
0.35 
VO(LDO)
V
IO = 4 mA; VI = VIH (host side);
SEL = LOW (3.0 V card interface)
0.85 
VO(LDO)
-
VO(LDO) + V
0.3
IO = 2 mA; VI = VIH (host side);
SEL = HIGH (1.8 V card interface)
0.85 
VO(LDO)
-
2.0
V
HIGH-level output voltage
for CMDB, DATxB
IO = 2 A; VI = VIH (host side);
SEL = HIGH (1.8 V card interface)
0.85 
VO(LDO)
-
2.0
V
LOW-level output voltage
IO = 4 mA; VI = VIL (host side);
SEL = LOW (2.9 V card interface)
0.3
-
0.125 
VO(LDO)
V
IO = 2 mA; VI = VI card L (host side);
SEL = HIGH (1.8 V interface)
0.3
-
0.125 
VO(LDO)
V
host side
-
7
-
pF
card side
-
15
-
pF
Parameter
Conditions
Unit
Card-side input signals: CMDB and DAT0B to DAT3B
HIGH-level input voltage
VIH
VIL
LOW-level input voltage
Card-side output signal
CMDB and DAT0B to DAT3B, CLKB
VOH
VOL
HIGH-level output voltage
for CLKB only
Bus signal equivalent capacitance
channel capacitance
Cch
VI = 0 V; fi = 1 MHz; VSD = 3.0 V;
VCCA = 1.8 V
[3]
Current consumption
ICC(stat)
ICC(stb)
static supply current
standby supply current
VSD  VSDen (active mode);
all inputs = HIGH;
SEL = LOW (3.0 V card interface)
-
-
100
A
SEL = HIGH (1.8 V card interface)
-
-
100
A
-
-
7
A
VSD  VSDen and VCCA  1.0 V
(inactive mode);
all host side inputs = HIGH
[1]
Guaranteed by design and characterization.
[2]
Typical values are measured at Tamb = 25 C.
[3]
EMI filter line capacitance per data channel from I/O driver to pin; Cch is guaranteed by design.
NVT4857UK
Product data sheet
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Rev. 1 — 20 November 2015
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SD 3.0 - SDR104 auto-direction control memory card level translator
12. Dynamic characteristics
12.1 Voltage regulator
Table 11. Voltage regulator
Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage regulator output pin: VCCB
tstartup(LDO)
regulator start-up time
VCCA = 1.8 V; VSD = 3.0 V; Cext = 2.2 F;
see Figure 6
-
-
400
s
tf(o)
output fall time
VO(LDO) = 3.0 V to 1.8 V;
SEL = LOW to HIGH; see Figure 5
-
-
1
ms
tr(o)
output rise time
VO(LDO) = 1.8 V to 3.0 V;
SEL = HIGH to LOW; see Figure 5
-
-
100
s
VSD
VSD
CLK_SD
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
0V
5 ms (min.)
VSD
VSD
CMD
0V
VSD
VSD
DATA[3:0]
0V
SEL
0V
50 %
50 %
VSD
VLDO
1.8 V
0V
tr(o)
tf(o)
97 %
1.8 V
150 mV
VSD
1.8 V
aaa-013318
Fig 5.
Regulator mode change timing
VSD
2.65 V
VSD
GND
tstartup(reg)
VO(reg)
97 %
regulator
output
0V
aaa-013319
Measuring points: VSD signal at 2.65 V and regulator output signal at 0.97 VO(LDO).
Fig 6.
Regulator start-up time
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SD 3.0 - SDR104 auto-direction control memory card level translator
12.2 Level translator
Table 12. Level translator dynamic characteristics
At recommended operating conditions; VCCA = 1.2 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Host side transition times
tr
rise time
tf
fall time
rise time
tr
fall time
tf
SEL = HIGH (1.8 V card interface);
VCCA = 1.8 V
[1]
-
0.4
1.0
ns
[1]
-
0.4
1.0
ns
SEL = HIGH (1.8 V card interface);
VCCA = 1.2 V
[1]
-
0.4
1.0
ns
[1]
-
0.4
1.0
ns
SEL = HIGH (1.8 V card interface)
[2]
0.4
0.9
1.4
ns
SEL = HIGH (1.8 V card interface)
[2]
0.4
0.9
1.4
ns
SEL = HIGH (1.8 V card interface);
VCCA = 1.2 V
-
3.0
5.5
ns
SEL = HIGH (1.8 V card interface);
VCCA = 1.2 V
-
5.5
10.0
ns
SEL = HIGH (1.8 V card interface);
VCCA = 1.2 V
-
2.5
4.5
ns
Card side transition times
rise time
tr
fall time
tf
Host to card propoagation delay
DATxA to DATxB, CMDA to CMDB, CLKA to CLKB
propagation delay
tpd
CLKA to CLK_FB
propagation delay
tpd
Card to host propagation delay
DATxB to DATxA, CMDB to CMDA
tpd
propagation delay
[1]
transition between VOL = 0.35 * VCCA and VOH = 0.65 * VCCA
[2]
transition between VOL = 0.45 V and VOH = 1.4 V
VCC
VOH
VOL
GND
tf
VOL
tr
VOH
aaa-014796
VOH and VOL are specified in Table 12 as Table note [1] and Table note [2]
Fig 7.
Output rise and fall times
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input
0.5*VCCI
output
0.5*VCCI
0.5*VCCO
tpd
0.5*VCCO
tpd
aaa-013321
Output delay is for every single channel, from input to output, 0.5*VCCI to 0.5*VCCO, in which VCCI
and VCCO are the input and output voltage domain.
Fig 8.
Output delay timing
12.3 ESD characteristic of pin card detect
Table 13. ESD characteristic of card detect
At recommended operating conditions; Tamb = +25 C; voltages are referenced to
GND (ground = 0 V); unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ESD protection pins: CD
VBR
rdyn
[1]
NVT4857UK
Product data sheet
breakdown voltage
dynamic resistance
TLP; I = 1 mA
-
8
-
V
positive transient
[1]
-
0.5
-

negative transient
[1]
-
0.5
-

TLP according to ANSI-ESD STM5.5.1/IEC 62615 Zo = 50 ; pulse width = 100 ns; rise time = 200 ps;
averaging window = 50 ns to 80 ns
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13. Test information
SXOVHZLGWK
9,
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9,
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92
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5WHUP
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DDD
Definitions test circuit:
Rsource = source resistance of pulse generator.
Rterm = termination resistance should be equal to output impedance Zo of pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
Fig 9.
NVT4857UK
Product data sheet
Load circuitry for measuring switching time
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14. Package outline
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Fig 10. Package outline NVT4857UK (WLCSP20)
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15. Packing information
4.00 ± 0.10
2.00 ± 0.05
4.00 ± 0.10
Ø 1.50 + 0.10
1.75 ± 0.10
8.00
5° max.
3.50 ± 0.05
+ 0.30
− 0.10
K0 B0 2.25 ± 0.05
K0
K0
A0
Ø 0.50 ± 0.05
5° max.
0.65 ± 0.05
0.25 ± 0.02
1.85 ± 0.05
All dimensions in mm.
aaa-013545
Fig 11. Carrier tape
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16. Soldering of WLCSP packages
16.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
16.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
16.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 14.
Table 14.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
16.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
16.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
16.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
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Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
16.3.4 Cleaning
Cleaning can be done after reflow soldering.
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17. Abbreviations
Table 15.
Abbreviations
Acronym
Description
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
MMC
MultiMedia Card
PCB
Printed-Circuit Board
RoHS
Restriction of Hazardous Substances
SD
Secure Digital
WLCSP
Wafer-Level Chip-Scale Package
18. Revision history
Table 16.
Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
NVT4857UK v.1
20151120
-
-
NVT4857UK
Product data sheet
Product data sheet
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NVT4857UK
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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21. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
9
10
11
12
12.1
12.2
12.3
13
14
15
16
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
17
18
19
19.1
19.2
19.3
19.4
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Level translator . . . . . . . . . . . . . . . . . . . . . . . . . 7
Enable and direction control . . . . . . . . . . . . . . . 7
Integrated voltage regulator . . . . . . . . . . . . . . . 7
Feedback clock channel . . . . . . . . . . . . . . . . . . 8
EMI filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions. . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 12
Level translator . . . . . . . . . . . . . . . . . . . . . . . . 13
ESD characteristic of pin card detect . . . . . . . 14
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Packing information . . . . . . . . . . . . . . . . . . . . 17
Soldering of WLCSP packages. . . . . . . . . . . . 18
Introduction to soldering WLCSP packages . . 18
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 18
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Quality of solder joint . . . . . . . . . . . . . . . . . . . 19
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 November 2015
Document identifier: NVT4857UK
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