Data Sheet

PCF2113x
LCD controllers/drivers
Rev. 04 — 4 March 2008
Product data sheet
1. General description
The PCF2113x is a low-power CMOS LCD controller and driver, designed to drive a dot
matrix LCD display of 2 lines of 12 characters or 1 line of 24 characters with 5 × 8 dot
format. All necessary functions for the display are provided in a single chip, including
on-chip generation of LCD bias voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2113x interfaces to most
microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a
character generator and displays alphanumeric and kana (Japanese) characters.
The letter ‘x’ in PCF2113x characterizes the built-in character set. Various character sets
can be manufactured on request.
2. Features
n Single-chip LCD controller/driver
n 2-line display of up to 12 characters + 120 icons, or 1-line display of up to
24 characters + 120 icons
n 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user-defined
symbols
n Icon mode for e.g. additional segment display section: reduced current consumption
while displaying icons only
n Icon blink function
n Very low current consumption (20 µA to 200 µA):
u Icon mode: < 25 µA
u Power-down mode: < 2 µA
n On-chip:
u Configurable 4, 3 or 2 voltage multiplier, generating LCD supply voltage VLCD,
independent of VDD, programmable by instruction (external supply also possible)
u Temperature compensation of on-chip generated VLCD: −0.16 %/K to −0.24 %/K
(programmable by instruction)
u Generation of intermediate LCD bias voltages
u Oscillator requires no external components (external clock also possible)
n Display data RAM: 80 characters
n Character generator ROM: 240 characters of 5 × 8 dots
n Character generator RAM: 16 characters of 5 × 8 dots; 3 characters used to drive
120 icons, 6 characters used if icon blink feature is used in application
n 4-bit or 8-bit parallel bus and 2-wire I2C-bus interface
n 18 row and 60 column outputs
PCF2113x
NXP Semiconductors
LCD controllers/drivers
n Multiplex rates (MUX) 1:18 (for normal operation), 1:9 (for single-line operation) and
1:2 (for Icon-only mode)
n Uses common 11 code instruction set (extended)
n Logic supply voltage range VDD1 − VSS1 = 1.8 V to 5.5 V (chip may be driven with two
battery cells)
n VLCD generator supply voltage range VDD2 − VSS2 = 2.2 V to 4.0 V
n Display supply voltage range VLCD − VSS2 = 2.2 V to 6.5 V
n Direct mode to save current consumption for Icon mode and MUX 1:9 (depending on
VDD2 and LCD liquid properties)
n CMOS compatible
n Remark: Icon mode is a way to save current. When only icons are displayed (i.e. only
the lower two rows are active), a much lower operating voltage VLCD can be used and
the switching frequency of the LCD outputs is reduced. In most applications it is
possible to use VDD as VLCD.
3. Applications
n Telecom equipment
n Point-of-sale terminals
n Portable instruments
4. Ordering information
Table 1.
Ordering information
Type number
Package
Description
Version
PCF2113AU/10/F4 -
Name
chip on flexible film carrier
-
PCF2113DU/F4
-
chip in tray
-
PCF2113DH/4
LQFP100
plastic low profile quad flat package; 100 leads; SOT407-1
body 14 × 14 × 1.4 mm
PCF2113DU/2/F4
-
chip with bumps in tray
-
PCF2113EU/2/F4
-
chip with bumps in tray
-
PCF2113WU/2/F4
-
chip with bumps in tray
-
5. Marking
Table 2.
Marking codes
Type number
Marking code
PCF2113DH/4
PCF2113DH
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
2 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
6. Block diagram
C1 to C60
R1 to R18
18
60
COLUMN DRIVERS
BIAS
VOLTAGE
GENERATOR
VLCDIN
60
VLCDSENSE
18
DATA LATCHES
SHIFT REGISTER 18-BIT
60
VLCD
VLCDOUT
ROW DRIVERS
SHIFT REGISTER 5 × 12 BIT
GENERATOR
VDD3
5
OSC
OSCILLATOR
CURSOR AND DATA CONTROL
5
VDD1
VDD2
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
TIMING
GENERATOR
VSS1
8
VSS2
DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
7
T1
T2
PD
7
T3
7
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
(AC)
7
7
INSTRUCTION
DECODER
PCF2113x
DATA
REGISTER
(DR)
8
INSTRUCTION
REGISTER (IR)
BUSY
FLAG
8
POWER-ON
RESET
8
I/O BUFFER
DB0 to DB3/SA0
Fig 1.
DB4 to DB7
E
R/W
RS
SCL
SDA
mge990
Block diagram of PCF2113x
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
3 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
7. Pinning information
77 C1
76 C2
78 R8
79 R7
80 R6
81 R5
82 R4
83 R3
84 R2
85 R1
86 R17
87 SCL
88 SDA
89 E
90 RS
91 R/W
92 DB7
93 DB6
94 DB5
95 DB4
96 DB3/SA0
97 DB2
98 DB1
99 DB0
100 VDD2
7.1 Pinning
VDD1
1
75 C3
OSC
2
74 C4
PD
3
73 C5
T1
4
72 C6
VSS1
5
71 C7
VSS2
6
70 C8
VLCDOUT
7
69 C9
VLCDIN
8
68 C10
R9
9
67 C11
R10 10
66 C12
R11 11
65 C13
R12 12
64 C14
PCF2113x
R13 13
62 C16
R15 15
61 C17
R16 16
60 C18
R18 17
59 C19
C60 18
58 C20
C59 19
57 C21
C58 20
56 C22
C57 21
55 C23
C56 22
54 C24
C28 50
C29 49
C30 48
C31 47
C32 46
C33 45
C34 44
C35 43
C36 42
C37 41
C38 40
C39 39
C40 38
C41 37
C42 36
C43 35
C44 34
C45 33
C46 32
C47 31
51 C27
C48 30
C53 25
C49 29
52 C26
C50 28
53 C25
C54 24
C51 27
C55 23
C52 26
Fig 2.
63 C15
R14 14
mge989
Pin configuration for PCF2113DH (LQFP100)
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
4 of 65
PCF2113x
NXP Semiconductors
dummy pad 6
84
C2
C1
R8
R7
R6
R5
R4
R3
R2
R1
R17
85
86
87
88
89
90
91
92
93
94
95
SCL
SDA
3.36
mm
C20
C21
C22
C23
C24
C25
C26
C27
dummy pad 4
63
62
61
60
59
58
57
C14
71
64
C13
72
C19
C12
73
65
C11
74
C18
C10
75
66
C9
76
C17
C8
77
67
C7
78
C16
C6
79
68
C5
80
C15
C4
81
69
C3
82
70
dummy pad 5
83
LCD controllers/drivers
y
PCF2113x
96
97
56
dummy pad 3
55
C28
54
C29
53
C30
52
C31
51
C32
50
C33
49
C34
48
C35
47
C36
46
C37
45
C38
44
C39
43
C40
42
C41
41
C42
E
98
RS
99
R/W
100
DB7
101
40
C43
DB6
102
39
C44
DB5
103
38
C45
DB4
104
37
C46
DB3
105
36
C47
DB2
106
35
C48
DB1
107
34
C49
33
C50
32
C51
DB0
108
VDD2
109
x
0
0
29
dummy pad 1
10
VLCDSENSE
23
24
25
26
27
28
9
VLCDOUT
C58
C57
C56
C55
C54
C53
7
8
VSS1
VSS2
12
13
14
15
16
17
18
19
20
21
22
6
T2
R9
R10
R11
R12
R13
R14
R15
R16
R18
C60
C59
5
T1
11
4
T3
VLCDIN
3
dummy pad 2
PD
30
2
111
OSC
dummy pad 7
1
C52
112
31
VDD1
110
dummy pad 8
VDD3
3.52 mm
mgu205
Fig 3.
Bonding pad locations for PCF2113xU (bottom view)
Table 3.
Pin (LQFP100 package) or pad allocation table
Pin
Pad
Symbol
1
1
VDD1
-
84
dummy pad
2
2
OSC
76
85
C2
3
3
PD
77
86
C1
-
4
T3
78 to 85
87 to 94
R8 to R1
4
5
T1
86
95
R17
-
6
T2
87
96
SCL
5
7
VSS1
88
97
SDA
6
8
VSS2
89
98
E
7
9
VLCDOUT
90
99
RS
-
10
VLCDSENSE
91
100
R/W
PCF2113_FAM_4
Product data sheet
Pin
Pad
Symbol
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
5 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 3.
Pin (LQFP100 package) or pad allocation table …continued
Pin
Pad
Symbol
Pin
Pad
Symbol
8
11
VLCDIN
92
101
DB7
9 to 16
12 to 19
R9 to R16
93
102
DB6
17
20
R18
94
103
DB5
18 to 25
21 to 28
C60 to C53
95
104
DB4
-
29
dummy pad
96
105
DB3/SA0
-
30
dummy pad
97
106
DB2
26 to 50
31 to 55
C52 to C28
98
107
DB1
-
56
dummy pad
99
108
DB0
-
57
dummy pad
100
109
VDD2
51 to 75
58 to 82
C27 to C3
-
110
VDD3
-
83
dummy pad
-
-
-
Table 4.
Bonding pad dimensions
Pad
Size
Unit
Type
galvanic pure Au
Bump dimensions
(50 ± 6) × (90 ± 6) × (17.5 ± 5)
µm
Height difference in one die
<2
µm
Convex deformation
<5
µm
Pad size (aluminium)
62 × 100
µm
Passivation opening
36 × 76
µm
Pad pitch
−635.0
µm
Wafer thickness (excluding bumps)
380 ± 25
[1]
Fab 1
µm
Fab 2
[2]
Die size X
3.52
3.47
mm
Die size Y
3.36
3.31
mm
[1]
Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer).
[2]
Fab 2 identification starts with AXnnnn, where X represents a letter or a number and n represents a number
between 0 and 9 (6 inch wafer).
Table 5.
Pin and bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type
Pad
X (µm)
Y (µm)
Description
VDD1
1
P
1
−1345
−1550
supply voltage 1 for all except VLCD
generator
OSC
2
I
2
−1155
−1550
oscillator and external clock input
PD
3
I
3
−1 055
−1550
power-down select input; for normal
operation PD is LOW
T3
-
I
4
−845
−1550
test pad; open circuit and not user
accessible
T1
4
I
5
−765
−1550
test pin; must be connected to VSS1
T2
-
I
6
−665
−1550
test pad; must be connected to VSS1
VSS1
5
P
7
−525
−1550
ground 1 for all except VLCD generator
PCF2113_FAM_4
Product data sheet
[1]
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
6 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type
Pad
X (µm)
Y (µm)
Description
VSS2
6
P
8
−455
−1550
ground 2 for VLCD generator
VLCDOUT
7
O
9
−295
−1550
VLCD output if VLCD is generated internally
[2]
VLCDSENSE
-
I
10
−145
−1550
input (VLCD) for voltage multiplier regulation
[2][3]
VLCDIN
8
I
11
15
−1550
input for generation of LCD bias levels
[2]
R9
9
O
12
175
−1550
LCD row driver output
R10
10
O
13
245
−1550
LCD row driver output
R11
11
O
14
315
−1550
LCD row driver output
R12
12
O
15
385
−1550
LCD row driver output
R13
13
O
16
455
−1550
LCD row driver output
R14
14
O
17
525
−1550
LCD row driver output
R15
15
O
18
595
−1550
LCD row driver output
R16
16
O
19
665
−1550
LCD row driver output
R18
17
O
20
735
−1550
LCD row driver output
C60
18
O
21
805
−1550
LCD column driver output
C59
19
O
22
875
−1550
LCD column driver output
C58
20
O
23
995
−1550
LCD column driver output
C57
21
O
24
1065
−1550
LCD column driver output
C56
22
O
25
1135
−1550
LCD column driver output
C55
23
O
26
1205
−1550
LCD column driver output
C54
24
O
27
1275
−1550
LCD column driver output
C53
25
O
28
1345
−1550
LCD column driver output
dummy pad 1
-
-
29
1435
−1550
-
dummy pad 2
-
-
30
1630
−1395
-
C52
26
O
31
1630
−1255
LCD column driver output
C51
27
O
32
1630
−1155
LCD column driver output
C50
28
O
33
1630
−1055
LCD column driver output
C49
29
O
34
1630
−955
LCD column driver output
C48
30
O
35
1630
−735
LCD column driver output
C47
31
O
36
1630
−635
LCD column driver output
C46
32
O
37
1630
−535
LCD column driver output
C45
33
O
38
1630
−435
LCD column driver output
C44
34
O
39
1630
−335
LCD column driver output
C43
35
O
40
1630
−235
LCD column driver output
C42
36
O
41
1630
−135
LCD column driver output
C41
37
O
42
1630
−35
LCD column driver output
C40
38
O
43
1630
65
LCD column driver output
C39
39
O
44
1630
165
LCD column driver output
C38
40
O
45
1630
265
LCD column driver output
C37
41
O
46
1630
365
LCD column driver output
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
7 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type
Pad
X (µm)
Y (µm)
Description
C36
42
O
47
1630
465
LCD column driver output
C35
43
O
48
1630
565
LCD column driver output
C34
44
O
49
1630
665
LCD column driver output
C33
45
O
50
1630
765
LCD column driver output
C32
46
O
51
1630
865
LCD column driver output
C31
47
O
52
1630
965
LCD column driver output
C30
48
O
53
1630
1065
LCD column driver output
C29
49
O
54
1630
1165
LCD column driver output
C28
50
O
55
1630
1265
LCD column driver output
dummy pad 3
-
-
56
1630
1335
-
dummy pad 4
-
-
57
1435
1550
-
C27
51
O
58
1335
1550
LCD column driver output
C26
52
O
59
1225
1550
LCD column driver output
C25
53
O
60
1115
1550
LCD column driver output
C24
54
O
61
1005
1550
LCD column driver output
C23
55
O
62
765
1550
LCD column driver output
C22
56
O
63
665
1550
LCD column driver output
C21
57
O
64
565
1550
LCD column driver output
C20
58
O
65
465
1550
LCD column driver output
C19
59
O
66
365
1550
LCD column driver output
C18
60
O
67
265
1550
LCD column driver output
C17
61
O
68
165
1550
LCD column driver output
C16
62
O
69
65
1550
LCD column driver output
C15
63
O
70
−35
1550
LCD column driver output
C14
64
O
71
−135
1550
LCD column driver output
C13
65
O
72
−235
1550
LCD column driver output
C12
66
O
73
−335
1550
LCD column driver output
C11
67
O
74
−435
1550
LCD column driver output
C10
68
O
75
−535
1550
LCD column driver output
C9
69
O
76
−635
1550
LCD column driver output
C8
70
O
77
−735
1550
LCD column driver output
C7
71
O
78
−835
1550
LCD column driver output
C6
72
O
79
−965
1550
LCD column driver output
C5
73
O
80
−1065
1550
LCD column driver output
C4
74
O
81
−1165
1550
LCD column driver output
C3
75
O
82
−1265
1550
LCD column driver output
dummy pad 5
-
-
83
−1465
1550
-
dummy pad 6
-
-
84
−1630
1355
-
C2
76
O
85
−1630
1255
LCD column driver output
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
8 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type
Pad
X (µm)
Y (µm)
Description
C1
77
O
86
−1630
1185
LCD column driver output
R8
78
O
87
−1630
1115
LCD row driver output
R7
79
O
88
−1630
1045
LCD row driver output
R6
80
O
89
−1630
975
LCD row driver output
R5
81
O
90
−1630
905
LCD row driver output
R4
82
O
91
−1630
835
LCD row driver output
R3
83
O
92
−1630
765
LCD row driver output
R2
84
O
93
−1630
695
LCD row driver output
R1
85
O
94
−1630
625
LCD row driver output
R17
86
O
95
−1630
555
LCD row driver output
SCL
87
I
96
−1630
375
I2C-bus serial clock input
[4]
[4]
SDA
88
I/O
97
−1630
305
I2C-bus
E
89
I
98
−1630
85
data bus clock input
RS
90
I
99
−1630
−15
register select input
R/W
91
I
100
−1630
−115
read or write input
DB7
92
I/O
101
−1630
−215
8-bit bidirectional bus bit 7
DB6
93
I/O
102
−1630
−315
8-bit bidirectional bus bit 6
DB5
94
I/O
103
−1630
−415
8-bit bidirectional bus bit 5
DB4
95
I/O
104
−1630
−515
8-bit bidirectional bus bit 4
DB3/SA0
96
I/O
105
−1630
−615
8-bit bidirectional bus bit 3 or I2C-bus
address input
DB2
97
I/O
106
−1630
−715
8-bit bidirectional bus bit 2
DB1
98
I/O
107
−1630
−815
8-bit bidirectional bus bit 1
DB0
99
I/O
108
−1630
−915
8-bit bidirectional bus bit 0
VDD2
100
P
109
−1630
−1015
supply voltage 2 for VLCD generator
[6]
VDD3
-
P
110
−1630
−1235
supply voltage 3 for VLCD generator
[3][6]
dummy pad 7
-
-
111
−1630
−1395
-
dummy pad 8
-
-
112
−1465
−1550
-
serial data input/output
[4]
[5]
[4][5]
[1]
When the on-chip oscillator is used this pad must be connected to VDD1.
[2]
When VLCD is generated internally, pins VLCDIN, VLCDOUT and VLCDSENSE must be connected together. When an external VLCD is
supplied, this should be done via VLCDIN. In this case only pins VLCDOUT and VLCDSENSE must be connected together.
[3]
In the LQFP100 version this signal is connected internally and is not accessible.
[4]
When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode pins DB7 to DB0 must be connected to
VDD1 or left open-circuit.
When the parallel bus is used, the pins SCL and SDA must be connected to pin VSS1 or pin VDD1; they must not be left open-circuit.
When the 4-bit interface is used without reading out from the PCF2113x (bit R/W is set permanently to logic 0), the unused ports DB0 to
DB3 can either be connected to VSS1 or VDD1 instead of leaving them open-circuit.
[5]
DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order
lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see Table note 4).
[6]
VDD2 and VDD3 must always be equal.
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PCF2113x
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LCD controllers/drivers
8. Functional description
8.1 LCD supply voltage generator
The LCD supply voltage (VLCD) may be generated on-chip. The VLCD generator is
controlled by two internal 6-bit registers: VA and VB. Section 10.10.1 shows how to
program these registers. The nominal LCD operating voltage at room temperature is given
by the relationship:
Voper(nom) = (integer value of register × 0.08 V) + 1.82 V
With a programmed value from 1 to 63, Voper(nom) = 1.90 V to 6.86 V at Tamb = 27 °C.
Values producing more than 6.5 V at operating temperature are not allowed. Operation
above this voltage may damage the device. When programming the operating voltage the
VLCD tolerance and temperature coefficient must be taken into account.
Values below 2.2 V are below the specified operating range of the chip and therefore are
not allowed.
Value 0 for VA and VB switches off the generator (i.e. VA = 0 in Character mode, VB = 0 in
Icon mode).
Usually register VA is programmed with the voltage for Character mode and register VB
with the voltage for Icon mode.
When VLCD is generated on-chip, the VLCD pins must be decoupled to VSS with a suitable
capacitor.
The generated VLCD is independent of VDD and is temperature compensated. When the
VLCD generator and the Direct mode are switched off, an external voltage may be supplied
at pins VLCDIN and VLCDOUT (which are connected together). VLCDIN and VLCDOUT may be
higher or lower than VDD2.
During Direct mode (program DM bit) the internal VLCD generator is turned off and the
VLCDOUT output voltage is directly connected to VDD2. This reduces the current
consumption during Icon mode and MUX 1:9 (depending on VDD2 and LCD liquid
properties).
The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to 4 V), the
required peak operating voltage of 6.5 V can be generated at any time.
8.2 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This
removes the need for an external resistive bias chain and significantly reduces the system
current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD
threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1:18
maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the
different multiplex rates are shown in Table 6. These bias levels are automatically set to
the given values when switching to the corresponding multiplex rate.
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 6.
Multiplex
rate
Bias levels as a function of multiplex rate
Number
of levels
Bias voltages[1]
V1
V2
V3
V4
V5
V6
1⁄
2
1⁄
2
1⁄
4
VSS
1:18
5
VLCD
3⁄
4
1:9
5
VLCD
3⁄
4
1⁄
2
1⁄
2
1⁄
4
VSS
VLCD
2⁄
3
2⁄
3
1⁄
3
1⁄
3
VSS
1:2
[1]
4
The values in the table are given relative to VLCD − VSS, e.g. 3⁄4 means {3⁄4 × (VLCD − VSS)} + VSS.
8.3 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC pin must be connected to VDD1.
8.4 External clock
If an external clock is to be used, this input is at the OSC pin. The resulting display frame
f osc
frequency is given by: f fr ( LCD ) = ----------3072
Only in the Power-down mode is the clock allowed to be stopped (pin OSC connected to
VSS), otherwise the LCD is frozen in a DC state.
8.5 Power-on reset
The on-chip power-on reset block initializes the chip after power-on or power failure. This
is a synchronous reset and requires 3 oscillator cycles to be executed.
8.6 Registers
The PCF2113x has two 8-bit registers: an Instruction Register (IR) and a Data
Register (DR). The Register Select (RS) signal determines which register will be
accessed. The instruction register stores instruction codes such as ‘display clear’, ‘cursor
shift’, and address information for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be written to but not read from by
the system controller.
The data register temporarily stores data to be read from the DDRAM and CGRAM. When
reading, data from the DDRAM or CGRAM corresponding to the address in the instruction
register is written to the data register prior to being read by the ‘read data’ instruction.
8.7 Busy flag
The busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the
chip is busy and further instructions will not be accepted. The busy flag is output to
pin DB7 when bit RS = 0 and bit R/W = 1. Instructions must only be written after checking
that the busy flag is at logic 0 or waiting for the required number of cycles.
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8.8 Address counter
The Address Counter (AC) assigns addresses to the DDRAM and CGRAM for reading
and writing and is set by the commands ‘set DDRAM address’ and ‘set CGRAM address’.
After a read/write operation the address counter is automatically incremented or
decremented by 1. The address counter contents are output to the bus (DB6 to DB0)
when bit RS = 0 and bit R/W = 1.
8.9 Display data RAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented
by 8-bit character codes. RAM locations which are not used for storing display data can be
used as general purpose RAM. The basic RAM to display addressing scheme is shown in
Figure 4. With no display shift the characters represented by the codes in the first 24 RAM
locations starting at address 00h in line 1 are displayed. Figure 5 and Figure 6 show the
display mapping for right and left shift respectively.
When data is written to or read from the DDRAM, wrap-around occurs from the end of one
line to the start of the next line. When the display is shifted each line wraps around within
itself, independently of the others. Thus all lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the various modes are shown in
Table 7.
display
position
DDRAM
address
non-displayed DDRAM addresses
1 2 3 4 5
22 23 24
00 01 02 03 04
15 16 17 18 19
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
DDRAM
address
1 2 3 4 5
10 11 12
00 01 02 03 04
09 0A 0B 0C 0D
1 2 3 4 5
10 11 12
40 41 42 43 44
49 4A 4B 4C 4D
24 25 26 27
line 1
64 65 66 67
line 2
mge991
2-line display
Fig 4.
DDRAM to display mapping: no shift
display
position
DDRAM
address
5
22 23 24
4F 00 01 02 03
1
2 3
4
14 15 16
1-line display
1
DDRAM
address
5
10 11 12
27 00 01 02 03
2 3
08 09 0A
1
5
10 11 12
67 40 41 42 43
48 49 4A
2 3
4
4
2-line display
Fig 5.
line 2
mge992
DDRAM to display mapping: right shift
PCF2113_FAM_4
Product data sheet
line 1
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Rev. 04 — 4 March 2008
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
display
position
DDRAM
address
5
22 23 24
01 02 03 04 05
1
2 3
4
16 17 18
1-line display
1
DDRAM
address
5
10 11 12
01 02 03 04 05
2 3
0A 0B 0C
1
5
10 11 12
41 42 43 44 45
4A 4B 4C
2 3
4
4
Table 7.
line 2
mge993
2-line display
Fig 6.
line 1
DDRAM to display mapping: left shift
Address space and wrap-around operation
Mode
1 × 24
2 × 12
1 × 12
Address space
00h to 4Fh
00h to 27h; 40h to 67h
00h to 27h
Read/write wrap-around
(moves to next line)
4Fh to 00h
27h to 40h; 67h to 00h
27h to 00h
Display shift wrap-around 4Fh to 00h
(stays within line)
27h to 00h; 67h to 40h
27h to 00h
8.10 Character generator ROM
The Character Generator ROM (CGROM) generates 240 character patterns in a 5 × 8 dot
format from 8-bit character codes. Figure 7, Figure 8, Figure 9 and Figure 10 show the
character sets that are currently implemented.
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
lower
4 bits
upper
4 bits 0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
mlb245
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 7.
Character set ‘A’ in CGROM
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PCF2113x
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lower
4 bits
upper
4 bits 0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
mgd688
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 8.
Character set ‘D’ in CGROM
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
lower
4 bits
upper
4 bits 0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
mgd689
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 9.
Character set ‘E’ in CGROM
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Product data sheet
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
lower
4 bits
upper
4 bits 0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
mgu204
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 10. Character set ‘W’ in CGROM
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PCF2113x
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LCD controllers/drivers
8.11 Character generator RAM
Up to 16 user-defined characters may be stored in the Character Generator RAM
(CGRAM). Some CGRAM characters (see Figure 18 and Figure 19) are also used to drive
icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both
icon rows are used in the application; 0 if no icons are driven by the icon rows). The
CGROM and CGRAM use a common address space, of which the first column is reserved
for the CGRAM (see Figure 7, Figure 8, Figure 9 and Figure 10).
Figure 11 shows the addressing principle for the CGRAM.
character codes
(DDRAM data)
7
6
5
4
3
2
higher
order
bits
0
0
0
0
0
0
CGRAM
address
1
0
6
lower
order
bits
0
0
0
0
0
0
0
0
5
4
3
2
higher
order
bits
0
1
0
0
0
0
0
0
character patterns
(CGRAM data)
1
0
lower
order
bits
0
1
4
3
higher
order
bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
1
character code
(CGRAM data)
0
4
3
2
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
lower
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
character
pattern
example 1
character
pattern
example 2
mge995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is
performed by logic OR with the cursor. Data in the 8th position appears in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to
selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM
address’ command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be
read using the ‘read busy flag’ and ‘address counter’ command.
Fig 11. Relationship between CGRAM addresses, data and display patterns
8.12 Cursor control circuit
The cursor control circuit generates the cursor underline and/or cursor blink as shown in
Figure 12 at the DDRAM address contained in the address counter.
When the address counter contains the CGRAM address the cursor will be inhibited.
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
cursor
mga801
5 x 7 dot character font
alternating display
Cursor display example
Blink display example
Fig 12. Cursor and blink display examples
icon 1
icon 5
row 17
row 8
row 2
row 1
cursor
001aah687
Bit Q = 1
Fig 13. Example of a display with icons
8.13 Timing generator
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not disturbed by operations on the data buses.
8.14 LCD row and column drivers
The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate
LCD bias voltages in sequence to the display in accordance with the data to be displayed.
R17 and R18 drive the icon rows.
The bias voltages and the timing are selected automatically when the number of lines in
the display is selected. Figure 14, Figure 15, Figure 16 and Figure 17 show typical
waveforms. Unused outputs should be left unconnected.
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19 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n + 1
frame n
state 1 (ON)
state 2 (OFF)
VLCD
V2
R1
V3/V4
V5
VSS
ROW 1
R2
R3
R4
R5
R6
VLCD
V2
ROW 17
ROW 2
R7
R8
V3/V4
V5
VSS
R17
VLCD
V2
V3/V4
V5
VSS
VLCD
V2
V3/V4
V5
VSS
COL 1
VLCD
V2
V3/V4
V5
VSS
COL 2
Voper
0.5Voper
0.25Voper
state 1 0 V
−0.25Voper
−0.5Voper
−Voper
Voper
0.5Voper
0.25Voper
state 2 0 V
−0.25Voper
−0.5Voper
−Voper
1
2
3
9
1
2
3
9
mgu217
R9 to R16 and R18 to be left open
Fig 14. MUX 1:9 LCD waveforms; Character mode
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20 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n + 1
frame n
state 1 (ON)
state 2 (OFF)
VLCD
V2
ROW 1
R1
V3/V4
V5
VSS
R2
R3
R4
R5
R6
VLCD
V2
ROW 9
ROW 2
R7
R8
V3/V4
V5
VSS
R9
VLCD
V2
V3/V4
V5
VSS
VLCD
V2
COL 1
COL 2
V3/V4
V5
VSS
VLCD
V2
V3/V4
V5
VSS
Voper
0.5Voper
0.25Voper
state 1 0 V
−0.25Voper
−0.5Voper
−Voper
Voper
0.5Voper
0.25Voper
state 2 0 V
−0.25Voper
−0.5Voper
−Voper
1 2 3
18 1 2 3
18
mge996
Fig 15. MUX 1:18 LCD waveforms; Character mode
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Product data sheet
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21 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n + 1
frame n
only icons are
driven (MUX 1:2)
VLCD
ROW 17
2/3
1/3
VSS
VLCD
ROW 18
2/3
1/3
VSS
VLCD
ROW 1 to 16
2/3
1/3
VSS
VLCD
COL 1 ON/OFF
2/3
1/3
VSS
VLCD
COL 2 OFF/ON
2/3
1/3
VSS
VLCD
COL 3 ON/ON
2/3
1/3
VSS
VLCD
COL 4 OFF/OFF
2/3
1/3
VSS
mge997
Fig 16. MUX 1:2 LCD waveforms; Icon mode (a)
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22 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n + 1
frame n
state 1 (ON)
state 1
COL 1 −
ROW 17
Voper
2/3Voper
1/3Voper
state 2 (OFF)
R17
R18
0
R1-16
−1/3Voper
−2/3Voper
−Voper
state 3 (OFF)
Voper
state 2
COL 2 −
ROW 17
2/3Voper
1/3Voper
0
−1/3Voper
−2/3Voper
−Voper
Voper
2/3Voper
1/3Voper
state 3
COL 1 −
0
ROW 1 to 16 −1/3Voper
−2/3Voper
−Voper
mge998
Von(RMS) = 0.745Voper
Voff(RMS) = 0.333Voper
V on
D = --------- = 2.23
V off
Fig 17. MUX 1:2 LCD waveforms; Icon mode (b)
8.15 Power-down mode
The chip can be put into Power-down mode by applying an external HIGH level to the
PD pin. In Power-down mode all static currents are switched off (no internal oscillator, no
bias level generation and all LCD outputs are internally connected to VSS).
During power-down, information in the RAMs and the chip state are preserved. Instruction
execution during power-down is possible when pin OSC is externally clocked.
8.16 Reset function
The PCF2113x automatically initializes (resets) when power is turned on. The chip
executes a reset sequence, including a ‘clear display’, requiring 165 oscillator cycles. After
the reset the chip has the state shown in Table 8.
PCF2113_FAM_4
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 8.
State after reset
Step
Function
1
clear display
2
entry mode set
3
4
display control
function set
Control bit state
Conditions
I/D = 1
+1 (increment)
S=0
no shift
D=0
display off
C=0
cursor off
B=0
cursor character blink off
DL = 1
8-bit interface
M=0
1-line display
H=0
normal instruction set
SL = 0
MUX 1:18 mode
5
default address pointer the Busy Flag (BF) indicates the busy state lasts 2 ms; the chip
to DDRAM
the busy state (BF = 1) until may also be initialized by software;
initialization ends
see Table 26 (8-bit interface) and
Table 27 (4-bit interface).
6
icon control
IM = 0; IB = 0; DM = 0
icons, icon blink and Direct mode
disabled
7
display or screen
configuration
L = 0; P = 0; Q = 0
default configurations
8
VLCD temperature
coefficient
TC1 = 0; TC2 = 0
default temperature coefficient
9
set VLCD
VA = 0; VB = 0
VLCD generator off
10
I2C-bus
11
set HVgen stages
S1 = 1; S0 = 0
VLCD generator voltage multiplier
set at factor 4
interface reset
9. Instructions
Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR),
can be directly controlled by the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow interfacing to various types of
microcontrollers which operate at different speeds or to allow interfacing to peripheral
control ICs.
The instruction set for I2C-bus commands is given in Table 9. Section 11.2.1 discusses
how these control and command bytes are embedded in the I2C-bus protocol.
Table 9.
Instruction set for I2C-bus commands
I2C-bus
commands
Control byte
[1]
Co[2] RS 0
0
0
0
[1]
R/W is set together with the slave address.
[2]
For explanation, see Table 11.
0
0
Command byte
I2C-bus
commands
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
[1]
The PCF2113x operation is controlled by the instructions shown in Table 10 together with
their execution time. Details are explained in subsequent sections.
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There are 4 types of instructions:
•
•
•
•
Designate PCF2113x functions such as display format, data length
Set internal RAM addresses
Perform data transfer with internal RAM
Other functions
In normal use, data transfer instructions are used most frequently. However, automatic
incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write
lessens the microcontroller program load. The display shift in particular can be performed
concurrently with display data write, enabling the designer to develop systems in minimum
time with maximum programming efficiency.
During internal operation, no instructions other than the ‘read busy flag’ and ‘read
address’ instructions will be executed. Because the busy flag is set to logic 1 while an
instruction is being executed, check to ensure it is logic 0 before sending the next
instruction or wait for the maximum instruction execution time, as given in Table 10. An
instruction sent while the busy flag is logic 1 will not be executed.
Table 10.
Instruction set with parallel bus commands
Instruction
Control and command bits
RS
Description[1]
Required
clock
cycles
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H = 0 or 1 (basic and extended functions)
NOP
0
0
0
0
0
0
0
0
0
0
no operation
3
Function set
0
0
0
0
1
DL
0
M
SL
H
sets interface Data
Length (DL), number of
display lines (M), single
line/MUX 1:9 (SL) and
extended instruction set
control (H)
3
Read busy flag
and address
counter
0
1
BF
AC
reads the Busy Flag (BF),
indicating internal operating
is being performed, and the
Address Counter (AC)
0
Read data
1
1
read data
reads data from CGRAM or
DDRAM
3
Write data
1
0
write data
writes data to CGRAM or
DDRAM
3
H = 0 (basic functions)
Clear display
0
0
0
0
0
0
0
0
0
1
clears entire display and sets 165
DDRAM address 0 in
address counter
Return home
0
0
0
0
0
0
0
0
1
0
sets DDRAM address 0 in
address counter; also
returns shifted display to
original position; DDRAM
contents remain unchanged
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Table 10.
Instruction set with parallel bus commands …continued
Instruction
Description[1]
Control and command bits
Required
clock
cycles
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
sets cursor move direction
(I/D) and specifies shift of
display (S); these operations
are performed during data
write and read
Display control
0
0
0
0
0
0
1
D
C
B
sets entire display on/off (D), 3
cursor on/off (C) and blink of
cursor position character (B)
Cursor/display
shift
0
0
0
0
0
1
S/C
R/L
0
0
moves cursor or shifts
display (S/C) to right or left
(R/L) without changing the
DDRAM contents
Set CGRAM
address
0
0
0
1
ACG
Set DDRAM
address
0
0
1
ADD
3
3
sets CGRAM address;
bit DB6 is to be set by the
command ‘set DDRAM
address’; the descriptions of
the commands provide
details
sets DDRAM address
3
H = 1 (extended functions)
Reserved
0
0
0
0
0
0
0
0
0
1
do not use
-
Screen
configuration
0
0
0
0
0
0
0
0
1
L
set screen configuration (L)
3
Display
configuration
0
0
0
0
0
0
0
1
P
Q
set display configuration,
columns (P) and rows (Q)
3
Icon control
0
0
0
0
0
0
1
IM
IB
DM
set Icon mode (IM), icon
blink (IB), Direct mode (DM)
3
Temperature
control
0
0
0
0
0
1
0
0
TC1 TC2 set temperature coefficient
(TC1 and TC2)
3
Set HVgen
stages
0
0
0
1
0
0
0
0
S1
set internal VLCD generator
voltage multiplier stages
(S1 = 1 and S0 = 1 are not
allowed)
3
Set VLCD
0
0
1
V
voltage
store VLCD in register VA or
in register VB (V)
3
[1]
S0
For explanation of symbols, see Table 11.
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Table 11.
Explanation of symbols
Bit
Logic 0
Logic 1
Co
last control byte
another control byte follows after
data/command
RS
select instruction register
select data register
DL
data length: 4 bits
data length: 8 bits
M (no impact if SL = 1)
1 line × 24 character display
2 line × 12 character display
SL
MUX 1:18 (1 line × 24 character
or 2 line × 12 character display)
MUX 1:9 (1 line × 12 character
display)
H
use basic instruction set
use extended instruction set
I/D
decrement
increment
S
display freeze
display shift
D
display off
display on
C
cursor off
cursor on
B
cursor character blink off;
character at cursor position does
not blink
cursor character blink on;
character at cursor position blinks
S/C
cursor move
display shift
R/L
left shift
right shift
L (no impact if M = 1 or
SL = 1)
left/right screen;
standard connection
left/right screen;
mirrored connection
1st 12 characters of 24;
columns are from 1 to 60
1st 12 characters of 24;
columns are from 60 to 1
2nd 12 characters of 24;
columns are from 1 to 60
2nd 12 characters of 24;
columns are from 60 to 1
P
column data; left to right; column
data is displayed from 1 to 60
column data; right to left; column
data is displayed from 60 to 1
Q
row data; top to bottom; row data row data; top to bottom; row data
is displayed from 1 to 16 and icon is displayed from 16 to 1 and icon
row data is in 17 and 18
row data is in 18 and 17
IM
Character mode; full display
Icon mode; only icons displayed
IB
icon blink disabled
icon blink enabled
DM
Direct mode disabled
Direct mode enabled
V
set VA
set VB
9.1 Clear display
‘Clear display’ writes character code 20h into all DDRAM addresses (the character pattern
for character code 20h must be a blank pattern), sets the DDRAM address counter to 0
and returns the display to its original position, if it was shifted. Thus, the display
disappears and the cursor or blink position goes to the left edge of the display. Sets entry
mode I/D = 1 (increment mode). S of entry mode does not change.
The instruction ‘clear display’ requires extra execution time. This may be allowed by
checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are foreseen, as in some
Chip-On-Glass (COG) applications.
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9.2 Return home
‘Return home’ sets the DDRAM address counter to 0 and returns the display to its original
position if it was shifted. DDRAM contents do not change. The cursor or blink position
goes to the left of the first display line. I/D and S of entry mode do not change.
9.3 Entry mode set
9.3.1 Bit I/D
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when
data is written into or read from the DDRAM or CGRAM. The cursor or blink position
moves to the right when incremented and to the left when decremented. The cursor
underline and cursor character blink are inhibited when the CGRAM is accessed.
9.3.2 Bit S
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1)
during a DDRAM write. Thus it appears as if the cursor stands still and the display moves.
The display does not shift when reading from the DDRAM, or when writing to or reading
from the CGRAM.
When S = 0, the display does not shift.
9.4 Display control (and partial Power-down mode)
9.4.1 Bit D
The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not
affected and can be displayed immediately by setting D = 1.
When the display is off (D = 0) the chip is in partial Power-down mode:
• The LCD outputs are connected to VSS
• The LCD generator and bias generator are turned off
Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all
outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running
during partial Power-down mode (‘display off’) the chip can still execute instructions. Even
lower current consumption is obtained by inhibiting the oscillator (pin OSC = VSS).
To ensure IDD < 1 µA, pin PD and the parallel bus pins DB7 to DB0 should be connected
to VDD, pins RS and R/W to VDD or left open-circuit.
Recovery from Power-down mode: connect pin PD back to VSS, if necessary pin OSC
back to VDD and send a ‘display control’ instruction with D = 1.
9.4.2 Bit C
The cursor is displayed when C = 1 and inhibited when C = 0. The cursor is displayed
using 5 dots in the 8th line (see Figure 12). Even if the cursor disappears, the display
functions like I/D, remain in operation during display data write.
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9.4.3 Bit B
The character indicated by the cursor blinks when B = 1. The cursor character blink is
displayed by switching between display characters and all dots on with a period of
f osc
approximately 1 s, with f blink = ----------------- Hz.
104448
The cursor underline and the cursor character blink can be set to display simultaneously.
9.5 Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the display to the right or left without
writing or reading display data. This function is used to correct a character or move the
cursor through the display. In 2-line displays, the cursor moves to the next line when it
passes the last position of the line. When the displayed data is shifted repeatedly all lines
shift at the same time; displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the only action performed is shift
display, but increments or decrements with the ‘cursor display shift’.
9.6 Function set
9.6.1 Bit DL (parallel mode only)
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or
in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should
be left open-circuit (internal pull-ups). Hence in the first ‘function set’ instruction after
power-on M, SL and H are set to logic 1. A second ‘function set’ must then be sent
(2 nibbles) to set M, SL and H to their required values.
‘Function set’ from the I2C-bus interface sets the DL bit to logic 1.
9.6.2 Bit M
Selects either 1 line × 24 character display (M = 0) or 2 line × 12 character display (M = 1).
9.6.3 Bit SL
Selects MUX 1:9, 1 line × 12 character display (independent of M and L). Only rows 1 to 8
and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the
same as in the 2 line × 12 character display mode, however, the second line is not
displayed.
9.6.4 Bit H
When H = 0 the chip can be programmed via the standard 11 instruction codes used in
the PCF2116 and other LCD controllers.
When H = 1 the extended range of instructions will be used. These are mainly for
controlling the display configuration and the icons, as shown in Section 10.
9.7 Set CGRAM address
‘Set CGRAM address’ writes bits DB5 to DB0 of the CGRAM address ACG into the
address counter (A5h to A0h). Data can then be written to or read from the CGRAM.
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Remark: the CGRAM address uses the same address register as the DDRAM address
and consists of 7 bits (A6h to A0h). With the ‘set CGRAM address’ command, only
bits DB5 to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command
first, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can
be read using the ‘read busy flag’ and ‘read address’ command.
When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not
set (e.g. by an earlier DDRAM write or read action).
9.8 Set DDRAM address
‘Set DDRAM address’ writes the DDRAM address ADD into the address counter
(A6h to A0h). Data can then be written to or read from the DDRAM.
9.9 Read busy flag and read address
‘Read busy flag and address counter’ reads the Busy Flag (BF) and Address
Counter (AC). BF = 1 indicates that an internal operation is in progress. The next
instruction will not be executed until BF = 0. It is recommended that the BF status is
checked before the next write operation is executed.
At the same time, the value of the address counter (A6h to A0h) is read out, into DB6 to
DB0. The address counter is used by both CGRAM and DDRAM, and its value is
determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set
CGRAM address’ or ‘set DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in accordance with the entry mode. Only
bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are ‘not relevant’.
9.11 Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM.
The most recent ‘set address’ command determines whether the CGRAM or DDRAM is to
be read.
The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while
pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC into the DR.
There are only three instructions that update the DR:
• ‘Set CGRAM address’
• ‘Set DDRAM address’
• ‘Read data’ from CGRAM or DDRAM
Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’)
do not modify the data register content.
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10. Extended function set instructions and features
10.1 New instructions
H = 1 sets the chip into Extended instruction set mode.
10.2 Icon control
The PCF2113x can drive up to 120 icons. See Figure 18 and Figure 19 for CGRAM to
icon mapping.
display:
COL 1 to 5
COL 6 to 10
ROW 17 –
1
ROW 18 –
61 62 63 64 65
2
3
4
5
6
7
8
9
COL 56 to 60
10
56 57 58 59 60
66 67 68 69 70
116 117 118 119 120
mge999
block of 5 columns
Fig 18. CGRAM to icon mapping (a)
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icon no.
phase
ROW/COL
character codes
7
6
5
4
3
2
CGRAM address
1
MSB
0
6
LSB
MSB
5
4
3
2
1
CGRAM data
0
4
3
2
1
icon view
0
LSB
LSB MSB
1-5
even
17/1-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
6-10
even
17/6-10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
11-15
even
17/11-15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
56-60
even
17/56-60
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
61-65
even
18/1-5
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
116-120
even
18/56-60
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
1-5
odd (blink)
17/1-5
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
mgg001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.
Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is
enabled.
Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when
icon blink is disabled).
Fig 19. CGRAM to icon mapping (b)
10.3 Bit IM
When IM = 0, the chip is in Character mode. In Character mode, characters and icons are
driven (MUX 1:18 or MUX 1:9). The VLCD generator, if used, produces the VLCD voltage
programmed in register VA.
When IM = 1, the chip is in Icon mode. In Icon mode only the icons are driven (MUX 1:2)
and the VLCD generator, if used, produces the VLCD voltage as programmed in register VB.
Table 12.
Character/Icon mode operation
IM
Mode
VLCD
0
Character mode
defined in VA
1
Icon mode
defined in VB
10.4 Bit IB
Icon blink control is independent of the cursor/character blink function.
When IB = 0, the icon blink is disabled. Icon data is stored in CGRAM characters 0 to 2
(3 × 8 × 5 = 120 bits for 120 icons).
When IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits.
Blink consists of two half phases (corresponding to the cursor on and off phases called
even and odd phases hereafter).
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Icon states for the even phase are stored in CGRAM characters 0 to 2
(3 × 8 × 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not
used (see Table 13).
Icon states for the odd phase are stored in CGRAM characters 4 to 6 (another 120 bits for
the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as
normal CGRAM characters.
Table 13.
Blink effect for icons and cursor character blink
Parameter
Even phase
Odd phase
Cursor character blink
block (all on)
normal (display character)
Icons
state 1; CGRAM character 0 to 2
state 2; CGRAM character 4 to 6
10.5 Direct mode
When DM = 0, the chip is not in the Direct mode. Either the internal VLCD generator or an
external voltage may be used to achieve VLCD.
When DM = 1, the chip is in Direct mode. The internal VLCD generator is turned off and the
output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage).
The Direct mode can be used to reduce the current consumption when the required
output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in Icon
mode or in MUX 1:9 (depending on LCD liquid properties).
10.6 Voltage multiplier control
10.6.1 Bits S1 and S0
A software configurable voltage multiplier is incorporated in the VLCD generator and can
be set via the ‘Set HVgen stages’ command.
The voltage multiplier control can be used to reduce current consumption by
disconnecting internal voltage multiplier stages, depending on the required output voltage
VLCD (see Table 14).
Table 14.
S1
S1 and S0 control of voltage multiplier
S0
Description
0
0
set VLCD generator stages to 1 (2 × voltage multiplier)
0
1
set VLCD generator stages to 2 (3 × voltage multiplier)
1
0
set VLCD generator stages to 3 (4 × voltage multiplier)
1
1
do not use
10.7 Screen configuration
10.7.1 Bit L
L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61,
2/62 to 60/120; default.
L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120,
2/119 to 60/61. This allows single layer PCB or glass layout.
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10.8 Display configuration
10.8.1 Bit P
The P bit is used to flip the display left to right by mirroring the column data, as shown in
Figure 20. This allows the display to be viewed from behind instead of front, enhances the
flexibility in the assembly of equipment and avoids complicated data manipulation within
the controller.
P = 0: default.
P = 1: mirrors the column data.
0
P= =P
1
P
0= =1
P
001aah714
Fig 20. Use of P bit
10.8.2 Bit Q
The Q bit flips the display top to bottom by mirroring the row data.
Q = 0: default.
Q = 1: mirrors the row data.
A combination of Q and P allows the display to be rotated 180 deg, as shown in Figure 21.
This is useful for viewing the display from the opposite edge.
P=0
Q=0
P=1
Q=1
001aah715
Fig 21. Use of P and Q bits
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10.9 Temperature control
Default is bit TC1 = 0 and bit TC2 = 0. Selects the default temperature coefficient for the
internally generated VLCD (see Table 15).
Table 15.
TC1 and TC2 selection of VLCD temperature coefficient
Bit TC1
Bit TC2
VLCD temperature coefficient TC (typical values)
0
0
TC = −0.16 %/K
1
0
TC = −0.18 %/K
0
1
TC = −0.21 %/K
1
1
TC = −0.24 %/K
10.10 Set VLCD
The VLCD value is programmed by instruction. Two on-chip registers, VA and VB hold VLCD
values for the Character mode and the Icon mode respectively. The generated VLCD is
independent of VDD, allowing battery operation of the chip.
10.10.1 VLCD programming
1. Send ‘function set’ instruction with H = 1
2. Send ‘set VLCD’ instruction to write to voltage register:
a. If DB[7:6] = 10, then DB[5:0] represents VLCD of Character mode (VA)
b. If DB[7:6] = 11, then DB[5:0] represents VLCD of Icon mode (VB)
c. DB[5:0] = 00 0000 switches VLCD generator off (when selected)
d. During ‘display off’ and power-down the VLCD generator is also disabled
3. Send ‘function set’ instruction with H = 0 to resume normal programming
Section 8.1 shows the relation between VLCD and registers VA and VB.
10.11 Reducing current consumption
Reducing current consumption can be achieved by one of the options given in Table 16.
When VLCD lies outside the VDD range and must be generated, it is usually more efficient
to use the on-chip generator than an external regulator.
Table 16.
Reducing current consumption
Original mode
Alternative mode
Character mode
Icon mode (control bit M)
Display on
display off (control bit D)
VLCD generator operating
Direct mode
Any mode
Power-down mode (PD pin)
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11. Interfaces to microcontroller
11.1 Parallel interface
The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can
thus interface to 4-bit or 8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three
further control lines E, RS and R/W are required (see Section 7).
In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the
transaction. The higher order bits (corresponding to bits DB7 to DB4 in 8-bit mode) are
sent in the first cycle and the lower order bits (corresponding to bits DB3 to DB0 in 8-bit
mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It
should be noted that two cycles are also required for the busy flag check. 4-bit operation is
selected by instruction: see Figure 22, Figure 23 and Figure 24 for examples of bus
protocol.
In 4-bit mode, pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD
internally.
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
instruction
write
busy flag and
address counter read
data register
read
mga804
Fig 22. 4-bit transfer example
PCF2113_FAM_4
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
instruction
write
not
busy
AC3
busy flag
check
AC3
D7
busy flag
check
D3
instruction
write
mga805
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
Fig 23. Example of 4-bit data transfer timing sequence
RS
R/W
E
internal
internal operation
data
DB7
instruction
write
busy
busy
busy flag
check
busy flag
check
not
busy
busy flag
check
data
instruction
write
mga806
Fig 24. Example of busy flag checking timing sequence
11.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH
level signal put on the bus by the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte.
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
11.2.1 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the START procedure. The I2C-bus configuration for the different PCF2113x read and
write cycles is shown in Figure 25, Figure 26 and Figure 27. The slow-down feature of the
I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the
PCF2113x.
acknowledgement
from PCF2113x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
A P
0
slave address
R/W
Co
2n ≥ 0 bytes
1 byte
Co
n ≥ 0 bytes
update
data pointer
mgg002
S
0 1 1 1 0 1 A 0
0
PCF2113x
slave address
R/W
Fig 25. Master transmits to slave receiver; write mode
PCF2113_FAM_4
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
acknowledgement
S
S 0 1 1 1 0 1 A 0 A 1 RSCONTROL BYTE A
DATA BYTE
DATA BYTE(1)
A 0 RSCONTROL BYTE A
A
0
2n ≥ 0 bytes
slave address
Co
acknowledgement
S
n ≥ 0 bytes
1 byte
R/W Co
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
DATA BYTE
1 P
DATA BYTE
A
n bytes
R/W Co
no acknowledgement
last byte
update
data pointer
update
data pointer
mgg003
(1) Last data byte is a dummy byte (may be omitted).
Fig 26. Master reads after setting word address; write word address; set RS; ‘read data’
acknowledgement
from PCF2113x
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
from master
DATA BYTE
A
n bytes
R/W Co
no acknowledgement
from master
DATA BYTE
1 P
last byte
update
data pointer
update
data pointer
mgg004
Fig 27. Master reads slave immediately after first byte; read mode (RS previously defined)
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Fig 28. System configuration
PCF2113_FAM_4
Product data sheet
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39 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 29. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 30. Definition of START and STOP conditions
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 31. Acknowledgement on the I2C-bus
11.2.2 Definitions
•
•
•
•
•
Transmitter: the device that sends the data to the bus
Receiver: the device that receives the data from the bus
Master: the device that initiates and terminates a transfer and generates clock signals
Slave: the device addressed by a master
Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message
• Arbitration: procedure to ensure that if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock signals of two or more devices
PCF2113_FAM_4
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
12. Internal circuitry
Table 17.
Device protection circuits
Symbol
Pad
VDD1
1
Internal circuit
VDD1
VSS1
mgu200
VDD2
109
VDD2
VSS1
VSS2
mgu201
VDD3
110
VDD3
VSS1
mgu202
VSS1
7
VSS2
8
VSS2
VSS1
mgu203
VLCDSENSE
10
VLCDIN
11
VLCDOUT
9
VSS1
mgu196
SCL
96
SDA
97
VDD1
VSS1
mgu198
PCF2113_FAM_4
Product data sheet
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41 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 17.
Device protection circuits …continued
Symbol
Pad
OSC
2
Internal circuit
PD
3
T1
5
T2
6
T3
4
E
98
VSS1
RS
99
mgu199
R/W
100
DB0 to DB7
108 to 101
R1 to R8
94 to 87
R9 to R16
12 to 19
R17
95
R18
20
C1 to C2
86 to 85
C3 to C27
82 to 58
VSS1
C28 to C52
55 to 31
mgu197
C53 to C60
28 to 21
VDD1
VLCDOUT
13. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD1
supply voltage 1
logic supply
−0.5
+5.5
V
VDD2
supply voltage 2
VLCD generator supply
−0.5
+4.0
V
VDD3
supply voltage 3
analog supply
−0.5
+4.0
V
VLCD
LCD supply voltage
−0.5
+6.5
V
Vi(n)
voltage on any input
VDD related inputs
−0.5
+5.5
V
Vo(n)
voltage on any output
VLCD related outputs
−0.5
+6.5
V
II
input current
DC level
−10
+10
mA
IO
output current
DC level
−10
+10
mA
IDD
supply current
on pins VDD1, VDD2, VDD3
-
+50
mA
ISS
ground supply current
on pins VSS1 and VSS2
-
−50
mA
IDD(LCD)
LCD supply current
-
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
Vesd
electrostatic discharge
voltage
Ilu
latch-up current
Tstg
storage temperature
-
100
mW
HBM
[1]
-
±2000
V
MM
[2]
-
±200
V
CDM
[3]
-
±2000
V
PCF2113_FAM_4
Product data sheet
[4]
-
100
mA
−65
+150
°C
© NXP B.V. 2008. All rights reserved.
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42 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
[1]
HBM: Human Body Model, according to JESD22-A114.
[2]
MM: Machine Model, according to JESD22-A115.
[3]
CDM: Charged-Device Model, according to JESD22-C101.
[4]
Latch-up testing, according to JESD78.
14. Static characteristics
Table 19. Static characteristics
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD1
supply voltage 1
logic supply
1.8
-
5.5
V
VDD2
supply voltage 2
VLCD generator supply;
internal VLCD generation
(VDD2 and VDD3 < VLCD)
2.2
-
4.0
V
VDD3
supply voltage 3
analog supply;
internal VLCD generation
(VDD2 and VDD3 < VLCD)
2.2
-
4.0
V
VLCD
LCD supply voltage
2.2
-
6.5
V
0.9
-
1.6
V
-
70
120
µA
Supplies
VPOR
ISS
[1][2]
power-on reset voltage
ground supply current
[1]
external VLCD; pins VSS1 and VSS2
[3]
Character mode; VLCD = 6.5 V;
VDD1 = 5.5 V; VDD2 = VDD3 = 4 V
Character mode; VLCD = 5 V;
VDD1 = VDD2 = VDD3 = 3 V
[4]
-
45
80
µA
Icon mode; VLCD = 2.5 V;
VDD1 = VDD2 = VDD3 = 3 V
[4]
-
25
45
µA
-
190
400
µA
internal VLCD; pins VSS1 and VSS2
[3][5]
Character mode; VLCD = 6.5 V;
VDD1 = 5.5 V; VDD2 = VDD3 = 2.2 V
Character mode; VLCD = 5 V;
VDD1 = VDD2 = VDD3 = 3 V
[4]
-
160
400
µA
Icon mode; VLCD = 2.5 V;
VDD1 = VDD2 = VDD3 = 2.5 V
[4]
-
120
-
µA
[3][4]
-
2
5
µA
Power-down mode; VLCD = 2.5 V;
VDD1 = VDD2 = VDD3 = 3 V;
pins RS, PD, R/W and DB7 to
DB0 = HIGH; in OSC = LOW
Logic
Vi
input voltage
VSS1 − 0.5 -
VDD1 + 0.5 V
VIL
LOW-level input voltage on pin OSC
VSS1
-
VDD1 − 1.2 V
on any other pin
VSS1
-
0.3VDD1
V
VIH
HIGH-level input
voltage
on pin OSC
VDD1 − 0.1 -
VDD1
V
on any other pin
0.7VDD1
-
VDD1
V
leakage current
VI = VDD1 or VSS1
−1
-
+1
µA
IL
PCF2113_FAM_4
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 19. Static characteristics …continued
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pins DB7 to DB0
IOL
LOW-level output
current
VOL = 0.4 V; VDD1 = 5 V
1.6
4
-
mA
IOH
HIGH-level output
current
VOH = 0.4 V; VDD1 = 5 V
−1
−8
-
mA
Ipu
pull-up current
VI = VSS1
0.04
0.15
1
µA
I2C-bus
Input on pins SDA and SCL
VI
input voltage
VSS1 − 0.5 -
5.5
V
VIL
LOW-level input voltage
0
-
0.3VDD1
V
VIH
HIGH-level input
voltage
0.7VDD1
-
5.5
V
ILI
input leakage current
−1
-
+1
µA
-
5
-
pF
VI = VDD1 or VSS1
[6]
input capacitance
CI
Output on pin SDA
IOL(SDA)
LOW-level output
current on pin SDA
VOL = 0.4 V; VDD1 > 2 V
3
-
-
mA
VOL = 0.2VDD1; VDD1 < 2 V
2
-
-
mA
output resistance
row outputs: pins R1 to R18
[7]
-
10
30
kΩ
column outputs: pins C1 to C60
[7]
-
15
40
kΩ
bias voltage variation
pins R1 to R18 and C1 to C60
[8]
-
20
130
mV
LCD voltage variation
Tamb = 25 °C
[5]
VLCD < 3 V
-
-
160
mV
VLCD < 4 V
-
-
200
mV
VLCD < 5 V
-
-
260
mV
VLCD < 6 V
-
-
340
mV
LCD outputs
RO
∆Vbias
∆VLCD
[1]
Spikes on VDD1 or VSS1 which cause (VDD1 − VSS1) ≤ 1.6 V can cause a Power-on reset.
[2]
Resets all logic when VDD1 < VPOR; 3 oscillator cycles required.
[3]
LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive.
[4]
Tamb = 25 °C; fosc = 200 kHz.
[5]
LCD outputs are open-circuit; VLCD generator is on; load current IDD(LCD) = 5 µA (at VLCD).
[6]
Tested on a sample basis.
[7]
Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 µA; outputs measured one at a time; external VLCD = 3 V;
VDD1 = VDD2 = VDD3 = VLCD.
[8]
LCD outputs are open-circuit; external VLCD.
PCF2113_FAM_4
Product data sheet
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44 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
15. Dynamic characteristics
Table 20. Dynamic characteristics
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified
Symbol
Parameter
Conditions
internal clock; VDD = 5.0 V
ffr(LCD)
LCD frame frequency
fosc
oscillator frequency
fosc(ext)
external oscillator frequency
[1]
td(startup)(OSC)
start-up delay time on pin OSC
tw(pd)
power-down pulse width
tw(spike)
spike pulse width
Timing characteristics of parallel interface
Min
Typ
Max
Unit
45
95
147
Hz
140
250
450
kHz
140
-
450
kHz
oscillator, after power down
[2]
-
200
300
µs
1
-
-
µs
on pin PD
[2]
-
-
90
ns
[3]
Write operation (writing data from microcontroller to PCF2113x); see Figure 32
tcy(en)
enable cycle time
500
-
-
ns
tw(en)
enable pulse width
220
-
-
ns
tsu(A)
address set-up time
50
-
-
ns
th(A)
address hold time
25
-
-
ns
tsu(D)
data input set-up time
60
-
-
ns
th(D)
data input hold time
25
-
-
ns
Read operation (reading data from PCF2113x to microcontroller); see Figure 33
tcy(en)
enable cycle time
500
-
-
ns
tw(en)
enable pulse width
220
-
-
ns
tsu(A)
address set-up time
50
-
-
ns
th(A)
address hold time
25
-
-
ns
td(DV)
data input valid delay time
VDD1 > 2.2 V
-
-
150
ns
VDD1 > 1.5 V
-
-
250
ns
th(D)
data input hold time
5
-
-
ns
-
-
400
Hz
Timing characteristics of
I2C-bus
fSCL
SCL frequency
interface
[3];
see Figure 34
tLOW
LOW period of the SCL clock
1.3
-
-
µs
tHIGH
HIGH period of the SCL clock
0.6
-
-
µs
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
15 + 0.1Cb
-
300
ns
15 + 0.1Cb
-
300
ns
tr
rise time of both SDA and SCL
signals
[2][4]
tf
fall time of both SDA and SCL
signals
[2][4]
Cb
capacitive load for each bus line
-
-
400
pF
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
µs
tHD;STA
hold time (repeated) START
condition
0.6
-
-
µs
[4]
PCF2113_FAM_4
Product data sheet
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45 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 20. Dynamic characteristics …continued
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified
Symbol
Parameter
tSU;STO
Conditions
Min
Typ
Max
Unit
set-up time for STOP condition
0.6
-
-
µs
tSP
pulse width of spikes that must on bus
be suppressed by the input filter
-
-
50
ns
tBUF
bus free time between a STOP
and START condition
1.3
-
-
µs
[1]
Not available at any pin.
[2]
Tested on a sample basis.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[4]
Cb = total capacitance of one bus line in pF.
RS
VIH
VIL
VIH
VIL
tsu(A)
R/W
th(A)
VIL
VIL
tw(en)
E
VIH
th(A)
VIH
VIL
VIL
VIL
th(D)
tsu(D)
VIH
valid data
VIL
DB0 to DB7
VIH
VIL
mbk474
tcy(en)
Fig 32. Parallel bus write operation sequence; writing data from microcontroller to
PCF2113x
RS
VIH
VIL
VIH
VIL
tsu(A)
R/W
th(A)
VIH
VIH
tw(en)
VIH
E
th(A)
VIH
VIL
VIL
th(D)
td(DV)
VOH
VOL
DB0 to DB7
VIL
VOH
VOL
mbk475
tcy(en)
Fig 33. Parallel bus read operation sequence; writing data from PCF2113x to
microcontroller
PCF2113_FAM_4
Product data sheet
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PCF2113x
NXP Semiconductors
LCD controllers/drivers
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
t SU;STA
t SU;STO
mga728
Fig 34. I2C-bus timing diagram
16. Application information
16.1 Application diagrams
P80CL51
P10
RS
P11
R/W
P12
E
P17 to P14
4
PCF2113x
DB7 to DB4
R17, R18
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
16
C1 to C60
60
mgg006
Fig 35. Direct connection to 8-bit microcontroller; 4-bit bus
P80CL51
P20
RS
P21
R/W
P22
E
P17 to P10
8
PCF2113x
DB7 to DB0
R17, R18
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
16
C1 to C60
60
mgg005
Fig 36. Direct connection to 8-bit microcontroller; 8-bit bus
PCF2113_FAM_4
Product data sheet
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47 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
R17, R18
OSC
VDD
2
VDD
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
PCF2113x
470
nF
16
VLCD
100
nF
VSS
C1 to C60
60
VSS
8
DB7 to DB0 E
mgg007
RS R/W
Fig 37. Typical application using parallel interface
VDD VDD
VDD
OSC
VDD
DB3/SA0
R17, R18
VDD
R1 to R16
PCF2113x
470
nF
16
VLCD
100
nF
VSS
VSS
2
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
C1 to C60
60
R17, R18
2
SCL SDA
VSS
OSC
VDD
DB3/SA0
VDD
R1 to R16
PCF2113x
470
nF
VLCD
100
nF
VSS
SCL SDA
16
C1 to C60
VSS
1 × 24 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
60
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
mgg008
Fig 38. Application using I2C-bus interface
PCF2113_FAM_4
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48 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
16.2 General application information
The required minimum value for the external capacitors in an application with the
PCF2113x are: Cext ≥ 100 nF between VLCD and VSS, and Cext ≥ 470 nF between VDD and
VSS. Higher capacitor values are recommended for ripple reduction.
For COG applications the recommended Indium Tin Oxide (ITO) track resistance is to be
minimized for the I/O and supply connections. Optimized values for these tracks are below
50 Ω for the supply and below 100 Ω for the I/O connections. Higher track resistances
reduce performance and increase current consumption.
To avoid accidental triggering of power-on reset (especially in COG applications), the
supplies must be adequately decoupled. Depending on power supply quality, VDD1 may
have to be risen above the specified minimum.
16.3 4-bit operation, 1-line display using internal reset
The program must set functions prior to a 4-bit operation (see Table 21 ). When power is
turned on, 8-bit operation is automatically selected and the PCF2113x attempts to
perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a
rewrite is then required. However, since one operation is completed in two accesses of
4-bit operation, a rewrite is required to set the functions (see Table 21 step 3). Thus,
DB4 to DB7 of the ‘function set’ are written twice.
Table 21.
4-bit operation, 1-line display example using internal reset
Step
Instruction
1
internal power supply on (PCF2113x
is initialized by the internal reset)
initialized; no display appears
2
function set
sets a 4-bit operation; in this instance
operation is handled as 8-bit by
initialization and only this instruction
completes with one write
3
4
5
6
Display
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
0
function set
Operation
0
0
0
0
1
0
0
0
0
0
0
0
sets to 4-bit operation, selects 1-line
display and VLCD = VA; 4-bit operation
starts from this point and resetting is
needed
turns on display and cursor; entire
display is blank after initialization
display control
0
0
0
0
0
0
0
0
1
1
1
0
entry mode set
0
0
0
0
0
0
0
0
0
1
1
0
sets mode to increment address by 1
and to shift the cursor to the right at the
time of write to the DDRAM/CGRAM;
display is not shifted
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
1
0
0
0
0
0
P
writes ’P’; the DDRAM has already
been selected by initialization at
power-on; the cursor is incremented by
1 and shifted to the right
16.4 8-bit operation, 1-line display using internal reset
Table 22 and Table 23 show an example of a 1-line display in 8-bit operation. The
PCF2113x functions must be set by the ‘function set’ instruction prior to display. Since the
DDRAM can store data for 80 characters, the RAM can be used for advertising displays
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
49 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
when combined with display shift operation. Since the display shift operation changes
display position only and the DDRAM contents remain unchanged, display data entered
first can be displayed when the ‘return home’ operation is performed.
Table 22.
Step
8-bit operation, 1-line display example; using internal reset (character set ‘A’)
Instruction
RS
Display
Operation
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
power supply on (PCF2113x is initialized by the internal
reset)
initialized; no display appears
2
function set
0
sets to 8-bit operation, selects 1-line
display and VLCD = VA
0
turns on display and cursor; entire
display is blank after initialization
0
0
0
3
display control
4
entry mode set
0
0
5
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
1
sets mode to increment the address
by 1 and to shift the cursor to the
right at the time of the write to the
DDRAM/CGRAM; display is not
shifted
0
‘write data’ to CGRAM/DDRAM
1
6
0
0
0
0
1
0
1
0
0
0
0
P
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
7 to 10
writes ‘P’; the DDRAM has already
been selected by initialization at
power-on; the cursor is incremented
by 1 and shifted to the right
writes ‘H’
0
1
0
0
0
PH
:
writes ‘ILIP’
:
11
‘write data’ to CGRAM/DDRAM
1
12
1
0
1
0
0
1
1
PHILIPS
0
0
0
0
0
0
1
1
1
PHILIPS
‘write data’ to CGRAM/DDRAM
1
14
0
entry mode set
0
13
0
writes ‘S’
0
0
0
1
writes space
0
0
0
0
0
HILIPS
0
1
1
0
1
HILIPS M
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
15 to 19
sets mode for display shift at time of
write
writes ‘M’
:
writes ‘ICROK’
:
20
‘write data’ to CGRAM/DDRAM
1
21
0
writes ‘O’
0
1
1
1
1
MICROKO
0
0
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the
left
0
0
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the
left
‘write data’ to CGRAM/DDRAM
1
24
1
cursor/display shift
0
23
0
cursor/display shift
0
22
0
0
0
1
0
0
0
0
1
1
ICROCO
writes ‘C’ correction; the display
moves to the left
0
0
1
1
1
0
0
MICROCO
shifts the display and cursor to the
right
cursor/display shift
0
0
0
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
50 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 22.
Step
8-bit operation, 1-line display example; using internal reset (character set ‘A’) …continued
Instruction
RS
25
cursor/display shift
0
26
0
0
Table 23.
Step
0
0
0
1
0
1
0
0
MICROCO
0
1
0
0
1
1
0
1
ICROCOM
writes ‘M’
return home
0
Operation
shifts only the cursor to the right
‘write data’ to CGRAM/DDRAM
1
27
Display
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
0
PHILIPS M
returns both display and cursor to
the original position (address 0)
8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)
Instruction
RS
R/W
Display
Operation
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
power supply on (PCF2113x is initialized by the internal reset)
initialized; no display appears
2
function set
0
sets to 8-bit operation, selects 1-line
display and VLCD = VA
turns on display and cursor; entire
display is blank after initialization
0
3
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
set CGRAM address
0
6
0
entry mode set
0
5
0
display control
0
4
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
7
sets mode to increment the address
by 1 and to shift the cursor to the
right at the time of the write to the
DDRAM/CGRAM; display is not
shifted
sets the CGRAM address to
position of character ‘0’; the
CGRAM is selected
writes data to CGRAM for icon even
phase; icon appears
:
:
8
sets CGRAM address
0
9
0
0
1
1
1
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
10
0
1
0
1
0
sets the CGRAM address to
position of character ‘0’; the
CGRAM is selected
writes data to CGRAM for icon odd
phase
:
:
11
function set
12
icon control
0
0
0
0
sets H = 1: Extended instruction set
0
0
0
0
function set
14
set DDRAM address
0
0
0
1
0
0
0
1
icons blink
13
0
1
0
0
1
0
1
0
sets H = 0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
PCF2113_FAM_4
Product data sheet
sets the DDRAM to the first position;
DDRAM is selected
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
51 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 23.
Step
8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’) …continued
Instruction
RS
15
Display
Operation
writes ‘P’; the cursor is incremented
by 1 and shifted to the right
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
‘write data’ to CGRAM/DDRAM
1
16
R/W
0
0
1
0
1
0
0
0
0
P
0
1
0
0
0
PH
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
17
writes ‘H’
:
writes ‘ILIPS’
:
22
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
returns both display and cursor to
the original position (address 0)
16.5 8-bit operation, 2-line display
For a 2-line display the cursor automatically moves from the first to the second line after
the 40th digit of the first line has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the 8th character is completed (see
Table 24). It should be noted that both lines of the display are always shifted together;
data does not shift from one line to the other.
Table 24.
Step
8-bit operation, 2-line display example; using internal reset
Instruction
RS
1
2
function set
sets to 8-bit operation, selects
1-line display and VLCD = VA
0
0
0
1
1
0
1
0
0
display control
0
0
0
0
0
1
1
1
turns on display and cursor;
entire display is blank after
initialization
0
entry mode set
0
5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
initialized; no display appears
0
4
Operation
power supply on (PCF2113x is initialized by the internal reset)
0
3
R/W
Display
0
0
0
0
0
0
1
1
sets mode to increment the
address by 1 and to shift the
cursor to the right at the time of
the write to the DDRAM/CGRAM;
display is not shifted
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
6 to 10
1
0
0
0
0
P
:
writes ‘P’; the DDRAM has
already been selected by
initialization at power-on; the
cursor is incremented by 1 and
shifted to the right
writes ‘HILIP’
:
11
‘write data’ to CGRAM/DDRAM
1
12
0
0
1
0
writes ‘S’
1
0
0
1
1
PHILIPS
sets DDRAM address
0
0
1
1
0
0
0
0
0
0
PCF2113_FAM_4
Product data sheet
PHILIPS
sets DDRAM to position the
cursor at the start of the 2nd line
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
52 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 24.
Step
8-bit operation, 2-line display example; using internal reset …continued
Instruction
RS
13
R/W
Display
Operation
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
writes ‘M’
0
1
1
0
1
PHILIPS
M
14 to 18
:
writes ‘ICROC’
:
19
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
writes ‘O’
0
1
1
1
1
PHILIPS
MICROCO
20
entry mode set
0
0
0
0
0
0
0
1
1
1
sets mode for display shift at the
time of write
PHILIPS
MICROCO
21
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
1
1
0
1
writes ‘M’; display is shifted to the
left; the 1st and 2nd lines shift
together
HILIPS
ICROCOM
22
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
MICROCOM
returns both the display and
cursor to the original position
(address 0)
16.6 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 25).
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1]
Table 25.
Step
I2C-bus byte
1
I2C-bus start
initialized; no display appears
2
slave address for write
during the acknowledge cycle SDA is
pulled down by the PCF2113x
3
4
Display
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R/W Ack
0
1
1
1
0
1
0
0
0
send a control byte for ‘function set’
Co
RS
0
0
0
0
0
0
Ack
0
0
0
0
0
0
0
0
1
function set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
5
0
1
X
0
0
0
0
1
display control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
6
0
0
0
1
1
1
0
1
entry mode set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
0
0
0
0
1
1
0
1
PCF2113_FAM_4
Product data sheet
Operation
control byte sets RS for the following
data bytes
selects 1-line display and VLCD = VA;
SCL pulse during acknowledge cycle
starts execution of instruction
turns on display and cursor; entire
display shows character 20h (blank in
ASCII-like character sets)
sets mode to increment the address
by 1 and to shift the cursor to the right
at the time of write to the DDRAM or
CGRAM; display is not shifted
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
53 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1] …continued
Table 25.
Step
I2C-bus byte
7
I2C-bus start
8
slave address for write
9
10
Display
to write data to DDRAM, RS must be
set to 1 so a control byte is needed
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R/W Ack
0
1
1
1
0
1
0
0
1
send a control byte for ‘write data’
Co
RS
0
0
0
0
0
0
Ack
0
1
0
0
0
0
0
0
1
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
11
Operation
1
0
1
0
0
0
0
P
1
‘write data’ to DDRAM
writes ‘H’
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
writes ‘P’; the DDRAM is selected at
power-up; the cursor is incremented
by 1 and shifted to the right
0
1
12 to 15
0
0
0
PH
1
:
writes ‘ILIP’
:
16
‘write data’ to DDRAM
writes ‘S’
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
1
I2C-bus
17
stop)
(optional
write (as step 8)
18
control byte
19
0
I2C-bus
0
1
1
1
start + slave address for
Co
RS
0
0
0
0
0
0
Ack
1
0
0
0
0
0
0
0
1
PHILIPS
PHILIPS
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
0
0
0
20
I2C-bus start
21
slave address for read
22
PHILIPS
0
0
1
0
PHILIPS
1
PHILIPS
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R/W Ack
0
1
1
1
0
1
0
1
PHILIPS
1
control byte for read
Co
RS
0
0
0
0
0
0
Ack
0
1
1
0
0
0
0
0
1
PHILIPS
PCF2113_FAM_4
Product data sheet
sets DDRAM address 0 in address
counter (also returns shifted display
to original position; DDRAM contents
unchanged); this instruction does not
update the Data Register (DR)
during the acknowledge cycle the
content of DR is loaded into the
internal I2C-bus interface to be shifted
out; in the previous instruction neither
a ‘set address’ nor a ‘read data’ has
been performed, so the content of the
DR was unknown; the R/W has to be
set to 1 while still in the I2C-bus write
mode
DDRAM content is read from the
following instructions
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
54 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1] …continued
Table 25.
Step
I2C-bus byte
23
‘read data’: 8 × SCL + master acknowledge [2]
Display
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
X
X
X
X
X
X
X
X
PHILIPS
0
‘read data’: 8 × SCL + master acknowledge [2]
24
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
0
PHILIPS
0
‘read data’: 8 × SCL + master acknowledge [2]
25
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
1
1
I2C-bus stop
26
PHILIPS
X = not relevant.
[2]
SDA is left at high-impedance by the microcontroller during the read acknowledge.
Step
8 × SCL; code of letter ‘H’ is read first;
during master acknowledge, code of
‘I’ is loaded into the I2C-bus interface
no master acknowledge;
-after the content of the I2C-bus
interface register is shifted out no
internal action is performed;
-no new data is loaded into the
interface register;
-data register is not updated;
-address counter is not incremented
and cursor is not shifted
Initialization by instruction, 8-bit interface [1]
Instruction
RS
8 × SCL; content loaded into interface
during previous acknowledge cycle is
shifted out over SDA; MSB is DB7;
during master acknowledge content
of DDRAM address 01 is loaded into
the I2C-bus interface
PHILIPS
[1]
Table 26.
Operation
Description
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
internal reset
:
2
wait 2 ms
:
starting from power-on or unknown state
:
:
3
0
0
4
wait 2 ms
0
0
1
1
X
X
X
X
function set (interface is 8 bit long). Busy Flag (BF)
cannot be checked before this instruction
X
X
X
X
function set (interface is 8 bit long). BF cannot be
checked before this instruction
X
X
X
X
function set (interface is 8 bit long). BF cannot be
checked before this instruction
:
:
5
0
0
0
0
6
wait more than 40 µs
1
1
:
:
7
0
0
0
0
1
8
1
:
BF can be checked after the following instructions;
when BF is not checked the waiting time between
instructions is the specified instruction time (see
Table 10)
:
:
9
0
0
0
0
1
1
0
M
0
H
function set (interface is 8 bit long); specify the
number of display lines
10
0
0
0
0
0
0
1
0
0
0
display off
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
55 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 26.
Step
Initialization by instruction, 8-bit interface [1] …continued
Instruction
Description
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
11
0
0
0
0
0
0
0
0
0
1
clear display
12
0
0
0
0
0
0
0
1
I/D
S
entry mode set
13
initialization ends
:
[1]
X = not relevant.
Table 27.
Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
Step
Instruction
1
internal reset
Description
:
starting from power-on or unknown state
:
2
wait 2 ms
:
:
3
4
RS
R/W
DB7
DB6
DB5
DB4
BF cannot be checked before this instruction
0
0
0
0
1
1
function set (interface is 8 bit long)
wait 2 ms
:
:
5
6
RS
R/W
DB7
DB6
DB5
DB4
BF cannot be checked before this instruction
0
0
0
0
1
1
function set (interface is 8 bit long)
wait more than 40 µs
:
:
7
RS
R/W
DB7
DB6
DB5
DB4
BF cannot be checked before this instruction
0
0
0
0
1
1
function set (interface is 8 bit long)
8
:
BF can be checked after the following instructions; when BF is
not checked the waiting time between instructions is the specified
instruction time (see Table 10)
:
9
RS
0
0
0
0
1
0
interface is 8 bit long
10
0
0
0
0
1
0
function set (interface is 4 bit long)
0
0
0
M
0
H
specify number of display lines
11
0
0
0
0
0
0
0
0
1
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
I/D
S
13
R/W
DB7
DB6
DB5
DB4
function set (set interface to 4 bit long)
display off
clear display
entry mode set
:
14
initialization ends
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
56 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
17. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y
X
A
51
75
50
76
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
pin 1 index
L
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
14.1
13.9
14.1
13.9
0.5
HD
HE
16.25 16.25
15.75 15.75
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
Z D (1) Z E (1)
1.15
0.85
1.15
0.85
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT407-1
136E20
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-02-01
03-02-20
Fig 39. Package outline SOT407-1 (LQFP100)
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
57 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
18. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
MOS devices; see JESD625-A and/or IEC61340-5.
19. Packing information
x
A
C
y
D
B
F
E
mgu206
Fig 40. Tray details
Table 28.
Tray dimensions (see Figure 40)
Symbol
Description
Value
A
pocket pitch in x direction
6.35 mm
B
pocket pitch in y direction
5.59 mm
C
pocket width in x direction
3.82 mm
D
pocket width in y direction
3.66 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
x
number of pockets, x direction
7
y
number of pockets, y direction
8
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
58 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
PCF2113x
mgu207
Fig 41. Tray alignment
The orientation of the IC in a pocket is indicated by the position of the IC type name on the
die surface with respect to the chamfer on the upper left corner of the tray. Refer to the
bonding pad location diagram (Figure 3) for the orientation and position of the type name
on the die surface.
20. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
20.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
20.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
59 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
20.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
20.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 42) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 29 and 30
Table 29.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
60 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 30.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 42.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 42. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
61 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
21. Revision history
Table 31.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF2113_FAM_4
20080304
Product data sheet
-
PCF2113_FAM_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Figure 3, Figure 13, Figure 20 and Figure 21: new graphics.
Table 2 added: marking codes table.
Table 4: adjusted die size.
Table 18 and Table 19: adjusted values.
Table 25: changed byte settings.
PCF2113_FAM_3
(9397 750 06995)
20011219
Product specification
-
PCF2113_FAM_2
PCF2113_FAM_2
(9397 750 01753)
19970404
Preliminary data sheet
-
PCF2113_FAM_1
PCF2113_FAM_1
19961021
Preliminary specification
-
-
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
62 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
63 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
24. Contents
1
2
3
4
5
6
7
7.1
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.5
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.8
9.9
9.10
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . 10
LCD supply voltage generator . . . . . . . . . . . . 10
LCD bias voltage generator . . . . . . . . . . . . . . 10
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Busy flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address counter . . . . . . . . . . . . . . . . . . . . . . . 12
Display data RAM . . . . . . . . . . . . . . . . . . . . . . 12
Character generator ROM . . . . . . . . . . . . . . . 13
Character generator RAM. . . . . . . . . . . . . . . . 18
Cursor control circuit. . . . . . . . . . . . . . . . . . . . 18
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 19
LCD row and column drivers . . . . . . . . . . . . . 19
Power-down mode . . . . . . . . . . . . . . . . . . . . . 23
Reset function. . . . . . . . . . . . . . . . . . . . . . . . . 23
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clear display . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Return home. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Entry mode set . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit I/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Display control (and partial Power-down
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Cursor or display shift . . . . . . . . . . . . . . . . . . . 29
Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit DL (parallel mode only) . . . . . . . . . . . . . . . 29
Bit M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit SL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Set CGRAM address . . . . . . . . . . . . . . . . . . . 29
Set DDRAM address . . . . . . . . . . . . . . . . . . . 30
Read busy flag and read address. . . . . . . . . . 30
Write data to CGRAM or DDRAM. . . . . . . . . . 30
9.11
10
10.1
10.2
10.3
10.4
10.5
10.6
10.6.1
10.7
10.7.1
10.8
10.8.1
10.8.2
10.9
10.10
10.10.1
10.11
11
11.1
11.2
11.2.1
11.2.2
12
13
14
15
16
16.1
16.2
16.3
16.4
16.5
16.6
17
18
19
20
20.1
20.2
20.3
20.4
Read data from CGRAM or DDRAM . . . . . . .
Extended function set instructions
and features . . . . . . . . . . . . . . . . . . . . . . . . . . .
New instructions. . . . . . . . . . . . . . . . . . . . . . .
Icon control. . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit IB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage multiplier control . . . . . . . . . . . . . . . .
Bits S1 and S0 . . . . . . . . . . . . . . . . . . . . . . . .
Screen configuration . . . . . . . . . . . . . . . . . . .
Bit L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display configuration . . . . . . . . . . . . . . . . . . .
Bit P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature control . . . . . . . . . . . . . . . . . . . .
Set VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLCD programming . . . . . . . . . . . . . . . . . . . . .
Reducing current consumption . . . . . . . . . . .
Interfaces to microcontroller . . . . . . . . . . . . .
Parallel interface. . . . . . . . . . . . . . . . . . . . . . .
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . .
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Application diagrams . . . . . . . . . . . . . . . . . . .
General application information . . . . . . . . . . .
4-bit operation, 1-line display using
internal reset . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit operation, 1-line display using
internal reset . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit operation, 2-line display . . . . . . . . . . . . .
I2C-bus operation, 1-line display . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
30
31
31
31
32
32
33
33
33
33
33
34
34
34
35
35
35
35
36
36
37
38
40
41
42
43
45
47
47
49
49
49
52
53
57
58
58
59
59
59
60
60
continued >>
PCF2113_FAM_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 March 2008
64 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
21
22
22.1
22.2
22.3
22.4
23
24
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
63
63
63
63
63
63
64
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 March 2008
Document identifier: PCF2113_FAM_4
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