Data Sheet

NVT4556
SIM card interface level translator with I2C-bus control and
LDO
Rev. 1.1 — 25 August 2015
Product data sheet
1. General description
The NVT4556 device is built for interfacing a SIM card with a single low-voltage host-side
interface. The NVT4556 contains an LDO that can deliver two different voltages, 1.8 V or
3 V, from a typical mobile phone battery voltage, and three level translators to convert the
data, RSTn and CLKn signals between a SIM card and a host microcontroller.
The NVT4556 VCC pin provides power to the host side I/Os and doubles as an enable pin,
for this reason it can be connected to a GPIO that matches the host side voltage. The total
current draw from the VCC pin is only 100 A maximum. The NVT4556 also uses the
I2C-bus interface to enable normal operation and to select either 1.8 V or 3 V for the SIM
card power supply. The NVT4556 can also disable the LDO functionality while maintaining
the level translator paths so that the user can use a system-controlled regulator to power
the SIM card power supply. The NVT4556 can enable users to provide second and third
SIM card functionality with a low-voltage one host SIM port, at the same time reducing the
number of GPIOs used in the system. The NVT4556 is compliant with all ETSI, IMT-2000
and ISO-7816 SIM/Smart card interface requirements.
The NVT4556 is available in a 12-pin WLCSP package and has three factory
programmed slave address options.
2. Features and benefits














Support SIM card supply voltages 1.8 V and 3 V
Input voltage range to LDO: 2.5 V to 5.25 V
Host microcontroller operating voltage range: 1.55 V to 3.6 V
VCC input pin provides both host supply voltage and logic level hardware
enable/disable pin: source through Host GPIO (ICC <100 A)
RST_HOST/EN pin can be programmed as a reset pin or as a device enable/disable
pin
Level translation of I/O, RSTn and CLKn between SIM card and host-side interface
with capacitive isolation
I2C-bus interface for device enable and LDO voltage selection
Low current shutdown mode < 3 A
Supports clock speed beyond 5 MHz clock
Supports CLK stop mode
Integrated EMI filters
Incorporates ISO-7816-3 shutdown feature for the SIM card signals
ETSI, IMT2000 and ISO-7816 compliant
8 kV IEC61000-4-2 ESD protected on all SIM card contact pins
NVT4556
NXP Semiconductors
SIM card interface level translator with I2C-bus control and LDO
 Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
 Available in 12-pin WLCSP package (1.205 mm  1.605 mm  0.412 mm,
0.4 mm pitch)
3. Applications
 NVT4556 can be used with a range of SIM card attached devices including:
 Mobile and personal phones
 Wireless modems
 SIM card terminals
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
NVT4556AUK
556A
WLCSP12
wafer level chip-size package; 12 balls;
body 1.205  1.605  0.412 mm (Backside coating included)
NVT4556AUK
NVT4556BUK
556B
WLCSP12
wafer level chip-size package; 12 balls;
body 1.205  1.605  0.412 mm (Backside coating included)
NVT4556BUK
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
NVT4556AUK
NVT4556AUKZ
WLCSP12 Reel 7” Q1/T1
*Special mark chips
dry pack
3000
Tamb = 40 C to +85 C
1100 000xb
NVT4556BUK
NVT4556BUKZ
WLCSP12 Reel 7” Q1/T1
*Special mark chips
dry pack
3000
Tamb = 40 C to +85 C
1100 001xb
NVT4556
Product data sheet
Packing method
Minimum Temperature
order
quantity
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Rev. 1.1 — 25 August 2015
Slave
address
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
5. Functional diagram
SDA
REGISTERS
AND
CONTROL LOGIC
I2C-BUS
SCL
VBAT
VSIM
LDO
VCC
UVLO
RST_HOST/EN
RST_SIM
CLK_HOST
CLK_SIM
IO_SIM
IO_HOST
GND
002aah626
Fig 1.
Functional diagram
6. Pinning information
bump A1
index area
NVT4556UK
A1
A2
A3
B1
B2
B3
C1
C2
C3
D1
D2
D3
1
2
3
A
IO_HOST
GND
VCC
B
RST_HOST/
EN
SDA
VBAT
C
CLK_HOST
SCL
VSIM
D
CLK_SIM
RST_SIM
IO_SIM
002aah627
002aah634
Transparent top view
Fig 2.
NVT4556
Product data sheet
Bump configuration for WLCSP12
Transparent top view
Fig 3.
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Rev. 1.1 — 25 August 2015
Bump mapping for WLCPS12
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NVT4556
NXP Semiconductors
SIM card interface level translator with I2C-bus control and LDO
6.1 Pin description
Table 3.
NVT4556
Product data sheet
Pin description
Symbol
Pin
Type
Description
IO_HOST
A1
I/O
Host controller bidirectional data input/output. This output
must be on an open-drain configuration.
GND
A2
ground
Ground for the SIM card and host controller. Proper grounding
and bypassing are required to meet ESD specifications.
VCC
A3
power
Supply voltage for the host controller side input/output pins
(CLK_HOST, RST_HOST/EN, IO_HOST). When VCC is below
the UVLO threshold, the VSIM supply is disabled. This pin
should be bypassed with a 100 nF ceramic capacitor close to
the pin.
RST_HOST/EN
B1
I
Reset input from host controller or acts as a programmable
logic-level enable/disable when bit 6 = 1.
SDA
B2
I/O
Digital input/output. I2C-bus serial bidirectional data line;
open-drain.
VBAT
B3
power
Battery voltage supply for internal LDO. This input voltage
ranges from 2.5 V to 5.25 V. This pin should be bypassed with
a 1.0 F ceramic capacitor close to the pin.
CLK_HOST
C1
I
Clock input from host controller.
SCL
C2
I
Digital input. I2C-bus serial bidirectional clock line.
VSIM
C3
power
SIM card supply voltage from internal LDO. The voltage at this
pin can be selected for either 1.8 V (CTRL = 0) or 3 V
(CTRL = 1). This pin should be bypassed with a 4.7 F
ceramic capacitor close to the pin.
CLK_SIM
D1
O
Clock output pin for the SIM card.
RST_SIM
D2
O
Reset output pin for the SIM card.
IO_SIM
D3
I/O
SIM card bidirectional data input/output. The SIM card output
must be on an open-drain driver.
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Rev. 1.1 — 25 August 2015
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NVT4556
NXP Semiconductors
SIM card interface level translator with I2C-bus control and LDO
7. Functional description
Refer to Figure 1 “Functional diagram”.
7.1 Shutdown sequence of NVT4556
The ISO 7816-3 specification specifies the shutdown sequence for the SIM card signals.
This shutdown sequence ensures that these channels are properly disabled and does not
have any accidental corruption of data. Also during hot swap, the orderly shutdown of
these signals helps to avoid any improper write and corruption of data.
When the VCC falls below its UVLO threshold, a shutdown sequence is immediately
initiated. The RST_SIM is first driven LOW after a short delay the CLK_SIM and IO_SIM
are driven LOW followed by VSIM. An internal pull-down resistor on the SIM pins is used
to pull these channels LOW. The shutdown sequence is completed in a few
microseconds.
UVLO
threshold
VCC
RST_SIM
tdis(CLK_SIM)
CLK_SIM
IO_SIM
ACTIVE DATA
tdis(VSIM)
VSIM
002aah639
Fig 4.
VCC UVLO shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of
NVT4556 SIM card translator
The shutdown sequence can also be initiated by one of two events: by de-asserting the
RST_HOST/EN pin if bit 6 (RST_HOST pin mode select bit) is set to 1, or by writing a 0 to
bit 0 (Device enable bit) if bit 6 is set to 0. The shutdown sequence consists of first
powering down the RST_SIM channel. Once the RST_SIM channel is powered down,
CLK_SIM, IO_SIM and VSIM are powered down sequentially one-by-one. An internal
pull-down resistor on the SIM pins is used to pull these channels LOW. The shutdown
sequence is completed in a few microseconds. It is important that enable is written LOW
before VBAT and VCC supplies go LOW to ensure that the shutdown sequence is properly
initiated. The NVT4556 is enabled and disabled at the end of the I2C-bus write sequence,
so a delay in the start of the I/O signals should account for time of this data sequence.
NVT4556
Product data sheet
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Rev. 1.1 — 25 August 2015
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
SCL
SDA
SLAVE ADDRESS
ACK
ACK
DATA
tdis(RST_SIM)
RST_SIM
tdis(CLK_SIM)
CLK_SIM
tdis(IO_SIM)
IO_SIM
ACTIVE DATA
tdis(VSIM)
VSIM
002aah640
Fig 5.
I2C-bus shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of
NVT4556 SIM card translator
7.2 RST_HOST/EN pin
The NVT4556 RST_HOST/EN pin can be programmed to accept the reset signal from the
host to the SIM card or programmed to be an enable pin for the part. When the NVT4556
is programmed with bit 6 = 0, the RST_HOST/EN pin acts as a pass-through logic-level
translator. A 0 on the host side appears as a 0 on the SIM side, and a 1 at the host side
appears as a 1 on the SIM side. When the NVT4556 is programmed with bit 6 = 1, the
RST_HOST/EN pin becomes a hardware enable/disable pin, so that the part can be
enabled and disabled with a logic level input. In this case, the VCC can be powered from
the host supply and does not need to be pulled down to disable the part. Also, the reset
signal for the SIM card must be written to bit 5. When a 1 is written to bit 5, a logic 1 is
asserted onto RST_SIM. When a 0 is written to bit 5, a logic 0 is asserted on onto
RST_SIM.
When bit 6 is set to 1 and RST_HOST/EN acts as an enable pin, bit 0 is ignored and only
logic signals acting on RST_HOST/EN and the VCC enable and disable the part. Bit 0 can
be read to see the state of the RST_HOST/EN pin and bit 3 can be programmed to set the
EN polarity to be active HIGH or active LOW.
7.3 Clock stop, latch I/O state
The NVT4556 can also support clock stop modes as well as an I/O stop so that two
NVT4556 devices can operate from a single host SIM port. The NVT4556 can latch the
state of the IO_HOST, CLK_HOST and RST_HOST/EN when bit 4 is toggled to 1. This
asserts the logic value onto the IO_SIM, CLK_SIM and RST_SIM pins. This effectively
initiates the clock stop mode and free the user to activate a secondary NVT4556 attached
to the same host port. The NVT4556 devices must have different I2C-bus addresses so
that they can be accessed independently of each other.
If bit 6 is programmed to 1 and the RST_HOST/EN pin is acting as an enable pin, then
bit 5 must be used to latch the RST_SIM state through the I2C-bus.
NVT4556
Product data sheet
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Rev. 1.1 — 25 August 2015
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
7.4 Software reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as the following (see Figure 6):
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2C-bus master.
3. The NVT4556 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h. The NVT4556 acknowledges this
value only. If the byte is not equal to 06h, the NVT4556 does not acknowledge it. If
more than 1 byte of data is sent, the NVT4556 does not acknowledge any more.
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: NVT4556 then resets to the
default value (power-up value) and is ready to be addressed again within the specified
bus free time. If the master sends a Repeated START instead, no reset is performed.
SWRST Call I2C-bus address
S
0
0
0
0
0
START condition
0
0
SWRST data = 06h
0
R/W
A
0
0
0
acknowledge
from slave(s)
0
0
1
1
0
A
P
acknowledge
from slave(s)
STOP condition;
NVT4556 is(are) reset.
Registers are set to default power-up values.
002aah742
Fig 6.
Software reset sequence
The I2C-bus master must interpret a non-acknowledge from the NVT4556 (at any time)
as a ‘Software Reset Abort’.
NVT4556
Product data sheet
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VESD
Parameter
Conditions
electrostatic discharge voltage
Min
Max
Unit
SIM card side and VSIM pins;
IEC 61000-4-2
[1]
-
8
kV
all other pins; IEC 61000-4-2
[1]
-
2
kV
all other pins; HBM
[2]
-
2
kV
all other pins; CDM
[3]
-
500
V
VCC
supply voltage
GND  0.5
3.6
V
VBAT
battery supply voltage
GND  0.5
5.5
V
VI(CLK_HOST)
input voltage on pin CLK_HOST
input signal voltage, HOST side
GND  0.5
VCC + 0.5
V
VI(RST_HOST/EN)
input voltage on pin
RST_HOST/EN
input signal voltage, HOST side
GND  0.5
VCC + 0.5
V
VI(IO_HOST)
input voltage on pin IO_HOST
input signal voltage, HOST side
GND  0.5
VCC + 0.5
V
VI(CLK_SIM)
input voltage on pin CLK_SIM
input signal voltage, SIM side
GND  0.5
VVSIM + 0.5
V
VI(RST_SIM)
input voltage on pin RST_SIM
input signal voltage, SIM side
GND  0.5
VVSIM + 0.5
V
VI(IO_SIM)
input voltage on pin IO_SIM
input signal voltage, SIM side
GND  0.5
VVSIM + 0.5
V
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
[1]
IEC 61000-4-2, level 4, contact discharge.
[2]
Human Body Model (HBM) according to JESD22-A114.
[3]
Charged-Device Model (CDM) according to JESD22-C101.
NVT4556
Product data sheet
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
9. Characteristics
Table 5.
Supplies
2.5 V  VBAT  5.5 V; 1.55 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
VCC
supply voltage
ICC
supply current
VBAT
battery supply voltage
IBAT
battery supply current
Vth(UVLO)
undervoltage lockout
threshold voltage
Vhys(UVLO)
undervoltage lockout
hysteresis voltage
[1]
Min
Typ[1]
Max
Unit
1.55
-
3.6
V
operating mode; register 00h = 01h/03h;
SDA = IO_HOST = VCC;
RST_HOST/EN = GND;
fclk = 1 MHz; fclk(SCL) = 400 kHz
-
40
100
A
operating mode; register 00h = 01h/03h;
SDA = SCL = IO_HOST = VCC;
RST_HOST/EN = GND; fclk = 1 MHz
-
10
20
A
operating mode; register 00h = 01h/03h;
SCL = SDA = IO_HOST = VCC;
CLK_HOST = RST_HOST/EN = GND
-
10
20
A
standby mode; register 00h = 00h;
SDA = SCL = IO_HOST = VCC;
CLK_HOST = RST_HOST/EN = GND;
VCC = 1.8 V
-
5
10
A
shut-down mode; register 00h = 00h;
VCC = 0 V
-
-
1
A
Conditions
2.5
-
5.25
V
operating mode; register 00h = 01h/03h;
IO_HOST = VCC;
CLK_HOST = RST_HOST/EN = GND
-
30
40
A
shutdown mode; register 00h = 00h
-
2
3
A
VCC rising; VBAT = 3.6 V
1.2
-
1.5
V
-
100
-
mV
Typical values measured at 25 C. VCC = 1.8 V; VBAT = 3.6 V; VVSIM (VSIM pin) = 1.8 V.
Table 6.
Static characteristics
2.5 V  VBAT  5.5 V; 1.55 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
-
-
400
kHz
I2C-bus
fclk(SCL)
SCL clock frequency
VIH
HIGH-level input voltage pins SCL, SDA
0.7  VCC
-
-
V
VIL
LOW-level input voltage
pins SCL, SDA
-
-
0.3  VCC
V
VOL = 0.4 V
-
3
-
mA
IOL(sink)(SDA) LOW-level output sink
current on pin SDA
NVT4556
Product data sheet
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
Table 6.
Static characteristics …continued
2.5 V  VBAT  5.5 V; 1.55 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
voltage on pin VSIM
VSIM pin; 00h = 03h;
3.2 V  VBAT  5.25 V;
0 mA  ISIM  50 mA
2.85
3.0
3.15
V
VSIM pin; 00h = 01h;
2.5 V  VBAT  5.25 V;
0 mA  ISIM  50 mA
1.7
1.8
1.9
V
LDO
VVSIM
Vdo
dropout voltage
IO = 50 mA; VBAT = 2.90 V
-
100
150
mV
Isc
short-circuit current
VSIM shorted to GND
90
135
170
mA
tstartup
start-up time
VVSIM = 1.8 V or 3 V;
IO = 50 mA; Co = 1 F
-
-
400
s
Tj(sd)
shutdown junction
temperature
-
160
-
°C
Tsd(hys)
hysteresis of shutdown
temperature
-
20
-
°C
Rpd
pull-down resistance
VSIM discharge; 00h = 00h;
VBAT = 3.6 V; VCC = 1.55 V
-
100
-

PSRR
power supply rejection
ratio
VBAT = 3.6 V; ISIM = 20 mA;
VVSIM = 1.8 V or 3 V
f = 1 kHz
-
60
-
dB
f = 10 kHz
-
50
-
dB
[2]
0.7  VCC
-
VCC + 0.2
V
IO_SIM
[2]
0.7  VVSIM -
VVSIM + 0.2
V
IO_HOST, RST_HOST/EN,
CLK_HOST
[2]
0.15
-
0.15  VCC
V
IO_SIM
[2]
0.3
-
0.15  VVSIM
V
IO_SIM connected to VSIM
[3]
4
6
8
k
IO_HOST connected to VCC
[3]
3.5
5
6.5
k
RST_SIM, CLK_SIM;
IOH = 1 mA
[2]
-
0.7  VVSIM
VVSIM
V
IO_SIM; IOH = 10 A
[2]
-
0.7  VVSIM
VVSIM
V
IO_HOST; IOH = 10 A
[2]
-
0.7  VCC
VCC
V
RST_SIM, CLK_SIM;
IOL = 1 mA
[2]
-
100
300
mV
IO_SIM; IOL = 1 mA
[2]
-
100
300
mV
IO_HOST; IOL = 1 mA
[2]
-
100
300
mV
70
100
130
k
Level shifter
VIH
HIGH-level input voltage IO_HOST, RST_HOST/EN,
CLK_HOST
1.55 V  VCC < 3.6 V
VIL
RPU
VOH
VOL
Rpd
LOW-level input voltage
pull-up resistance
HIGH-level
output voltage
LOW-level
output voltage
pull-down resistance
NVT4556
Product data sheet
CLK_HOST,
RST_HOST/EN; EN = 0
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NVT4556
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SIM card interface level translator with I2C-bus control and LDO
Table 6.
Static characteristics …continued
2.5 V  VBAT  5.5 V; 1.55 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Min
Typ[1]
Max
Unit
[2][4]
-
200
-

RST_SIM
[4]
-
200
-

CLK_SIM
[2][4]
-
200
-

[2][4]
-
45
-
pF
RST_SIM
[4]
-
45
-
pF
CLK_SIM
[2][4]
-
45
-
pF
Parameter
Conditions
series resistance
IO_SIM
EMI filter
Rs
input/output capacitance IO_SIM
Cio
[1]
Typical values measured at 25 C.
[2]
VIL, VIH depend on the individual supply voltage per interface.
[3]
See Figure 10 for details.
[4]
Guaranteed by design.
Table 7.
Dynamic characteristics
2.5 V  VBAT  5.5 V; fclk = fio = 1 MHz; Tamb = 40 C to +85 C; unless otherwise specified. Refer to Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
-
-
5
s
10
ns
VCC = 1.8 V; VSIM = 3 V; SIM card CL  30 pF; host CL  10 pF
time after ACK from I2C-bus write to latch host I/Os
to SIM I/Os; bit 4 = 1
td(latch)
latch delay time
tt
transition time
[1]
-
-
tsk(o)
output skew time
between channels; IO_SIM and CLK_SIM
[2]
-
2
-
ns
tPD
propagation delay
I/O channel; SIM card side to host side
[1]
-
15
25
ns
all channels; host side to SIM card side
[1]
-
15
25
ns
fo(clk)
clock output frequency
CLK_SIM
5
-
-
MHz
tdis(RST_SIM)
RST_SIM disable time
disable time from initiating RST_HOST/EN bit 6 = 1
or from I2C-bus disable ACK
-
20
50
s
tdis(CLK_SIM)
CLK_SIM disable time
-
25
60
s
tdis(IO_SIM)
IO_SIM disable time
-
35
65
s
tdis(VSIM)
VSIM disable time
-
200
-
s
Co(L) = 4.7 F
[1]
All dynamic measurements are done with a 50 pF load. Rise times are determined by internal pull-up resistors.
[2]
Skew between any two outputs of the same package switching in the same direction with the same CL.
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
9.1 Waveforms
VI
input
VM
GND
tPHL
tPLH
VOH
90 %
output
VM
10 %
tTHL
tTLH
VOL
002aag078
Measurement points are given in Table 7.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
NVT4556
Product data sheet
Data input to data output propagation delay times
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SIM card interface level translator with I2C-bus control and LDO
10. Application information
Figure 8 is the application circuit for the NVT4556 and shows the typical interface with a
SIM card. The VCC pin on the NVT4556 powers the host I/O pins and is designed to be
driven from a GPIO. This GPIO then acts as both the host-side power supply and an
enable/disable pin. The NVT4556 provides a Low-DropOut (LDO) regulator that is
designed for high Power Supply Rejection Ratio (PSRR) at a very low drop-out voltage
(VBAT  VVSIM). The LDO regulator provides two levels of fixed voltage regulation at 1.8 V
or 3 V, which are selected with an I2C-bus write. Since there is only one register, a
subaddress is not necessary.
VBAT (2.5 V to 5.25 V)
100 nF
GPIO
1 μF
VCC
SCL
SDA
HOST
PROCESSOR
I2C-BUS
INTERFACE
LDO
REGULATOR
(1.8 V or 3 V; 50 mA max.)
VSIM
4.7 μF
NVT4556
RST_HOST/EN
CLK_HOST
IO_HOST
RST_SIM
LEVEL
TRANSLATOR
SIM CARD
CLK_SIM
IO_SIM
002aah630
Fig 8.
NVT4556
Product data sheet
NVT4556 application circuit interfacing with typical SIM card
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SIM card interface level translator with I2C-bus control and LDO
10.1 Input/output capacitor considerations
It is recommended that a 1 F capacitor and a 100 nF capacitor having low Equivalent
Series Resistance (ESR) are used respectively at the battery (VBAT) and VCC input
terminals of the NVT4556. X5R and X7R type multi-layer ceramic capacitors (MLCC) are
preferred because they have minimal variation in value and ESR over temperature. The
maximum ESR should be < 500 m(50 m typical).
Also, a 2.2 F to 4.7 F capacitor is recommended at the Low Dropout regulator (LDO)
output terminal to ensure stability. X5R and X7R type are recommended for their minimal
variation over temperature and low ESR over frequency which avoids stability issues at
high frequencies. The maximum ESR should be < 1.0 . Furthermore, the decrease in
capacitance with an increase in the bias voltage should be considered to optimize LDO
stability. In addition, the trade-off in LDO stability versus the value and constraint in case
size of the capacitor determined by the application must be considered. As output load
capacitance decreases, the LDO stability becomes marginal. A given 4.7 F ceramic
capacitor may become 0.33 F capacitance depending on the effects of bias voltage and
temperature. It is recommended to refer to the manufacturer’s characterization of a
capacitor based on case size, bias voltage and type. Figure 9 is an example of how a
4.7 F capacitor is affected by the above parameters.
002aah650
20
∆C/
C
(%)
1206, 6.3 V
−20
1206, 10 V
0805, 6.3 V
0603, 6.3 V
−60
0805, 10 V
0603, 10 V
0402, 6.3 V
−100
0
2
4
6
8
10
VDC (V)
Fig 9.
Variation of capacitance for a 4.7 F capacitor versus DC voltage, value, and case size
10.2 Layout consideration
The capacitors should be placed directly at the terminals and ground plane. Since the
internal band gap regulator is the dominant noise source in a typical application,
connections and routing of the ground is very important to improve and optimize noise
performance, PSRR and transient response. It is recommended to design the PCB with
separate ground planes for the VI (VBAT) and VO (VSIM) of the LDO regulator with each
ground plane connected only at the GND pin of the NVT4556.
NVT4556
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10.3 Dropout voltage
The NVT4556 uses a PMOS pass transistor to achieve a very low dropout voltage. When
VBAT  VVSIM is less than the dropout voltage, the PMOS transistor operates in the linear
region and the input-to-output resistance is RDSon of the PMOS device. The dropout
voltage, Vdo, scales with the output current since the PMOS device behaves like a resistor
in the input-to-output path.
10.4 Level translator stage
The architecture of the NVT4556 I/O channel is shown in Figure 10. The device does not
require an extra input signal to control the direction of data flow from host to SIM or from
SIM to host. As a change of driving direction is possible only when both sides are in HIGH
state, the control logic is recognizing the first falling edge granting it control about the
other signal side. During a rising edge signal, the non-driving output is driven by a
one-shot circuit to accelerate the rising edge. In case of a communication error or some
other unforeseen incident that would drive both connected sides to be drivers at the same
time, the internal logic automatically prevents stuck-at situation, so both I/Os return to
HIGH level once released from being driven LOW.
The channels RST and CLK contain single direction drivers without the holding
mechanism of the I/O channel, as these are driven only from the host to the card side.
VSIM
side B supply
RISING EDGE
DETECT
ONE
SHOT
pull-up
IO_SIM
DIRECTION
CONTROL
CIRCUITRY
VCC
side A supply
pull-up
ONE
SHOT
RISING EDGE
DETECT
IO_HOST
aaa-012269
Fig 10. Automatic direction control level translator for HIGH-level direction change interfaces
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
10.5 LDO block diagram
The block diagram of the LDO is depicted in Figure 11. It contains a pull-down mechanism
to avoid any uncontrolled voltage level at the VSIM pin in the disabled state. Furthermore,
thermal protection as well as an overcurrent protection are integrated to disable the output
in case of a permanent short that may result in excessive self-heating.
VSIM
VBAT
R1
Vref
GENERATOR
enable and control
from I2C-bus
R2
THERMAL
PROTECTION
OVERCURRENT
PROTECTION
GND
002aah629
Fig 11. LDO block diagram
The default LDO output voltage is 1.8 V but can be selected to be either 1.8 V or 3.0 V
through the proper I2C-bus writes.
The I2C-bus has the ability to disable the LDO such that the VSIM can be powered
through an external system regulator. If the LDO is disabled, the RSTn, CLKn and IOn
data paths are still active. It is necessary to supply external power to the VCC, VSIM, and
VBAT power supply pins, since there is active circuitry that still exists on the three supplies.
10.6 Power-on reset
When power is applied to VCC, an internal Power-On Reset (POR) holds the NVT4556 in
a reset condition until VCC has reached VPOR. At that point, the reset condition is released
and the NVT4556 registers and I2C-bus state machine initialize to their default states.
Thereafter VCC must be lowered below 1.2 V to reset the device.
10.7 Serial bus interface
The NVT4556 communicates with a host controller by means of the 2-wire serial bus
(I2C-bus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device
supports I2C-bus Standard-mode and Fast-mode. The I2C-bus Standard-mode speed is
defined to have bus speeds from 0 Hz to 100 kHz. I2C-bus Fast-mode speed is from 0 Hz
to 400 kHz. The host or bus master generates the SCL signal and the NVT4556 uses the
SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional,
and is 1 byte at a time with the Most Significant Bit (MSB) transferred first. Since SCL and
SDA are open-drain, pull-up resistors must be installed on these pins.
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
10.8 Slave address
The NVT4556 uses a 7-bit slave address to identify it on the I2C-bus. The last bit of the
address byte defines the operation to be performed. When set to logic 1, a read is
selected, while a logic 0 selects a write operation. The level translator’s 7-bit fixed slave
address is ‘60h’ for the NVT4556AUK, ‘61h’ for the NVT4556BUK and ‘62h’ for the
NVT4556CUK. However, for a write operation (R/W bit = 0) to the NVT4556, the address
byte content (8 bits) is ‘C0h’ for the NVT4556AUK, ‘C2h’ for the NVT4556BUK, and
‘C4h’ for the NVT4556CUK.
Remark: Device variant NVT4556CUK is under development.
slave address
R/W
MSB
1
slave address
LSB
1
0
0
0
0
0
R/W
MSB
X
slave address
LSB
1
1
0
0
0
0
002aah651
1
R/W
MSB
X
1
LSB
1
0
0
0
1
0
002aah656
a. NVT4556A
X
002aah657
b. NVT4556B
c. NVT4556C
(under development)
Fig 12. Slave address; normal read/write
10.9 I2C-bus interface
There is only one data register in this device, so the Pointer register is always set to ‘00h’.
For this reason, a subaddress is not required for reading or writing. Only data is required
to be sent on the bus after a slave address acknowledge.
A ‘write’ to this device always includes the slave address byte and data byte.
A ‘read’ to this device always includes the slave address byte and data byte.
The data byte has the most significant bit first. At the end of a read, this device can accept
either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge
is typically used as a signal for the slave that the Master has read its last byte).
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
A0
8
9
W
A
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
SCL
SDA
S
START
ACK
by slave
device address and write
A
register data
P
ACK
STOP
by slave
002aah652
A = ACK = Acknowledge bit. W = Write bit = 0.
Fig 13. I2C-bus write to NVT4556A
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
A0
8
9
R
A
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
SCL
SDA
S
START
A
ACK
by slave
device address and read
P
NACK STOP
by master
register data
002aah653
A = ACK = Acknowledge bit. R = Read bit = 1.
Fig 14. I2C-bus read from NVT4556A
10.10 Write operations
10.10.1 Byte Write
In Byte Write mode, the master creates a START condition and then broadcasts the slave
address and data to be written. The slave acknowledges the bytes by pulling down the
SDA line during the ninth clock cycle following each byte. The master creates a STOP
condition after the last ACK from the slave, which then starts the internal write operation
(see Figure 15). During internal write, the slave ignores any read/write request from the
master.
slave address
SDA
S
1
1
0
0
0
START condition
data
0
0
0
A
0
0
R/W acknowledge
from slave
0
0
0
0
D1 D0 A
P
acknowledge
from slave
STOP condition
002aah654
Fig 15. Byte Write for NVT4556A
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
10.11 Read operations
10.11.1 Byte Read
If the NVT4556 decodes a slave address with a ‘1’ in the R/W bit position (Figure 16), it
issues an Acknowledge in the ninth clock cycle and then transmits the data byte. The
master can then stop further transmission by issuing a No Acknowledge on the ninth bit
then followed by a STOP condition.
slave address
SDA
S
1
1
0
0
0
START condition
data
0
0
1
A
R/W acknowledge
from slave
A
P
no acknowledge
from master
STOP condition
002aah655
Fig 16. Byte Read for NVT4556A
10.12 User accessible registers
10.12.1 Register overview
This section describes all the registers used in the NVT4556. The device contains only
one register which is read/write-able. No subaddress is necessary when reading or writing
to the device.
Table 8.
NVT4556
Product data sheet
Register summary
Address
Register name
Description
00h
DEV_CFG
Device information and revision and enable functions
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SIM card interface level translator with I2C-bus control and LDO
10.12.2 Register map
Table 9.
User accessible register maps
Legend: * = default. Register modes and default values are only valid with operating the NVT4556 in I2C-bus mode.
Address Register
name
00h
Symbol Bit
DEV_CFG
Description
Device information. Contains enable functions.
D7
7
LDO disable; enables/disables the LDO. The I/O paths are still operational. VVSIM
(VSIM pin) must be provided from the system. VBAT must be connected to the
battery voltage.
0* — LDO enabled (default)
1 — LDO disabled
D6
6
RST_HOST/EN pin mode select
0* — RST_HOST enabled (default)
The RST_HOST/EN pin passes the logic on the input directly to the RST_SIM pin.
1 — EN
The RST_HOST/EN pin becomes an enable/disable pin for the device. The
polarity of the RST_HOST/EN pin is set by bit 3.
The RST_SIM signal is sent through bit 5.
D5
5
RST_SIM active: this bit is active only when bit 6 = 1.
0* — RST_SIM disable (default)
This sends and latches a logic LOW to the RST_SIM pin.
1 — RST_SIM enabled
This sends and latches a logic HIGH to the RST_SIM pin.
D4
4
Latch IO states
Setting this bit latches the state of the input pins IO_HOST, CLK_HOST and
RST_HOST/EN (when bit 6 = 0) to the output pins IO_SIM, CLK_SIM, and
RST_SIM.
This can be used for clock stop when two NVT4556 devices are used on the same
host.
0* — Latch OFF (default)
1 — I/Os latched
D3
3
Enable polarity. This bit sets the RST_HOST/EN pin polarity when bit 6 is set to 1.
0* — Active HIGH enable: Device enables when RST_HOST/EN pin = 1.
1 — Active LOW enable: Device enables when RST_HOST/EN pin = 0.
-
2
D1
1
reserved
Voltage selection: selects the output voltage of the LDO
0* — 1.8 V (default)
1—3V
D0
0
Device enable
0* — Disable (default)
1 — Enable
bit 6 = 0: R/W
bit 6 = 1: R only and displays RST_HOST/EN status
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
11. Package outline
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1978.
Fig 17. Package outline NVT4556UK (WLCSP12)
NVT4556
Product data sheet
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SIM card interface level translator with I2C-bus control and LDO
12. Soldering of WLCSP packages
12.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
12.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
12.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 10.
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
12.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
12.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
12.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
NVT4556
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SIM card interface level translator with I2C-bus control and LDO
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
12.3.4 Cleaning
Cleaning can be done after reflow soldering.
13. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
GPIO
General Purpose Input/Output
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LDO
Low DropOut regulator
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal-Oxide Semiconductor
SIM
Subscriber Identification Module
UVLO
UnderVoltage Lock-Out
14. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NVT4556 v.1.1
20150825
Product data sheet
-
NVT4556 v.1
Modifications:
NVT4556 v.1
NVT4556
Product data sheet
•
Table 3 “Pin description”: VCC description; changed “1.0 nF” to “100 nF”
20140602
Product data sheet
-
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-
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SIM card interface level translator with I2C-bus control and LDO
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NVT4556
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 25 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
25 of 27
NVT4556
NXP Semiconductors
SIM card interface level translator with I2C-bus control and LDO
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NVT4556
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 25 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
26 of 27
NVT4556
NXP Semiconductors
SIM card interface level translator with I2C-bus control and LDO
17. Contents
1
2
3
4
4.1
5
6
6.1
7
7.1
7.2
7.3
7.4
8
9
9.1
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.10.1
10.11
10.11.1
10.12
10.12.1
10.12.2
11
12
12.1
12.2
12.3
12.3.1
12.3.2
12.3.3
12.3.4
13
14
15
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Shutdown sequence of NVT4556 . . . . . . . . . . . 5
RST_HOST/EN pin. . . . . . . . . . . . . . . . . . . . . . 6
Clock stop, latch I/O state. . . . . . . . . . . . . . . . . 6
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 13
Input/output capacitor considerations . . . . . . . 14
Layout consideration . . . . . . . . . . . . . . . . . . . 14
Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . 15
Level translator stage . . . . . . . . . . . . . . . . . . . 15
LDO block diagram . . . . . . . . . . . . . . . . . . . . . 16
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial bus interface . . . . . . . . . . . . . . . . . . . . . 16
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 17
Write operations . . . . . . . . . . . . . . . . . . . . . . . 18
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read operations . . . . . . . . . . . . . . . . . . . . . . . 19
Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User accessible registers . . . . . . . . . . . . . . . . 19
Register overview . . . . . . . . . . . . . . . . . . . . . . 19
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Soldering of WLCSP packages. . . . . . . . . . . . 22
Introduction to soldering WLCSP packages . . 22
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Quality of solder joint . . . . . . . . . . . . . . . . . . . 23
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
15.1
15.2
15.3
15.4
16
17
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
26
27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 August 2015
Document identifier: NVT4556
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