Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
PCF2116 family
LCD controller/drivers
Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12
1997 Apr 07
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
3.1
Packages
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
Entry mode set
Display on/off control
Cursor/display shift
Function set
Set CGRAM address
Set DDRAM address
Read busy flag and address
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
6
PINNING
10
7
PIN FUNCTIONS
INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
RS: register select (parallel control)
R/W: read/write (parallel control)
E: data bus clock
DB0 to DB7: data bus
C1 to C60: column driver outputs
R1 to R32: row driver outputs
VLCD: LCD power supply
V0: VLCD control input
OSC: oscillator
SCL: serial clock line
SDA: serial data line
SA0: address pin
T1: test pad
11
INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
11.1
11.2
11.3
11.4
11.5
11.6
Characteristics of the I2C-bus
Bit transfer
START and STOP conditions
System configuration
Acknowledge
I2C-bus protocol
12
LIMITING VALUES
13
HANDLING
14
DC CHARACTERISTICS
15
DC CHARACTERISTICS (PCF2116K)
AC CHARACTERISTICS
8
FUNCTIONAL DESCRIPTION
16
8.1
17
TIMING CHARACTERISTICS
18
APPLICATION INFORMATION
18.1
18.3
18.4
18.5
8-bit operation, 1-line display using internal
reset
4-bit operation, 1-line display using internal
reset
8-bit operation, 2-line display
I2C operation, 1-line display
Initializing by instruction
19
BONDING PAD LOCATIONS
20
PACKAGE OUTLINE
21
SOLDERING
22
DEFINITIONS
23
LIFE SUPPORT APPLICATIONS
24
PURCHASE OF PHILIPS I2C COMPONENTS
8.19
LCD supply voltage generator, PCF2114x and
PCF2116x
LCD supply voltage generator, PCF2116K
Character generator ROM (CGROM)
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Registers
Busy Flag
Address Counter (AC)
Display data RAM (DDRAM)
Character generator ROM (CGROM)
Character generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Programming MUX 1 : 16 displays with the
PCF2114x
Programming MUX 1 : 32 displays with the
PCF2114x
Reset function
9
INSTRUCTIONS
9.1
9.2
Clear display
Return home
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
1997 Apr 07
18.2
2
Philips Semiconductors
Product specification
LCD controller/drivers
1
PCF2116 family
3
FEATURES
• Single chip LCD controller/driver
GENERAL DESCRIPTION
The PCF2116 family of LCD controller/drivers consists of
the PCF2116x, the PCF2114x and the PCF2116K.
The term ‘PCF2116’ is used to refer to all devices for
common information. Specific information is given in
separate paragraphs.
• 1 or 2-line display of up to 24 characters per line, or
2 or 4 lines of up to 12 characters per line
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese syllabary) and user defined symbols
The ‘x’ in ‘PCF2116x’ and ‘PCF2114x’ represents a
specific letter code for a character set in the character
generator ROM (CGROM). The different character sets
currently available are specified by the letters A, C, and G
(see Figs 8 to 10). Other character sets are available on
request.
• On-chip:
– generation of LCD supply voltage (external supply
also possible)
– generation of intermediate LCD bias voltages
– oscillator requires no external components (external
clock also possible)
The PCF2116 is a low-power CMOS LCD controller and
driver, designed to drive a split screen dot matrix LCD
display of 1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with 5 × 8 dot format. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages,
resulting in a minimum of external components and lower
system power consumption. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. The PCF2116 interfaces to most
microcontrollers via a 4 or 8-bit bus or via the 2-wire
I2C-bus. To allow partial VDD shutdown the ESD protection
system of the SCL and SDA pins does not use a diode
connected to VDD.
• Display data RAM: 80 characters
• Character generator ROM: 240 characters
• Character generator RAM: 16 characters
• 4 or 8-bit parallel bus or 2-wire I2C-bus interface
• CMOS/TTL compatible
• 32 row, 60 column outputs
• MUX rates 1 : 32 and 1 : 16
• Uses common 11 code instruction set
• Logic supply voltage range, VDD − VSS: 2.5 to 6 V
• Display supply voltage range, VDD − VLCD: 3.5 to 9 V
• Low power consumption
The PCF2116K differs from the other members of the
family in that:
• I2C-bus address: 011101 SA0.
• VLCD/VOP generation is different (see Section 8.1)
2
• It is available with character set C only (see Fig.9).
APPLICATIONS
• Telecom equipment
• Portable instruments
• Point-of-sale terminals.
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER(1)
NAME
PCF2116xU/10
−
chip on flexible film carrier
−
PCF2114xU/10
−
chip on flexible film carrier
−
PCF2116xU/12
−
chip with bumps on flexible film carrier
−
−
chip with bumps on flexible film carrier
PCF2114xU/12
PCF2116xHZ
DESCRIPTION
LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm
Note
1. The letter ‘x’ in the type number represents the letter of the required built-in character set: A, C or G.
1997 Apr 07
3
VERSION
−
SOT425-1
Philips Semiconductors
Product specification
LCD controller/drivers
5
PCF2116 family
BLOCK DIAGRAM
handbook, full pagewidth
C1 to C60
R1 to R32
84 to 77, 115 to 122
76 to 69, 123 to 128,
1 and 4
68, 65 to 38
35 to 5
60
BIAS
VOLTAGE
GENERATOR
V LCD
32
COLUMN DRIVERS
ROW DRIVERS
60
6
93, 95, 97
32
SHIFT REGISTER
32-BIT
DATA LATCHES
60
V LCD
SHIFT REGISTER
5 x 12-bit
GENERATOR
5
V0
VDD
V SS
T1
92
PCF2116
CURSOR + DATA CONTROL
5
104, 106
CHARACTER
GENERATOR
RAM
(CGRAM)
16
CHARACTERS
109, 112
111
CHARACTER
GENERATOR
ROM
(CGROM)
240
CHARACTERS
OSCILLATOR
102
TIMING
GENERATOR
8
DISPLAY DATA RAM
(DDRAM) 80 CHARACTERS
7
7
DISPLAY
ADDRESS
COUNTER
ADDRESS
COUNTER (AC)
7
POWER - ON
RESET
INSTRUCTION
DECODER
8
8
DATA
REGISTER (DR)
BUSY
FLAG
8
INSTRUCTION
REGISTER (IR)
7
8
I/O BUFFER
4
105, 103,
98, 96
4
94, 91,
89, 87
108
110
113
88
90
107
MGA797 - 1
DB0 to DB3
DB4 to DB7 E
RS
R/W
SCL
SDA
SA0
Fig.1 Block diagram (pin numbers for LQFP128 package).
1997 Apr 07
4
OSC
Philips Semiconductors
Product specification
LCD controller/drivers
6
PCF2116 family
PINNING
SYMBOL
LQFP128
FFC PAD
TYPE
R31
1
27
O
LCD row driver output
n.c.
2 and 3
−
−
not connected
R32
4
28
O
LCD row driver output
C60 to C30
n.c.
C29 to C2
n.c.
C1
DESCRIPTION
5 to 35
29 to 59
O
LCD column driver outputs 60 to 30
36 and 37
−
−
not connected
38 to 65
60 to 87
O
LCD column driver outputs 29 to 2
66 and 67
−
−
not connected
68
88
O
LCD column driver output 1
R24 to R17
69 to 76
89 to 96
O
LCD row driver outputs
R8 to R1
77 to 84
97 to 104
O
LCD row driver outputs
not connected
n.c.
85 and 86
−
−
DB7
87
105
I/O
SCL
88
106
I
DB6
89
107
I/O
1 bit of 8-bit bidirectional data bus
SDA
90
108
I/O
I2C-bus serial data input/output
DB5
91
109
I/O
1 bit of 8-bit bidirectional data bus
V0
92
110
I
VLCD1
93
111
I/O
LCD supply voltage input/output 1
DB4
94
112
I/O
1 bit of 8-bit bidirectional data bus
VLCD2
95
113
I/O
LCD supply voltage input/output 2
DB3
96
114
I/O
1 bit of 8-bit bidirectional data bus
VLCD3
97
115
I/O
LCD supply voltage input/output 3
DB2
98
116
I/O
1 bit of 8-bit bidirectional data bus
n.c.
99 to 101
−
−
not connected
OSC
102
1
I
oscillator/external clock input
DB1
103
2
I/O
1 bit of 8-bit bidirectional data bus
I2C-bus serial clock input
control input for VLCD
1 bit of 8-bit bidirectional data bus
VDD2
104
3
P
DB0
105
4
I/O
VDD1
106
5
P
supply voltage 1
SA0
107
6
I
I2C-bus address pin
E
108
7
I
data bus clock input (parallel control)
VSS1
109
8
P
ground (logic) 1
R/W
110
9
I
read/write input (parallel control)
T1
111
10
I
test pad (connect to VSS)
VSS2
112
11
P
ground (logic) 2
RS
113
12
I
register select input (parallel control)
n.c.
114
−
−
not connected
R9 to R16
115 to 122
13 to 20
O
LCD row driver outputs
R25 to R30
123 to 128
21 to 26
O
LCD row driver outputs
1997 Apr 07
5
supply voltage 2
1 bit of 8-bit bidirectional data bus
Philips Semiconductors
Product specification
103 DB1
105 DB0
104 VDD2
107 SA0
106 VDD1
R31
1
102 OSC
n.c.
2
101 n.c.
n.c.
3
100 n.c.
R32
4
99 n.c.
C60
5
C59
6
98 DB2
97 VLCD3
C58
7
96 DB3
C57
8
C56
9
95 VLCD2
94 DB4
C55
10
93
VLCD1
C54
11
92
V0
C53 12
91
DB5
C52
C51
13
90
14
89
SDA
DB6
C50
15
88
SCL
C49
16
87
DB7
C48
17
86
n.c.
C47
18
85
n.c.
C46
19
84
R1
C45
20
83
R2
C44
21
82
R3
C43 22
81
R4
C42 23
80
R5
C41 24
C40 25
79
R6
78
R7
C39 26
77
R8
C38 27
76
R17
C37 28
75
R18
C36 29
74
R19
C35 30
73
R20
C34 31
72
R21
C33 32
71
R22
C32 33
70
R23
C31 34
69
R24
C30 35
68
C1
n.c. 36
67
n.c.
n.c. 37
66
n.c.
C29 38
65
C2
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
49
C18
C17 50
48
C19
C20 47
C21 46
C22 45
C23 44
C24 43
C25 42
C26 41
C27 40
C28 39
PCF2116
Fig.2 Pin configuration (LQFP128).
1997 Apr 07
108 E
110 R/W
109 VSS1
111 T1
113 RS
112 VSS2
114 n.c.
115 R9
118 R12
117 R11
116 R10
119 R13
120 R14
121 R15
122 R16
PCF2116 family
123 R25
124 R26
125 R27
126 R28
128 R30
handbook, full pagewidth
127 R29
LCD controller/drivers
6
MBD451 - 1
Philips Semiconductors
Product specification
LCD controller/drivers
7
7.1
PCF2116 family
7.9
PIN FUNCTIONS
OSC: oscillator
When the on-chip oscillator is used this pin must be
connected to VDD. An external clock signal, if used, is input
at this pin.
RS: register select (parallel control)
RS selects the register to be accessed for read and write
when the device is controlled by the parallel interface.
RS = logic 0 selects the instruction register for write and
the Busy Flag and Address Counter for read. RS = logic 1
selects the data register for both read and write. There is
an internal pull-up on pin RS.
7.10
Input for the I2C-bus clock signal.
7.11
7.2
R/W: read/write (parallel control)
7.12
E: data bus clock
7.13
DB0 to DB7: data bus
V0 is a high-impedance input and draws no current from
the system power supply. Its range is between VSS and
VDD − 1 V. When V0 is connected to VDD the generator is
switched off and an external voltage must be supplied to
pin VLCD. This may be more negative than VSS.
C1 to C60: column driver outputs
When G = logic 1 the generator produces a negative
voltage at pin VLCD, controlled by the input voltage at
pin V0. The LCD operating voltage is given by the
relationship:
VOP = 1.8VDD − V0
R1 to R32: row driver outputs
Where:
These pins output the row select waveforms to the left and
right halves of the display.
VOP = VDD − VLCD
VLCD = V0 − (0.8VDD)
VLCD: LCD power supply
When G = logic 0, the generated output voltage VLCD is
equal to V0 (between VSS and VDD). In this instance:
Negative power supply for the liquid crystal display.
This may be generated on-chip or supplied externally.
7.8
VOP = VDD − V0
When VLCD is generated on-chip the VLCD pin should be
decoupled to VDD with a suitable capacitor. VDD and V0
must be selected to limit the maximum value of VOP to 9 V.
V0: VLCD control input
The input level at this pin determines the generated VLCD
output voltage.
1997 Apr 07
LCD supply voltage generator, PCF2114x and
PCF2116x
The on-chip voltage generator is controlled by bit G of the
‘Function set’ instruction and V0.
These pins output the data for pairs of columns.
This arrangement permits optimized chip-on-glass (COG)
layout for 4-line by 12 characters.
7.7
FUNCTIONAL DESCRIPTION (see Fig.1)
8.1
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2116. DB7 may be used
as the Busy Flag, signalling that internal operations are not
yet completed. In 4-bit operations the 4 higher order lines
DB4 to DB7 are used; DB0 to DB3 must be left open
circuit. There is an internal pull-up on each of the data
lines. Note that these pins must be left open circuit when
I2C-bus control is used.
7.6
T1: test pad
Must be connected to VSS. Not user accessible.
8
7.5
SA0: address pin
The hardware sub-address line is used to program the
device sub-address for 2 different PCF2116s on the same
I2C-bus.
The E pin is set HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied
to logic 0 (VSS) when I2C-bus control is used.
7.4
SDA: serial data line
Input/output for the I2C-bus data line.
R/W selects either the read (R/W = logic 1) or write
(R/W = logic 0) operation when control is by the parallel
interface. There is an internal pull-up on this pin.
7.3
SCL: serial clock line
Figure 3 shows the two generator control characteristics.
7
Philips Semiconductors
Product specification
LCD controller/drivers
8.2
PCF2116 family
LCD supply voltage generator, PCF2116K
8.5
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to VDD.
In the PCF2116K version, V0 is connected through an
on-chip resistor (R0) to VLCD. Resistor R0 has a nominal
value of 1 MΩ and draws a typical current of 4 µA from the
pin V0. A constant voltage (equal to 1.34VDD) is always
present across R0.
8.6
The voltage range of the PCF2116K is between VSS and
VDD − 0.5 V (see Fig.4). When V0 is connected to VDD the
generator is switched off and an external voltage must be
supplied to pin VLCD. This may be more negative than VSS.
If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
fframe = 1⁄2304fosc . A clock signal must always be present,
otherwise the LCD may be frozen in a DC state.
When G = logic 1 the generator produces a negative
voltage at pin VLCD, controlled by the input voltage at
pin V0. The LCD operating voltage is given by the
relationship:
8.7
External clock
Power-on reset
The power-on reset block initializes the chip after
power-on or power failure.
VOP = 2.34VDD − V0
8.8
Where:
The PCF2116 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed.
VOP = VDD − VLCD
VLCD = V0 − (1.34VDD)
When G = logic 0, the generated output voltage VLCD is
equal to V0 (between VSS and VDD). In this instance:
The instruction register stores instruction codes such as
‘Display clear’ and ‘Cursor shift’, and address information
for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be
written to, but not read, by the system controller.
VOP = VDD − V0
8.3
Character generator ROM (CGROM)
The standard character sets A, C and G are available for
the PCF2114x and PCF2116x. Standard character set C is
available for the PCF2116K.
8.4
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM corresponding to the address in the
Address Counter is written to the data register prior to
being read by the ‘Read data’ instruction.
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.
8.9
Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2116. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output to pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is logic 0 or waiting for the required number of
clock cycles.
The optimum value of VOP depends on the multiplex rate,
the LCD threshold voltage (Vth) and the number of bias
levels and is given by the relationships in Table 1.Using a
5-level bias scheme for 1 : 16 MUX rate allows VOP < 5 V
for most LCD liquids. The effect on the display contrast is
negligible.
Table 1
Registers
Optimum values for VOP
MUX RATE
NUMBER OF BIAS
LEVELS
VOP/Vth
DISCRIMINATION
Von/Voff
1 : 16
5
3.67
1.277
1 : 32
6
5.19
1.196
1997 Apr 07
8
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
9
9V
VOP
VOP(max) = 1.8 x V DD
8
6 = VDD
7
G=1
5
6
4
5
3
4
3.5
VOP(min) = 0.8 x VDD 1
2.5
0
1
2
3
4
5
V0
6
MGA798
a. High-voltage mode VOP = 1.8VDD − V0.
9
VOP
8
7
G=0
6
5
6 = VDD
5
4
3.5
4
0
1
2
3
4
5
V0
6
MGA799
b. Buffer mode VOP = VDD − V0.
Fig.3 VOP as a function of V0 control characteristics.
1997 Apr 07
9
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
9
9V
6
VOP
8
5
7
G=1
4 = VDD
6
5
3
VOP(min) = 1.34 × VDD + 0.5
2.5
4
3.5
0
1
2
3
4
5
V0
6
MBH667
a. High-voltage mode VOP = 2.34VDD − V0.
9
VOP
8
7
G=0
6
5
6 = VDD
5
4
3.5
4
0
1
2
3
4
5
V0
6
MGA799
b. Buffer mode VOP = VDD − V0.
Fig.4 VOP as a function of V0 control characteristics (PCF2116K).
1997 Apr 07
10
Philips Semiconductors
Product specification
LCD controller/drivers
8.10
PCF2116 family
Address Counter (AC)
8.13
The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1.The Address Counter contents are
output to the bus (DB0 to DB6) when RS = logic 0 and
R/W = logic 1.
8.11
Up to 16 user-defined characters may be stored in the
character generator RAM. The CGROM and CGRAM use
a common address space, of which the first column is
reserved for the CGRAM (see Fig.8). Figure 11 shows the
addressing principle for the CGRAM.
8.14
Display data RAM (DDRAM)
8.15
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
8.16
LCD row and column drivers
The PCF2116 contains 32 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 13 and 14 show typical waveforms.
The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively.
For 2 and 4-line displays the end address of one line and
the start address of the next line are not consecutive.
When the display is shifted each line wraps around
independently of the others (Figs 6 and 7).
In 1-line mode (1 : 16) the row outputs are driven in pairs:
R1/R17, R2/R18 for example. This allows the output pairs
to be connected in parallel, providing greater drive
capability.
When data is written into the DDRAM wrap-around occurs
from 4F to 00 in 1-line mode and from 27 to 40 and
67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line mode.
Unused outputs should be left unconnected.
Character generator ROM (CGROM)
The character generator ROM generates 240 character
patterns in 5 × 8 dot format from 8-bit character codes.
Figures 8 to 10 show the character sets currently
available.
1997 Apr 07
Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.12) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.
The display data RAM stores up to 80 characters of
display data represented by 8-bit character codes.
RAM locations not used for storing display data can be
used as general purpose RAM. The basic
DDRAM-to-display mapping scheme is shown in Fig.5.
With no display shift the characters represented by the
codes in the first 12 or 24 RAM locations starting at
address 00 in line 1 are displayed. Subsequent lines
display data starting at addresses 20, 40, or 60 Hex.
Figs 6 and 7 show the DDRAM-to-display mapping
principle when the display is shifted.
8.12
Character generator RAM (CGRAM)
11
Philips Semiconductors
Product specification
LCD controller/drivers
Display
handbook,
4 columns
Position
(decimal)
1
2
PCF2116 family
3
4
5
00 01 02 03 04
DDRAM
Address
(hex)
non-displayed DDRAM addresses
22 23 24
15 16 17 18 19
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
DDRAM
Address
(hex)
00 01 02 03 04
15 16 17 18 19
24 25 26 27
line 1
40 41 42 43 44
55 56 57 58 59
64 65 66 67
line 2
MLA792
2-line display
non-displayed DDRAM addresses
handbook, 4 columns
1
2
3
4
5
6
7
8
9 10 11 12
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
line 1
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
line 2
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
line 4
DDRAM
Address
(hex)
4 line display
MLA793
Fig.5 DDRAM-to-display mapping; no shift.
1997 Apr 07
12
Philips Semiconductors
Product specification
LCD controller/drivers
Display
Position
(decimal)
DDRAM
Address
(hex)
DDRAM
Address
(hex)
1
2 3
4
5
PCF2116 family
Display
Position
(decimal)
22 23 24
4F 00 01 02 03
14 15 16
DDRAM
Address
(hex)
1-line display
27 00 01 02 03
14 15 16
line 1
67 40 41 42 43
54 55 56
line 2
2 3
4
22 23 24
16 17 18
1-line display
01 02 03 04 05
16 17 18
line 1
41 42 43 44 45
56 57 58
line 2
2-line display
1 2
8 9 10 11 12
MLA815
3 4 5 6 7 8 9 10 11 12
13 00 01 02 03 04 05 06 07 08 09 0A
line 1
01 02 03 04 05 06 07 08 09 0A 0B 0C
line 1
33 20 21 22 23 24 25 26 27 28 29 2A
line 2
21 22 23 24 25 26 27 28 29 2A 2B 2C
line 2
DDRAM
DDRAM
Address
(hex)
Address
(hex)
53 40 41 42 43 44 45 46 47 48 49 4A
line 3
41 42 43 44 45 46 47 48 49 4A 4B 4C
line 3
73 60 61 62 63 64 65 66 67 68 69 6A
line 4
61 62 63 64 65 66 67 68 69 6A 6B 6C
line 4
4-line display
MLA803
4-line display
Fig.6 DDRAM-to-display mappi7ng; right shift.
1997 Apr 07
5
01 02 03 04 05
MLA802
2-line display
1 2 3 4 5 6 7
DDRAM
Address
(hex)
1
MLA816
Fig.7 DDRAM-to-display mapping; left shift.
13
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
6 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MLB245 - 1
Fig.8 Character set ‘A’ in CGROM: PCF2116A; PCF2114A.
1997 Apr 07
14
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
CG
RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MLB895
Fig.9 Character set ‘C’ in CGROM: PCF2116C; PCF2114C.
1997 Apr 07
15
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
CG
RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
6 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MLB896
Fig.10 Character set ‘G’ in CGROM: PCF2116G; PCF2114G.
1997 Apr 07
16
Philips Semiconductors
Product specification
LCD controller/drivers
character codes
(DDRAM data)
handbook, full pagewidth
7
6
5
4
3
2
higher
order
bits
0
0
PCF2116 family
0
0
0
0
CGRAM
address
1
0
6
lower
order
bits
0
0
0
0
0
0
0
0
5
4
3
2
higher
order
bits
0
1
0
0
0
0
0
0
character patterns
(CGRAM data)
1
0
lower
order
bits
0
1
4
3
higher
order
bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
1
0
lower
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
character
pattern
example 1
character
pattern
example 2
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.11 (bit 4 being at the left end).
As shown in Figs 8 and 11, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1
corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction
or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.
Fig.11 Relationship between CGRAM addresses and data and display patterns.
1997 Apr 07
17
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
cursor
MGA801
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.12 Cursor and blink display examples.
1997 Apr 07
18
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
frame n
handbook, full pagewidth
frame n 1
state 1 (ON)
state 2 (ON)
VDD
V2
V3 /V4
V5
V LCD
ROW 1
VDD
V2
ROW 9
V3 /V4
V5
V LCD
1-line display
(1:16)
VDD
V2
V3 /V4
V5
V LCD
ROW 2
VDD
V2
V3 /V4
V5
V LCD
COL 1
VDD
V2
V3 /V4
V5
V LCD
COL 2
VOP
0.25 VOP
state 1 0 V
0.25 VOP
VOP
VOP
0.25 VOP
state 2 0 V
0.25 VOP
VOP
MGA802 - 1
1 2 3
16 1 2 3
Fig.13 Typical LCD waveforms; 1-line mode.
1997 Apr 07
19
16
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
frame n 1
frame n
handbook, full pagewidth
ROW 1
V DD
V2
V3
V4
V5
V LCD
ROW 9
V DD
V2
V3
V4
V5
V LCD
ROW 2
V DD
V2
V3
V4
V5
V LCD
COL 1
V DD
V2
V3
V4
V5
V LCD
COL 2
V DD
V2
V3
V4
V5
V LCD
state 1 (ON)
state 2 (ON)
2-line display
(1:32)
VOP
state 1
0.15 VOP
0V
0.15 VOP
VOP
VOP
state 2
0.15 VOP
0V
0.15 VOP
VOP
MGA803 - 1
123
32 1 2 3
Fig.14 Typical LCD waveforms; 2-line mode.
1997 Apr 07
20
32
Philips Semiconductors
Product specification
LCD controller/drivers
8.17
PCF2116 family
With the ‘Function set’ instruction M and N are set to 0, 0.
Figures 15 to 17 show DDRAM addresses of the display
characters. The second row of each table corresponds to
either the right half of a 1-line display or to the second line
of a 2-line display. Wrap around of data during display shift
or when writing data is non-standard.
Programming MUX 1 : 16 displays with the
PCF2114x
The PCF2114x can be used in:
• 1-line mode to drive a 2-line display
• 2 × 12 characters with MUX rate 1 : 16, resulting in
better contrast. The internal data flow of the chip is
optimized for this purpose.
handbook, full pagewidth
display position
1
2
3
4
5
6
7
8
9
10
11
12
DDRAM address
00
01
02
03
04
05
06
07
08
09
0A
0B
display position
13
14
15
16
17
18
19
20
21
22
23
24
DDRAM address
0C
0D
0E
0F
10
11
12
13
14
15
16
17
MLB899
Fig.15 DDRAM-to-display mapping; no shift (PCF2114x).
handbook, full pagewidth
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
11
12
4F
00
01
02
03
04
05
06
07
08
09
0A
display position
13
14
15
16
17
18
19
20
21
22
23
24
DDRAM address
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
MLB900
Fig.16 DDRAM-to-display mapping; right shift (PCF2114x).
handbook, full pagewidth
display position
1
2
3
4
5
6
7
8
9
10
11
12
DDRAM address
01
02
03
04
05
06
07
08
09
0A
0B
0C
24
display position
13
14
15
16
17
18
19
20
21
22
23
DDRAM address
0D
0E
0F
10
11
12
13
14
15
16
17
18
MLB901
Fig.17 DDRAM-to-display mapping; left shift (PCF2114x).
1997 Apr 07
21
Philips Semiconductors
Product specification
LCD controller/drivers
8.18
PCF2116 family
Programming MUX 1 : 32 displays with the
PCF2114x
9
INSTRUCTIONS
Only two PCF2116 registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow
interface to various types of microcontrollers which
operate at different speeds or to allow interface to
peripheral control ICs.
The PCF2116 operation is controlled by the instructions
shown in Table 3 together with their execution time.
Details are explained in subsequent sections.
To drive a 2-line by 24 characters MUX 1 : 32 display, use
instruction ‘Function set’ M, N to 0, 1. Note that the right
half of the display needs mirrored column connection
compared to a display driven by a PCF2116x.
To drive a 4-line by 12 characters MUX 1 : 32 display the
PCF2116x operating instructions apply. There is no
functional difference between the PCF2114x and the
PCF2116x in this mode. For such an application
set M, N to 1, 1 with the ‘Function set’ instruction.
Instructions are of 4 categories, those that:
8.19
Reset function
1. Designate PCF2116 functions such as display format,
data length, etc.
The PCF2116 automatically initializes (resets) when
power is turned on. After reset the chip has the following
state.
Table 2
4. Others.
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1 (or
decrementing by 1) of internal RAM addresses after each
data write lessens the microcontroller program load. The
display shift in particular can be performed concurrently
with display data write, enabling the designer to develop
systems in minimum time with maximum programming
efficiency.
DESCRIPTION
1
display clear
2
function set
4
3. Perform data transfer with internal RAM
State after reset
STEP
3
2. Set internal RAM addresses
display on/off
control
entry mode set
DL = 1
8-bit interface
M, N = 0
1-line display
G=0
voltage
generator;
VLCD = V0
D=0
display off
C=0
cursor off
B=0
blink off
I/D = 1
+1 (increment)
S=0
no shift
5
Default address pointer to DDRAM. The Busy
Flag (BF) indicates the busy state (BF = logic 1)
until initialization ends. The busy state lasts
2 ms. The chip may also be initialized by
software. See Figs 28 and 29.
6
I2C-bus interface reset
1997 Apr 07
During internal operation, no instruction other than
‘Read busy flag and address’ will be executed.
Because the Busy Flag is set to logic 1 while an instruction
is being executed, check to make sure it is on logic 0
before sending the next instruction or wait for the
maximum instruction execution time, as given in Table 3.
An instruction sent while the Busy Flag is HIGH will not be
executed.
22
INSTRUCTION
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES(2)
0
0
0
0
0
0
0
0
0
0
No operation.
Clear display
0
0
0
0
0
0
0
0
0
1
Clears entire display and sets DDRAM
address 0 in Address Counter.
Return Home
0
0
0
0
0
0
0
0
1
0
Sets DDRAM address 0 in Address Counter.
Also returns shifted display to original position.
DDRAM contents remain unchanged.
3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
Sets cursor move direction and specifies shift
of display. These operations are performed
during data write and read.
3
Display control
0
0
0
0
0
0
1
D
C
B
Sets entire display on/off (D), cursor on/off (C)
and blink of cursor position character (B).
3
Cursor/display
shift
0
0
0
0
0
1
S/C
R/L
0
0
Moves cursor and shifts display without
changing DDRAM contents.
3
Function set
0
0
0
0
1
DL
N
M
G
0
Sets interface data length (DL), number of
display lines (N, M) and voltage generator
control (G).
3
Set CGRAM
address
0
0
0
1
Sets CGRAM address.
3
Set DDRAM
address
0
0
1
ADD
Sets DDRAM address.
3
Read busy flag
and address
0
1
BF
AC
Reads Busy Flag (BF) indicating internal
operation is being performed and reads
Address Counter contents.
0
Read data
1
1
read data
Reads data from CGRAM or DDRAM.
3
Write data
1
0
write data
Writes data to CGRAM or DDRAM.
3
23
NOP
ACG
0
165
In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.
1
2. Example: fosc = 150 kHz, T cy = --------- = 6.67 µs; 3 cycles = 20 µs, 165 cycles = 1.1 ms.
f osc
Product specification
1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed.
PCF2116 family
Notes
Philips Semiconductors
Instructions (note 1)
LCD controller/drivers
1997 Apr 07
Table 3
Philips Semiconductors
Product specification
LCD controller/drivers
Table 4
PCF2116 family
Command bit identities
BIT
0
1
I/D
decrement
increment
S
display freeze
display shift
D
display off
display on
C
cursor off
cursor on
B
character at cursor position does not blink
character at cursor position blinks
S/C
cursor move
display shift
R/L
left shift
right shift
DL
4 bits
8 bits
G
voltage generator: VLCD = V0
voltage generator; VLCD = V0 − 0.8VDD
PCF2116x
1 line × 24 characters; MUX 1 : 16
2 lines × 24 characters; MUX 1 : 32
PCF2114x
2 line × 12 characters; MUX 1 : 16
2 lines × 24 characters; MUX 1 : 32
N, (M = 0)
N, (M = 1)
reserved
4 lines × 12 characters; MUX 1 : 32
BF
end of internal operation
internal operation in progress
Co
last control byte, only data bytes to follow
next two bytes are a data byte and another
control byte
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
instruction
write
busy flag and
address counter read
Fig.18 4-bit transfer example.
1997 Apr 07
24
data register
read
MGA804
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
instruction
write
not
busy
AC3
busy flag
check
AC3
D7
busy flag
check
D3
instruction
write
MGA805
IR7, IR3: instruction 7th bit, 3rd bit.
AC3: Address Counter 3rd bit.
Fig.19 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
DB7
internal operation
data
instruction
write
busy
busy flag
check
busy
busy flag
check
not
busy
busy flag
check
Fig.20 Example of Busy Flag check timing sequence.
1997 Apr 07
25
data
instruction
write
MGA806
Philips Semiconductors
Product specification
LCD controller/drivers
9.1
PCF2116 family
Clear display
9.4.2
‘Clear display’ writes space code 20 (hexadecimal) into all
DDRAM addresses (The character pattern for character
code 20 must be blank pattern). Sets the DDRAM Address
Counter to logic 0. Returns display to its original position if
it was shifted. Thus, the display disappears and the cursor
or blink position goes to the left edge of the display
(the first line if 2 or 4 lines are displayed). Sets entry mode
I/D = logic 1 (increment mode). S of entry mode does not
change.
C
The cursor is displayed when C = logic 1 and inhibited
when C = logic 0. Even if the cursor disappears, the
display functions I/D, etc. remain in operation during
display data write. The cursor is displayed using 5 dots in
the 8th line (see Fig.12).
9.4.3
B
The instruction ‘Clear display’ requires extra execution
time. This may be allowed for by checking the busy-flag
(BF) or by waiting until 2 ms has elapsed. The latter must
be applied where no read-back options are foreseen, as in
some chip-on-glass (COG) applications.
The character indicated by the cursor blinks when
B = logic 1. The blink is displayed by switching between
display characters and all dots on with a period of
1 second when fosc = 150 kHz (see Fig.12). At other clock
frequencies the blink period is equal to 150 kHz/fosc.
The cursor and the blink can be set to display
simultaneously.
9.2
9.5
Return home
‘Return home’ sets the DDRAM Address Counter to
logic 0. Returns display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the display (the first line if 2
or 4 lines are displayed). I/D and S of entry mode do not
change.
9.3
9.3.1
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2 or 4-line displays, the
cursor moves to the next line when it passes the last
position (40 or 20 decimal) of the line. When the displayed
data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the cursor shift.
Entry mode set
I/D
When I/D = logic 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor and blink are inhibited
when the CGRAM is accessed.
9.3.2
9.6
9.6.1
9.4.1
S
DL (PARALLEL MODE ONLY)
Data is sent or received in bytes (bits DB7 to DB0) when
DL = logic 1, or in two 4-bit nibbles (DB7 to DB4) when
DL = logic 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus(1).
When using the I2C-bus interface the DL should not
previously have been set to 0 using the parallel interface.
9.6.2
Display on/off control
N, M
Sets number of display lines.
D
The display is on when D = logic 1 and off when
D = logic 0. Display data in the DDRAM are not affected
and can be displayed immediately by setting D to logic 1.
1997 Apr 07
Function set
Defines interface data width when the parallel data
interface is used.
When S = logic 1, the entire display shifts either to the right
(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM
write. Thus it looks as if the cursor stands still and the
display moves. The display does not shift when reading
from the DDRAM, or when writing into or reading out of the
CGRAM. When S = logic 0 the display does not shift.
9.4
Cursor/display shift
(1) In a 4-bit application DB3 to DB0 are left open (internal
pull-ups). Hence in the first ‘Function set’ instruction after
power-on, G and H are set to 1. A second ‘Function set’ must
then be sent (2 nibbles) to set G and H to their required
values.
26
Philips Semiconductors
Product specification
LCD controller/drivers
9.6.3
PCF2116 family
After writing, the address automatically increments or
decrements by 1, in accordance with the entry mode.
Only bits D[4] to D[0] of CGRAM data are valid, bits
D[7] to D[5] are ‘don’t care’.
G
Controls the VLCD voltage generator characteristic.
9.7
Set CGRAM address
9.11
‘Set CGRAM address’ sets bit 0 to 5 of the CGRAM
address (ACG in Table 3) into the Address Counter
(binary A[5] to A[0]). Data can then be written to or read
from the CGRAM.
Reads binary 8-bit data D[7] to D[0] from the CGRAM or
DDRAM.
The most recent ‘Set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
Only bits 0 to 5 of the CGRAM address are set by the
‘Set CGRAM address’ instruction. Bit 6 can be set using
the ‘Set DDRAM address’ instruction or by using the
auto-increment feature during CGRAM write. All bits 0 to 6
can be read using the ‘Read busy flag and address’
instruction.
9.8
The ‘Read data’ instruction gates the content of the data
register (DR) to the bus while E = HIGH. After E goes LOW
again, internal operation increments (or decrements) the
AC and stores RAM data corresponding to the new AC into
the DR.
Set DDRAM address
Remark: the only three instructions that update the data
register (DR) are:
‘Set DDRAM address’ sets the DDRAM address (ADD in
Table 3) into the Address Counter (binary A[6] to A[0]).
Data can then be written to or read from the DDRAM.
• ‘Set CGRAM address’
• ‘Set DDRAM address’
• ‘Read data’ from CGRAM or DDRAM.
Hexadecimal address ranges.
ADDRESS
Other instructions (e.g. ‘Write data’, ‘Cursor/Display shift’,
‘Clear display’, ‘Return home’) will not modify the data
register content.
FUNCTION
00 to 4F
1-line by 24; 2114x/2116x
00 to 0B and 0C to 4F
2-line by 12; 2114x
00 to 27 and 40 to 67
2-line by 24; 2114x/2116x
00 to 13, 20 to 33, 40 to 53
and 60 to 73
4-line by 12; 2114x/2116x
9.9
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2116 can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
Read busy flag and address
‘Read busy flag and address’ reads the Busy Flag (BF).
BF = logic 1 indicates that an internal operation is in
progress. The next instruction will not be executed until
BF = logic 0, so BF should be checked before sending
another instruction.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB0 to DB7. Three further control lines E, RS,
and R/W are required.
In 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB4 to DB7
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB0 to DB3 in 8-bit mode) in the second.
Data transfer is complete after two 4-bit data transfers.
It should be noted that two cycles are also required for the
Busy Flag check. 4-bit operation is selected by instruction.
See Figs 18, 19 and 20 for examples of bus protocol.
At the same time, the value of the Address Counter (AC in
Table 3) expressed in binary A[6] to A[0] is read out. The
Address Counter is used by both CGRAM and DDRAM,
and its value is determined by the previous instruction.
9.10
Write data to CGRAM or DDRAM
Writes binary 8-bit data D[7] to D[0] to the CGRAM or the
DDRAM.
In 4-bit mode pins DB3 to DB0 must be left open-circuit.
They are pulled up to VDD internally.
Whether the CGRAM or DDRAM is to be written into is
determined by the previous specification of CGRAM or
DDRAM address setting.
1997 Apr 07
Read data from CGRAM or DDRAM
27
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
11.5
11 INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
11.1
Characteristics of the
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
I2C-bus
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
11.2
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
11.3
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
11.4
11.6
I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C-bus configuration for the different
PCF2116 READ and WRITE cycles is shown in
Figs 25 to 27.
System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
1997 Apr 07
Acknowledge
28
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.21 Bit transfer.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.22 Definition of START and STOP conditions.
1997 Apr 07
29
MBC622
Philips Semiconductors
Product specification
LCD controller/drivers
MASTER
TRANSMITTER/
RECEIVER
PCF2116 family
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
MGA807
Fig.23 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
START
CONDITION
MBC602
Fig.24 Acknowledgement on the I2C-bus.
1997 Apr 07
30
clock pulse for
acknowledgement
1997 Apr 07
slave address
0
R/W
Co
DATA
31
PCF2116
slave address
1 byte
CONTROL BYTE
MBH668
Co
A 0
R/W
S
0 1 1 1 0 1 A 0
0
0 bytes
A
A
n
0 bytes
DATA
update
data pointer
A P
LCD controller/drivers
Fig.25 Master transmits to slave receiver; WRITE mode.
2n
CONTROL BYTE
ull pagewidth
S 0 1 1 1 0 1 A 0 A 1
S
acknowledgement
from PCF2116
Philips Semiconductors
Product specification
PCF2116 family
S
S 0 1 1 1 0 1 A 0 A 1
CONTROL BYTE
A
DATA
A 0 1 1
CONTROL
DATA
A
(1)
Philips Semiconductors
LCD controller/drivers
1997 Apr 07
acknowledgement
from PCF2116
A
0
slave address
2n
R/W
0 bytes
2 bytes
Co
Co
32
acknowledgement
from PCF2116
S
SLAVE
ADDRESS
S
A 1 A
0
no acknowledgement
from master
DATA
n bytes
A
DATA
1 P
last byte
R/W
MGA809 - 1
Product specification
Fig.26 Master reads after setting word address; write word address, set RS/RW; READ data.
PCF2116 family
(1) Last data byte is a dummy byte (may be omitted).
handbook, full pagewidth
update
data pointer
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
acknowledgement
from PCF2116
handbook, full pagewidth
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
from master
DATA
A
n bytes
no acknowledgement
from master
DATA
1 P
last byte
R/W
update
data pointer
MGA810 - 1
Fig.27 Master reads slave immediately after first byte; READ mode (RS previously defined).
1997 Apr 07
33
1997 Apr 07
SCL
SDA
PROTOCOL
t BUF
34
t HD;STA
t LOW
BIT 7
MSB
(A7)
t HIGH
tr
tf
t/fSCL
BIT 6
(A6)
BIT 0
LSB
R/W
ACKNOWLEDGE
(A)
Fig.28 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
START
CONDITION
(S)
MGA811 - 1
STOP
CONDITION
(P)
t SU;STO
LCD controller/drivers
handbook, full pagewidth
Philips Semiconductors
Product specification
PCF2116 family
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
12 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+8.0
V
VLCD
LCD supply voltage
VDD − 11
VDD
V
VI
input voltage OSC, V0, RS, R/W, E and DB0 to DB7
VSS − 0.5
VDD + 0.5
V
VO
output voltage R1 to R32, C1 to C60 and VLCD
VLCD − 0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS, ILCD VDD, VSS or VLCD current
−50
+50
mA
Ptot
total power dissipation
−
400
mW
PO
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
13 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1997 Apr 07
35
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
14 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
6.0
V
VLCD
LCD supply voltage
VDD − 9
−
VDD − 3.5
V
IDD
supply current external VLCD
note 1
IDD1
supply current 1
−
200
500
µA
IDD2
supply current 2
VDD = 5 V; VOP = 9 V;
fosc = 150 kHz;
Tamb = 25 °C
−
200
300
µA
IDD3
supply current 3
VDD = 3 V; VOP = 5 V;
fosc = 150 kHz;
Tamb = 25 °C
−
150
200
µA
IDD
supply current internal VLCD
notes 1, 2 and 8
IDD4
supply current 4
−
700
1100
µA
IDD5
supply current 5
VDD = 5 V; VOP = 9 V;
fosc = 150 kHz;
Tamb = 25 °C
−
600
900
µA
IDD6
supply current 6
VDD = 3 V; VOP = 5 V;
fosc = 150 kHz;
Tamb = 25 °C
−
500
800
µA
ILCD
VLCD input current
notes 1 and 7
−
50
100
µA
VPOR
power-on reset voltage level
note 3
−
1.3
1.8
V
Logic
VIL1
LOW level input voltage E, RS,
R/W, DB0 to DB7 and SA0
VSS
−
0.3VDD
V
VIH1
HIGH level input voltage E, RS,
R/W, DB0 to DB7 and SA0
0.7VDD
−
VDD
V
VIL(osc)
LOW level input voltage OSC
VSS
−
VDD − 1.5
V
VIH(osc)
HIGH level input voltage OSC
VDD − 0.1
−
VDD
V
−
VIL(V0)
LOW level input voltage V0
VSS
VDD − 0.5
V
VIH(V0)
HIGH level input voltage V0
VDD − 0.05 −
VDD
V
Ipu
pull-up current at DB0 to DB7
VI = VSS
0.04
0.15
1.00
µA
IOL(DB)
LOW level output current
DB0 to DB7
VOL = 0.4 V; VDD = 5 V 1.6
−
−
mA
IOH(DB)
HIGH level output current
DB0 to DB7
VOH = 4 V; VDD = 5 V
−1.0
−
−
mA
IL1
leakage current OSC, V0, E, RS,
R/W, DB0 to DB7 and SA0
VI = VDD or VSS
−1
−
+1
µA
1997 Apr 07
36
Philips Semiconductors
Product specification
LCD controller/drivers
SYMBOL
PARAMETER
PCF2116 family
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus
SDA, SCL
VIL2
LOW level input voltage
note 4
VSS
−
0.3VDD
V
VIH2
HIGH level input voltage
note 4
0.7VDD
−
VDD
V
IL2
leakage current
VI = VDD or VSS
−1
−
+1
µA
Ci
input capacitance
note 5
−
−
7
pF
IOL(SDA)
LOW level output current (SDA)
VOL = 0.4 V; VDD = 5 V 3
−
−
mA
LCD outputs
RROW
row output resistance R1 to R32
note 6
−
1.5
3
kΩ
RCOL
column output resistance C1 to C60 note 6
−
3
6
kΩ
Vtol1
bias voltage tolerance R1 to R32
and C1 to C60
note 7
−
±20
±130
mV
Vtol2
LCD supply voltage (VLCD)
tolerance
note 2
−
±40
±300
mV
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle
50% (IDD1 only).
2. LCD outputs are open-circuit; LCD supply voltage generator is on; load current at VLCD = 20 µA.
3. Resets all logic when VDD < VPOR.
4. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must
not exceed ±0.5 mA.
5. Tested on sample basis.
6. Resistance of output terminals (R1 to R32 and C1 to C60) with load current = 150 µA; VOP = VDD − VLCD = 9 V;
outputs measured one at a time; (external VLCD).
7. LCD outputs open-circuit; external VLCD.
8. Maximum value occurs at 85 °C.
15 DC CHARACTERISTICS (PCF2116K)
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
2.5
−
6.0
V
VLCD
LCD supply voltage
VDD − 9
−
VDD − 3.5
V
V0
voltage generator control input
voltage
VSS
−
VDD − 0.5
V
R0
voltage generator control input
resistance
700
1000
1300
kΩ
Tamb = 25 °C; note 1
Note
1. R0 has a temperature coefficient of resistance of +0.6%/K.
1997 Apr 07
37
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
16 AC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
fFR
LCD frame frequency (internal clock); note 1
40
65
100
Hz
fosc
external clock frequency
90
150
225
kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2116)
Tcy
enable cycle time
500
−
−
ns
PWEH
enable pulse width
220
−
−
ns
tASU
address set-up time
50
−
−
ns
tAH
address hold time
25
−
−
ns
tDSW
data set-up time
60
−
−
ns
tHD
data hold time
25
−
−
ns
READ OPERATION (READING DATA FROM PCF2116 TO MICROCONTROLLER)
Tcy
enable cycle time
500
−
−
ns
PWEH
enable pulse width
220
−
−
ns
tASU
address set-up time
50
−
−
ns
tAH
address hold time
25
−
−
ns
tDHD
data delay time
−
−
150
ns
tHD
data hold time
20
−
100
ns
kHz
Timing characteristics: I2C-bus interface; note 2
fSCL
SCL clock frequency
−
−
100
tSW
tolerable spike width on bus
−
−
100
ns
tBUF
bus free time
4.7
−
−
µs
tSU;STA
set-up time for a repeated START condition
4.7
−
−
µs
tHD;STA
START condition hold time
4
−
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4
−
−
µs
tr
SCL and SDA rise time
−
−
1
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
set-up time for STOP condition
4
−
−
µs
Notes
1. VDD = 5 V.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
1997 Apr 07
38
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
17 TIMING CHARACTERISTICS
book, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
t AS
R/W
t AH
V IL1
VIL1
t AH
PW EH
VIH1
VIL1
E
VIH1
VIL1
VIL1
t DSW
VIH1
Valid Data
VIL1
DB0 to DB7
tH
VIH1
VIL1
MLA798 - 1
Tcy
Fig.29 Parallel bus write operation sequence; writing data from microcontroller to PCF2116.
dbook, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
t AS
R/W
t AH
VIH1
VIH1
t AH
PW EH
E
VIL1
VIH1
VIH1
VIL1
t DHR
t DDR
DB0 to DB7
VIL1
VOH1
VOL1
VOH1
VOL1
Tcy
MLA799 - 1
Fig.30 Parallel bus read operation sequence; reading data from PCF2116 to microcontroller.
1997 Apr 07
39
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
18 APPLICATION INFORMATION
handbook, 4 columns
P20
RS
P21
R/W
P22
E
32
P80CL51
R1 to R32
to
LCD
PCF2116
60
P10 to P17
C1 to C60
DB0 to DB7
8
MGA812 - 1
Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
P10
RS
P11
R/W
P12
E
32
P80CL51
R1 to R32
to
LCD
PCF2116
60
P14 to P17
C1 to C60
DB4 to DB7
4
MGA813 - 1
Fig.32 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
R7 to R16
R25 to R32
V LCD
16
100 nF
VDD
VDD
100
nF
VSS
OSC
100
kΩ
R1 to R8
R17 to R24
PCF2116
16
2 x 24 CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
VO
C1 to C60
V SS
DB0 to DB7 E
60
60
MGA816 - 1
RS R/W
Fig.33 Typical application using parallel interface.
1997 Apr 07
40
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
V LCD
R1 to R16
16
R17 to R24
2 x 24 CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
100 nF
VDD
VDD
100
kΩ
100
nF
VDD VDD
V SS
OSC
PCF2116
16
VO
V SS
C1 to C60
60
60
SA0
VDD
V LCD
100 nF
VDD
100
nF
VDD
OSC
100
kΩ
16
2 x 12 CHARACTER
LCD DISPLAY
VO
V SS
V SS
R1 to R16
PCF2114
VSS
SCL SDA
MASTER TRANSMITTER
PCF84C81
Fig.34 Application using I2C-bus interface.
1997 Apr 07
60
C1 to C60
SA0
41
MGA817 - 1
Philips Semiconductors
Product specification
LCD controller/drivers
18.1
PCF2116 family
8-bit operation, 1-line display using internal
reset
18.3
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the eighth
character is completed (see Table 7). Note that both lines
of the display are always shifted together; data does not
shift from one line to the other.
Table 6 shows an example of a 1-line display in 8-bit
operation. The PCF2116 functions must be set by the
‘Function set’ instruction prior to display. Since the display
data RAM can store data for 80 characters, the RAM can
be used for advertising displays when combined with
display shift operation. Since the display shift operation
changes display position only and DDRAM contents
remain unchanged, display data entered first can be
displayed when the Return Home operation is performed.
18.2
8-bit operation, 2-line display
18.4
I2C operation, 1-line display
A control byte is required with most instructions
(see Table 8).
4-bit operation, 1-line display using internal
reset
18.5
The program must set functions prior to 4-bit operation.
Table 5 shows an example. When power is turned on, 8-bit
operation is automatically selected and the PCF2116
attempts to perform the first write as an 8-bit operation.
Since nothing is connected to DB0 to DB3, a rewrite is
then required. However, since one operation is completed
in two accesses of 4-bit operation, a rewrite is required to
set the functions (see Table 5 step 3).
Initializing by instruction
If the power supply conditions for correctly operating the
internal reset circuit are not met, the PCF2116 must be
initialized by instruction. Tables 9 and 10 show how this
may be performed for 8-bit and 4-bit operation.
Thus, DB4 to DB7 of the function set are written twice.
Table 5
4-bit operation, 1-line display example; using internal reset
STEP
INSTRUCTION
DISPLAY
1
power supply on (PCF2116 is initialized by
the internal reset circuit)
2
function set
3
4
5
6
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
0
OPERATION
Initialized. No display appears.
Sets to 4-bit operation. In this instance operation
is handled as 8-bits by initialization and only this
instruction completes with one write.
function set
0
0
0
0
1
0
0
0
0
0
0
0
Sets to 4-bit operation, selects 1-line display and
VLCD = V0. 4-bit operation starts from this point
and resetting is needed.
display on/off control
0
0
0
0
0
0
0
0
1
1
1
0
_
Turns on display and cursor. Entire display is
blank after initialization.
_
Sets mode to increment the address by 1 and to
shift the cursor to the right at the time of write to
the DD/CGRAM. Display is not shifted.
P_
Writes ‘P’. The DDRAM has already been
selected by initialization at power-on. The cursor
is incremented by 1 and shifted to the right.
entry mode set
0
0
0
0
0
0
0
0
0
1
1
0
write data to CGRAM/DDRAM
1
0
0
1
0
1
1
0
0
0
0
0
1997 Apr 07
42
STEP
INSTRUCTION
1
power supply on (PCF2116 is initialized by the internal reset
function)
2
function set
RS
0
3
0
0
1
1
0
0
0
0
Sets to 8-bit operation, selects 1-line display and
VLCD = V0.
0
0
0
0
0
1
1
1
0
_
Turns on display and cursor. Entire display is blank after
initialization.
0
0
0
0
1
1
0
_
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM. Display is not shifted.
1
0
0
0
0
P_
Writes ‘P’. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.
0
1
0
0
0
PH_
entry mode set
0
5
Initialized. No display appears.
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
write data to CGRAM/DDRAM
1
0
0
1
0
43
6
OPERATION
display mode on/off control
0
4
DISPLAY
Philips Semiconductors
8-bit operation, 1-line display example; using internal reset (character set ‘A’)
LCD controller/drivers
1997 Apr 07
Table 6
write data to CGRAM/DDRAM
1
0
0
1
0
Writes ‘H’.
|
7
|
|
8
write data to CGRAM/DDRAM
9
entry mode set
1
10
0
0
1
0
0
1
1
PHILIPS_
Writes ‘S’.
0
0
0
0
1
1
1
PHILIPS_
Sets mode for display shift at the time of write.
0
0
0
0
0
0
0
PHILIPS_
Writes space.
0
1
1
0
1
PHILIPS M_
Writes ‘M’.
0
1
write data to CGRAM/DDRAM
1
0
0
1
0
Product specification
1
write data to CGRAM/DDRAM
1
11
0
0
PCF2116 family
0
0
DISPLAY
OPERATION
|
12
|
|
13
write data to CGRAM/DDRAM
1
0
0
1
14
cursor or display shift
15
cursor or display shift
0
0
16
0
0
0
0
0
0
0
0
1
17
cursor or display shift
Z18
cursor or display shift
0
44
0
1
1
1
1
MICROKO
Writes ‘O’.
0
1
0
0
0
0
MICROKO
Shifts only the cursor position to the left.
0
1
0
0
0
0
MICROKO
Shifts only the cursor position to the left.
0
0
0
0
1
1
ICROCO
Writes ‘C’ correction. The display moves to the left.
0
1
1
1
0
0
MICROCO
Shifts the display and cursor to the right.
0
1
0
1
0
0
MICROCO_
Shifts only the cursor to the right.
0
1
1
0
1
ICROCOM_
Writes ‘M’.
write data to CGRAM/DDRAM
1
0
19
0
Philips Semiconductors
INSTRUCTION
LCD controller/drivers
1997 Apr 07
STEP
0
0
0
0
0
0
write data to CGRAM/DDRAM
1
0
0
1
0
|
20
|
|
21
Return Home
0
0
0
0
0
0
0
0
1
0
PHILIPS M
Returns both display and cursor to the original position
(address 0).
Product specification
PCF2116 family
STEP
INSTRUCTION
1
power supply on (PCF2116 is initialized by the internal reset
function)
Initialized. No display appears.
2
function set
Sets to 8-bit operation, selects 2-line display and voltage
generator off.
RS
0
3
DISPLAY
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
0
0
0
display on/off control
Turns on display and cursor. Entire display is blank after
initialization.
_
0
4
5
0
0
0
0
0
1
1
1
0
entry mode set
0
0
0
0
0
0
0
1
1
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM.
Display is not shifted.
P_
Writes ‘P’. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.
0
w
45
_
Write data to CGRAM/DDRAM
1
OPERATION
0
0
1
0
1
0
0
0
Philips Semiconductors
8-bit operation, 2-line display example; using internal reset
LCD controller/drivers
1997 Apr 07
Table 7
0
|
6
|
|
7
write data to CGRAM/DDRAM
Writes ‘S’.
PHILIPS_
1
8
0
0
1
0
1
0
0
1
1
set DDRAM address
PHILIPS
0
1
1
0
0
0
0
0
0
_
write data to CGRAM/ DDRAM
Writes ‘M’.
1
10
0
0
1
0
0
1
1
0
1
M_
|
|
|
Product specification
PHILIPS
PCF2116 family
0
9
Sets DDRAM address to position the cursor at the head of
the 2nd line.
DISPLAY
write data to CGRAM/ DDRAM
OPERATION
Writes ‘O’.
PHILIPS
1
12
0
0
1
0
0
1
1
1
1
MICROCO_
write data to CGRAM/ DDRAM
Sets mode for display shift at the time of write.
PHILIPS
0
13
0
0
0
0
0
0
1
1
1
MICROCO_
write data to CGRAM/ DDRAM
PHILIPS
1
0
0
1
0
0
1
1
0
1
Writes ‘M’. Display is shifted to the left. The first and
second lines shift together.
ICROCOM_
Philips Semiconductors
11
INSTRUCTION
LCD controller/drivers
1997 Apr 07
STEP
|
14
|
|
15
return Home
PHILIPS
46
0
0
0
0
0
0
0
0
1
0
Returns both display and cursor to the original position
(address 0).
MICROCOM
Product specification
PCF2116 family
I2C BYTE
STEP
1
I2C
2
slave address for write
DISPLAY
START
Initialized. No display appears.
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
3
4
1
1
1
0
1
0
0
During the acknowledge cycle SDA will be pulled-down by the
PCF2116.
1
send a control byte for function set
Co
RS
R/W
0
0
0
Ack
X
X
X
X
X
Control byte sets RS and R/W for following data bytes.
1
function set
Selects 1-line display and VLCD = V0; SCL pulse during
acknowledge cycle starts execution of instruction.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
5
0
1
X
0
0
0
0
1
display on/off control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
6
0
0
0
1
1
1
0
1
47
_
Turns on display and cursor. Entire display shows character
Hex 20 (blank in ASCII-like character sets).
_
Sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM.
Display is not shifted.
_
For writing data to DDRAM, RS must be set to 1. Therefore a
control byte is needed.
entry mode set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
7
8
OPERATION
Philips Semiconductors
Example of I2C operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1)
LCD controller/drivers
1997 Apr 07
Table 8
I2C
0
0
0
0
1
1
0
1
START
slave address for write
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
9
1
1
0
1
0
0
1
_
RS
R/W
0
1
0
Ack
X
X
X
X
X
1
_
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
1
0
0
0
0
1
P_
Writes ‘P’. The DDRAM has been selected at power-up.
The cursor is incremented by 1 and shifted to the right.
Product specification
Co
PCF2116 family
10
1
send a control byte for write data
OPERATION
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
0
1
Writes ‘H’.
PH_
|
12 to 15
|
|
|
16
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
17
18
48
19
1
0
1
0
0
1
1
Writes ‘S’.
1
PHILIPS_
(optional I2C stop) I2C start + slave address for write
(as step 8)
PHILIPS_
control byte
Co
RS
R/W
1
0
0
Ack
X
X
X
X
X
1
PHILIPS_
Return Home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
20
0
0
0
0
0
1
0
X
X
X
X
X
1
PHILIPS
Sets DDRAM address 0 in Address Counter. (also returns
shifted display to original position. DDRAM contents
unchanged). This instruction does not update the Data Register
control byte for read
Co
RS
R/W
0
1
1
Ack
21
I2C START
22
slave address for read
1
PHILIPS
1
1
1
0
1
0
1
1
During the acknowledge cycle the content of the DR is loaded
into the internal I2C interface to be shifted out. In the previous
instruction neither a ‘Set address’ nor a ‘Read data’ has been
performed. Therefore the content of the DR was unknown.
PHILIPS
8 × SCL; content loaded into interface during previous
acknowledge cycle is shifted out over SDA. MSB is DB7. During
master acknowledge content of DDRAM address 01 is loaded
into the I2C interface.
read data: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
X
X
X
X
X
X
X
X
0
Product specification
PHILIPS
PCF2116 family
0
DDRAM content will be read from following instructions.
The R/W has to be set to 1 while still in I2C-write mode.
PHILIPS
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
23
Philips Semiconductors
11
DISPLAY
LCD controller/drivers
1997 Apr 07
I2C BYTE
STEP
read data: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
25
1
0
0
1
0
0
0
0
PHILIPS
8 × SCL; code of letter ‘H’ is read first. During master
acknowledge code of ‘I’ is loaded into the I2C interface.
read data: 8 × SCL + no master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
26
OPERATION
1
I2C STOP
0
0
1
0
0
1
1
PHILIPS
No master acknowledge; After the content of the I2C interface
register is shifted out no internal action is performed. No new
data is loaded to the interface register, Data Register (DR) is not
updated, Address Counter (AC) is not incremented and cursor is
not shifted.
PHILIPS
Philips Semiconductors
24
DISPLAY
LCD controller/drivers
1997 Apr 07
I2C BYTE
STEP
Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
49
Product specification
PCF2116 family
STEP
DESCRIPTION
power-on or unknown state
|
wait 2 ms after VDD rises above VPOR
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
X
X
X
DB0 BF cannot be checked before this instruction.
X
Function set (interface is 8-bits long).
|
wait 2 ms
Philips Semiconductors
Initialization by instruction, 8-bit interface (note 1)
LCD controller/drivers
1997 Apr 07
Table 9
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
X
X
X
DB4
DB3
DB2
DB1
1
X
X
X
DB0 BF cannot be checked before this instruction.
X
Function set (interface is 8-bits long).
|
wait more than 40 µs
|
50
RS
R/W
DB7
DB6
DB5
0
0
0
0
1
DB0 BF cannot be checked before this instruction.
X
|
Function set (interface is 8-bits long).
BF can be checked after the following instructions. When BF is not checked,
the waiting time between instructions is the specified instruction time (see
Table 3).
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
N
M
G
0
0
0
0
0
0
1
0
0
0
Display off.
0
0
0
0
0
0
0
0
0
1
Clear display.
0
0
0
0
0
0
0
1
I/D
S
Entry mode set.
Initialization ends
1. X = don’t care.
Product specification
Note
PCF2116 family
|
DB0 Function set (interface is 8-bits long). Specify the number of display lines and
voltage generator characteristic.
0
DESCRIPTION
power-on or unknown state
|
wait 2 ms after VDD rises above VPOR
|
RS
R/W
0
0
DB7
DB6
DB5
DB4
0
0
1
1
DB6
DB5
DB4
0
1
1
DB7
DB6
DB5
DB4
0
0
1
1
BF cannot be checked before this instruction.
Function set (interface is 8-bits long).
|
wait 2 ms
Philips Semiconductors
STEP
LCD controller/drivers
1997 Apr 07
Table 10 Initialization by instruction, 4-bit interface. Not applicable for I2C-bus operation
|
RS
R/W
0
0
DB7
0
BF cannot be checked before this instruction.
Function set (interface is 8-bits long).
|
wait 40 µs
|
51
RS
0
R/W
0
|
RS
0
R/W
0
BF cannot be checked before this instruction.
Function set (interface is 8-bits long).
BF can be checked after the following instructions. When BF is not checked, the waiting time
between instructions is the specified instruction time. (See Table 3).
DB7
DB6
DB5
DB4
0
0
1
0
Function set (set interface to 4-bits long).
Interface is 8-bits long.
0
0
0
0
1
0
Function set (interface is 4-bits long).
0
0
N
M
G
0
Specify number of display lines and voltage generator characteristic.
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
I/D
S
Entry mode set.
Product specification
Initialization ends
Clear display.
PCF2116 family
|
Display off.
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
DISPLAY LAYOUT: COLUMNS
handbook, full pagewidth
C1
15 31
1
31
C16
30 46
45 45
31 15
61
91
60 60
46 30
1
120
16
PCF2116 column
output numbers
LCD column
numbers
PCF2116 column
output numbers
DISPLAY LAYOUT: ROWS
R8 to R1
R9 to R16
R17 to R24
R32 to R25
MGA814 - 1
2 x 24 character display
Fig.35 Example of 2 × 24 display layout (PCF2116x).
1997 Apr 07
52
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
DISPLAY LAYOUT: COLUMNS
handbook, full pagewidth
C1
15 46
1
31
PCF2116 column
output numbers
60
LCD column
numbers
60
DOT MATRIX LCD
C16
PCF2116 column
output numbers
45
DISPLAY LAYOUT: ROWS
R8 to R1
R9 to R16
R17 to R24
R32 to R25
MGA815 - 2
Fig.36 Example of 4 × 12 display layout (PCF2114x/PCF2116x).
1997 Apr 07
53
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
book, full pagewidth
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT
1 to 8
16 to 9
MLB897
1 line by 24 characters display
Fig.37 Display example (PCF2114x); 1-line by 24 characters.
1997 Apr 07
54
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
book, full pagewidth
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT
1 to 8
16 to 9
MLB898
2 lines by 12 characters display
Fig.38 Display example (PCF2114x); 2-lines by 12 characters.
1997 Apr 07
55
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
R1
R8
PCF2116
R9
R16
CHIP-ON-GLASS
R17
R24
4 LINE BY
12 CHARACTER
R25
R32
C1
2116
R9
C60
MGA818 - 1
SCL
VSS
SDA
VDD
V0 VLCD
Fig.39 Chip on glass application.
1997 Apr 07
56
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
y
C15
C14
C13
C12
C11
C9
C8
C7
C6
C5
C4
C3
C2
handbook, full pagewidth
C10
19 BONDING PAD LOCATIONS
C30
C1
C31
R24
C32
R23
C33
R22
C34
R21
C35
R20
C36
R19
C37
R18
C38
R17
C39
R8
C40
R7
C41
R6
C42
R5
C43
R4
C44
R3
C45
R2
R1
≈ 6.99
mm
0
x
0
DB7
C46
SCL
C47
DB6
C48
C49
SDA
C50
DB5
C51
V0
PCF2114
PCF2116
VLCD1
C52
C53
DB4
C54
VLCD2
C55
C56
DB3
C57
VLCD3
C58
C59
DB2
C60
≈ 5.64 mm
Chip dimensions: approximately 5.64 × 6.99 mm.
Pad area: 0.0121 mm2.
Bonding pad dimensions: 110 × 110 µm.
Fig.40 Bonding pad locations.
1997 Apr 07
57
R31
R30
R29
R28
R27
R26
R25
R16
R15
R14
R13
R12
R11
R9
R10
RS
V SS2
T1
R/W
V SS1
E
SA0
VDD1
DB0
VDD2
DB1
OSC
R32
MLB969
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
Table 11 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip,
see Fig.40.
PAD
x
y
C50
39
2626
−1060
C49
40
2626
−890
−3300
C48
41
2626
−720
−1806
−3300
C47
42
2626
−550
5
−1627
−3300
C46
43
2626
−380
SA0
6
−1437
−3300
C45
44
2626
582
E
7
−1245
−3300
C44
45
2626
752
SYMBOL
PAD
x
y
OSC
1
−2445
−3300
DB1
2
−2211
−3300
VDD2
3
−2034
DB0
4
VDD1
SYMBOL
VSS1
8
−1056
−3300
C43
46
2626
922
R/W
9
−867
−3300
C42
47
2626
1092
T1
10
−672
−3300
C41
48
2626
1262
VSS2
11
−486
−3300
C40
49
2626
1432
RS
12
−297
−3300
C39
50
2626
1602
R9
13
77
−3300
C38
51
2626
1772
R10
14
247
−3300
C37
52
2626
1942
R11
15
417
−3300
C36
53
2626
2112
R12
16
587
−3300
C35
54
2626
2282
R13
17
757
−3300
C34
55
2626
2452
R14
18
927
−3300
C33
56
2626
2622
R15
19
1097
−3300
C32
57
2626
2792
R16
20
1267
−3300
C31
58
2626
2962
59
2626
3132
R25
21
1436
−3300
C30
R26
22
1606
−3300
C29
60
2339
3302
R27
23
1776
−3300
C28
61
2169
3302
R28
24
1946
−3300
C27
62
1999
3302
R29
25
2116
−3300
C26
63
1829
3302
R30
26
2286
−3300
C25
64
1659
3302
R31
27
2456
−3300
C24
65
1489
3302
R32
28
2626
−3013
C23
66
1319
3302
C60
29
2626
−2760
C22
67
1149
3302
C59
30
2626
−2590
C21
68
979
3302
C58
31
2626
−2420
C20
69
809
3302
C57
32
2626
−2250
C19
70
639
3302
C56
33
2626
−2080
C18
71
469
3302
C55
34
2626
−1910
C17
72
299
3302
C54
35
2626
−1740
C16
73
129
3302
C53
36
2626
−1570
C15
74
−245
3302
C52
37
2626
−1400
C14
75
−415
3302
C51
38
2626
−1230
C13
76
−585
3302
1997 Apr 07
58
Philips Semiconductors
Product specification
LCD controller/drivers
SYMBOL
PCF2116 family
PAD
x
y
C12
77
−755
3302
C11
78
−925
3302
C10
79
−1095
3302
C9
80
−1265
3302
C8
81
−1435
3302
C7
82
−1605
3302
C6
83
−1775
3302
C5
84
−1945
3302
C4
85
−2115
3302
C3
86
−2285
3302
C2
87
−2455
3302
C1
88
−2625
3015
R24
89
−2625
2846
R23
90
−2625
2676
R22
91
−2625
2506
R21
92
−2625
2336
R20
93
−2625
2166
R19
94
−2625
1996
R18
95
−2625
1826
R17
96
−2625
1656
R8
97
−2625
1487
R7
98
−2625
1317
R6
99
−2625
1147
R5
100
−2625
977
R4
101
−2625
807
R3
102
−2625
637
R2
103
−2625
467
R1
104
−2625
297
DB7
105
−2625
−290
SCL
106
−2625
−479
DB6
107
−2625
−716
SDA
108
−2625
−976
DB5
109
−2625
−1202
V0
110
−2625
−1388
VLCD1
111
−2625
−1580
DB4
112
−2625
−1808
VLCD2
113
−2625
−1985
DB3
114
−2625
−2213
VLCD3
115
−2625
−2390
DB2
116
−2625
−2621
1997 Apr 07
59
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
20 PACKAGE OUTLINE
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
c
y
X
A
65
102
64
103
ZE
e
Q
E HE
A A2 A
1
(A 3)
θ
wM
Lp
bp
pin 1 index
L
detail X
39
128
1
38
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
14.1
13.9
0.5
HD
HE
22.15 16.15
21.85 15.85
L
Lp
Q
v
w
y
1.0
0.75
0.45
0.70
0.58
0.2
0.12
0.1
Z D(1) Z E(1)
θ
0.81
0.59
7
0o
0.81
0.59
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
96-04-02
SOT425-1
1997 Apr 07
EUROPEAN
PROJECTION
60
o
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
If wave soldering cannot be avoided, the following
conditions must be observed:
21 SOLDERING
21.1
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
21.2
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
21.4
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
21.3
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Apr 07
Repairing soldered joints
61
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
22 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
23 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 07
62
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
NOTES
1997 Apr 07
63
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/04/pp64
Date of release: 1997 Apr 07
Document order number:
9397 750 01754
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