Data Sheet

PCF8531
34 x 128 pixel matrix driver
Rev. 8 — 12 September 2014
Product data sheet
1. General description
The PCF8531 is a low-power CMOS1 LCD row and column driver, designed to drive dot
matrix graphic displays at multiplex rates of 1:17, 1:26, and 1:34. Furthermore, it can drive
up to 128 icons. All necessary functions for the display are provided in a single chip,
including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of
external components and low power consumption. The PCF8531 is compatible with most
microcontrollers and communicates via a two-line bidirectional I2C-bus. All inputs are
CMOS compatible.
Remark: The icon mode is used to reduce current consumption. When only icons are
displayed, a much lower operating voltage (VLCD) can be used and the switching
frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as
VLCD.
For a selection of NXP LCD graphic drivers, see Table 20 on page 48.
2. Features and benefits













1.
Single-chip LCD controller and driver
34 row and 128 column outputs
Display data RAM 34  128 bits
128 icons (last row is used for icons)
Fast-mode I2C-bus interface (400 kbit/s)
Software selectable multiplex rates: 1:17, 1:26, and 1:34
Icon mode with multiplex rate 1:2:
 Featuring reduced current consumption while displaying icons only
On-chip:
 Generation of VLCD (external supply also possible)
 Selectable linear temperature compensation
 Oscillator requires no external components (external clock also possible)
 Generation of intermediate LCD bias voltages
 Power-On Reset (POR)
No external components required
Software selectable bias configuration
Logic supply voltage range VDD1 to VSS1: 1.8 V to 5.5 V
Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2:
2.5 V to 4.5 V
Display supply voltage range VLCD to VSS:
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
 Normal mode: 4 V to 9 V
 Icon mode: 3 V to 9 V
 Low-power consumption, suitable for battery operated systems
 CMOS compatible inputs
 Manufactured in silicon gate CMOS process
3. Applications




Telecommunication systems
Automotive information systems
Point-of-sale terminals
Instrumentation
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCF8531U/2DA/1
Name
Description
Version
-
chip with bumps in tray
-
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF8531U/2DA/1
PCF8531U/2DA/1,026
chips in tray
1
PCF8531
Product data sheet
935286602026
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
5. Block diagram
5WR5
966
9''
9''
52:
'5,9(56
966
9''
&WR&
&2/801
'5,9(56
32:(5215(6(7
(15
,17(51$/
5(6(7
5(6
7
7
3&)
7
7
'$7$/$7&+(6
9/&',1
%,$6
92/7$*(
*(1(5$725
26&,//$725
26&
0$75,;
/$7&+(6
7,0,1*
*(1(5$725
9/&'6(16(
9/&'287
6&/
6'$
6'$&.
',63/$<'$7$5$0
9/&'
*(1(5$725
,1387
),/7(56
0$75,;'$7$
5$0
,&%86
&21752/
&200$1'
'(&2'(5
',63/$<
$''5(66
&2817(5
$''5(66
&2817(5
PJV
6$
Fig 1.
PCF8531
Product data sheet
Block diagram of PCF8531
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
6. Pinning information
6.1 Pinning
5
5
&
7
6&/
7
7
966
&
&
966
7
(15
6$
6'$&.
[
&
&
\
6'$
9''
9''
9''
5(6
&
&
9/&',1
9/&'287
9/&'6(16(
26&
3&)
&
5
5
SDG
PJV
Viewed from active side. The positioning of the bonding pads is not to scale.
Fig 2.
PCF8531
Product data sheet
Bonding pad location for PCF8531
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 3.
Pad allocation table
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Pad
Symbol
Pad
Symbol
15
OSC
55
ENR
16
VLCDSENSE
56
T4
17 to 23
VLCDOUT
57 to 63
VSS2
24 to 30
VLCDIN
64 to 70
VSS1
31
RES
71
T3
32 to 34
VDD3
72
T1
35 to 42
VDD2
73 to 74
SCL
43 to 49
VDD1
78
T2
50 to 51
SDA
87 to 103
R0, R2, R4, R6, R8,
R10, R12, R14, R16,
R18, R20, R22, R24,
R26, R28, R30, R32
52
SDACK
104 to 231
C0 to C127
54
SA0
232 to 248
R33, R31, R29, R27,
R25, R23, R21, R19,
R17, R15, R13, R11,
R9, R7, R5, R3, R1
\
FHQWHU
\
FHQWHU
\
FHQWHU
[FHQWHU
[FHQWHU
[FHQWHU
FLUFOH
&
)
$OOGLPHQVLRQVLQ—P
Fig 3.
DDD
Alignment markers
Table 4.
Alignment markers for PCF8531
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Alignment marks
x (m)
y (m)
C1
5402.0
823.1
C2
5292.4
823.4
F
5890.3
401.9
circle 1
5543.0
798.4
circle 2
5637.4
798.4
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
/
3&)
:
SLWFK
<
;
DDJ
Fig 4.
Chip dimensions
Table 5.
Bonding pad dimensions
Pad
Size
Unit
pad pitch (minimum)
70
m
bump dimensions
50  90  17.5 (3)
m
wafer thickness (excluding bumps)
381
m
die size L  W
12.14 
[1]
1.86[1]
mm
Die size including saw lane of 70 m.
6.2 Pin description
Table 6.
Bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
-
1
5973.6
821.7
dummy
-
2
5969.5
823.4
-
3
5899.5
823.4
-
4
5829.5
823.4
-
5
5479.5
823.4
-
6
5409.5
823.4
-
7
5059.5
823.4
-
8
4989.5
823.4
-
9
4639.5
823.4
-
10
4569.5
823.4
-
11
4219.5
823.4
-
12
4149.5
823.4
-
13
3799.5
823.4
-
14
3729.5
823.4
OSC
15
3449.5
823.4
oscillator input
[1]
VLCDSENSE
16
3169.5
823.4
voltage multiplier regulation input (VLCD)
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
VLCDOUT
17
3099.5
823.4
voltage multiplier output (VLCD)
[3]
VLCDOUT
18
3029.5
823.4
VLCDOUT
19
2959.5
823.4
VLCDOUT
20
2889.5
823.4
VLCDOUT
21
2819.5
823.4
VLCDOUT
22
2749.5
823.4
VLCDOUT
23
2679.5
823.4
VLCDIN
24
2539.5
823.4
LCD supply voltage (VLCD)
[2]
VLCDIN
25
2469.5
823.4
VLCDIN
26
2399.5
823.4
VLCDIN
27
2329.5
823.4
VLCDIN
28
2259.5
823.4
VLCDIN
29
2189.5
823.4
VLCDIN
30
2119.5
823.4
RES
31
1979.5
823.4
external reset input (active LOW)
[4]
VDD3
32
1699.5
823.4
supply voltage 3
[5]
VDD3
33
1629.5
823.4
VDD3
34
1559.5
823.4
VDD2
35
1279.5
823.4
supply voltage 2
[5]
VDD2
36
1209.5
823.4
VDD2
37
1139.5
823.4
VDD2
38
1069.5
823.4
VDD2
39
999.5
823.4
supply voltage 2
[5]
VDD2
40
929.5
823.4
VDD2
41
859.5
823.4
VDD2
42
789.5
823.4
VDD1
43
649.5
823.4
supply voltage 1
[5]
VDD1
44
579.5
823.4
VDD1
45
509.5
823.4
VDD1
46
439.5
823.4
VDD1
47
369.5
823.4
VDD1
48
299.5
823.4
VDD1
49
229.5
823.4
SDA
50
19.5
823.4
SDA
51
50.5
823.4
SDACK
52
400.5
823.4
serial data acknowledge output
-
53
750.5
823.4
dummy
SA0
54
820.5
823.4
I2C-bus slave address input; bit 0
ENR
55
1100.5
823.4
enable internal Power-On Reset (POR)
input
serial data line input of the I2C-bus
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
[6]
[7]
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
T4
56
1380.5
823.4
test input 4
[8]
VSS2
57
1660.5
823.4
ground 2
[9]
VSS2
58
1730.5
823.4
VSS2
59
1800.5
823.4
VSS2
60
1870.5
823.4
VSS2
61
1940.5
823.4
VSS2
62
2010.5
823.4
VSS2
63
2080.5
823.4
VSS1
64
2220.5
823.4
ground 1
[9]
VSS1
65
2290.5
823.4
VSS1
66
2360.5
823.4
VSS1
67
2430.5
823.4
VSS1
68
2500.5
823.4
VSS1
69
2570.5
823.4
VSS1
70
2640.5
823.4
T3
71
2780.5
823.4
test 3
[8]
T1
72
3060.5
823.4
test 1
[8]
SCL
73
3410.5
823.4
serial clock line input of the I2C-bus
SCL
74
3480.5
823.4
-
75
3830.5
823.4
-
76
4180.5
823.4
-
77
4530.5
823.4
T2
78
4600.5
823.4
test 2 output
-
79
4880.5
823.4
dummy
-
80
4950.5
823.4
-
81
5230.5
823.4
-
82
5300.5
823.4
-
83
5650.5
823.4
-
84
5720.5
823.4
-
85
5930.5
823.4
-
86
5926.4
821.7
R0
87
5786.4
821.7
R2
88
5716.4
821.7
R4
89
5646.4
821.7
R6
90
5576.4
821.7
R8
91
5506.4
821.7
R10
92
5436.4
821.7
R12
93
5366.4
821.7
R14
94
5296.4
821.7
dummy
LCD row driver output
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
[10]
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
R16
95
5226.4
821.7
LCD row driver output
R18
96
5156.4
821.7
R20
97
5086.4
821.7
R22
98
5016.4
821.7
R24
99
4946.4
821.7
R26
100
4876.4
821.7
R28
101
4806.4
821.7
R30
102
4736.4
821.7
R32
103
4666.4
821.7
C0
104
4526.4
821.7
C1
105
4456.4
821.7
C2
106
4386.4
821.7
C3
107
4316.4
821.7
C4
108
4246.4
821.7
C5
109
4176.4
821.7
C6
110
4106.4
821.7
C7
111
4036.4
821.7
C8
112
3966.4
821.7
C9
113
3896.4
821.7
C10
114
3826.4
821.7
C11
115
3756.4
821.7
C12
116
3686.4
821.7
C13
117
3616.4
821.7
C14
118
3546.4
821.7
C15
119
3476.4
821.7
C16
120
3406.4
821.7
C17
121
3336.4
821.7
C18
122
3266.4
821.7
C19
123
3196.4
821.7
C20
124
3126.4
821.7
C21
125
3056.4
821.7
C22
126
2986.4
821.7
C23
127
2916.4
821.7
C24
128
2846.4
821.7
C25
129
2776.4
821.7
C26
130
2706.4
821.7
C27
131
2636.4
821.7
C28
132
2566.4
821.7
C29
133
2496.4
821.7
LCD column driver output
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
C30
134
2426.4
821.7
LCD column driver output
C31
135
2356.4
821.7
C32
136
2216.4
821.7
C33
137
2146.4
821.7
C34
138
2076.4
821.7
C35
139
2006.4
821.7
C36
140
1936.4
821.7
C37
141
1866.4
821.7
C38
142
1796.4
821.7
C39
143
1726.4
821.7
C40
144
1656.4
821.7
C41
145
1586.4
821.7
C42
146
1516.4
821.7
C43
147
1446.4
821.7
C44
148
1376.4
821.7
C45
149
1306.4
821.7
C46
150
1236.4
821.7
C47
151
1166.4
821.7
C48
152
1096.4
821.7
C49
153
1026.4
821.7
C50
154
956.4
821.7
C51
155
886.4
821.7
C52
156
816.4
821.7
C53
157
746.4
821.7
C54
158
676.4
821.7
C55
159
606.4
821.7
C56
160
536.4
821.7
C57
161
466.4
821.7
C58
162
396.4
821.7
C59
163
326.4
821.7
C60
164
256.4
821.7
C61
165
186.4
821.7
C62
166
116.6
821.7
C63
167
46.4
821.7
C64
168
93.6
821.7
C65
169
163.6
821.7
C66
170
233.6
821.7
C67
171
303.6
821.7
C68
172
373.6
821.7
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
C69
173
443.6
821.7
LCD column driver output
C70
174
513.6
821.7
C71
175
583.6
821.7
C72
176
653.6
821.7
C73
177
723.6
821.7
C74
178
793.6
821.7
C75
179
863.6
821.7
C76
180
933.6
821.7
C77
181
1003.6
821.7
C78
182
1073.6
821.7
C79
183
1143.6
821.7
C80
184
1213.6
821.7
C81
185
1283.6
821.7
C82
186
1353.6
821.7
C83
187
1423.6
821.7
C84
188
1493.6
821.7
C85
189
1563.6
821.7
C86
190
1633.6
821.7
C87
191
1703.6
821.7
C88
192
1773.6
821.7
C89
193
1843.6
821.7
C90
194
1913.6
821.7
C91
195
1983.6
821.7
C92
196
2053.6
821.7
C93
197
2123.6
821.7
C94
198
2193.6
821.7
C95
199
2263.6
821.7
C96
200
2403.6
821.7
C97
201
2473.6
821.7
C98
202
2543.6
821.7
C99
203
2613.6
821.7
C100
204
2683.6
821.7
C101
205
2753.6
821.7
C102
206
2823.6
821.7
C103
207
2893.6
821.7
C104
208
2963.6
821.7
C105
209
3033.6
821.7
C106
210
3103.6
821.7
C107
211
3173.6
821.7
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 6.
Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 2).
PCF8531
Product data sheet
Symbol
Pad
X (m)
Y (m)
Description
C108
212
3243.6
821.7
LCD column driver output
C109
213
3313.6
821.7
C110
214
3383.6
821.7
C111
215
3453.6
821.7
C112
216
3523.6
821.7
C113
217
3593.6
821.7
C114
218
3663.6
821.7
C115
219
3733.6
821.7
C116
220
3803.6
821.7
C117
221
3873.6
821.7
C118
222
3943.6
821.7
C119
223
4013.6
821.7
C120
224
4083.6
821.7
C121
225
4153.6
821.7
C122
226
4223.6
821.7
C123
227
4293.6
821.7
C124
228
4363.6
821.7
C125
229
4433.6
821.7
C126
230
4503.6
821.7
C127
231
4573.6
821.7
R33
232
4713.6
821.7
LCD row driver output; icon row
R31
233
4783.6
821.7
LCD row driver output
R29
234
4853.6
821.7
R27
235
4923.6
821.7
R25
236
4993.6
821.7
R23
237
5063.6
821.7
R21
238
5133.6
821.7
R19
239
5203.6
821.7
R17
240
5343.6
821.7
R15
241
5413.6
821.7
R13
242
5483.6
821.7
R11
243
5553.6
821.7
R9
244
5623.6
821.7
R7
245
5693.6
821.7
R5
246
5763.6
821.7
R3
247
5833.6
821.7
R1
248
5903.6
821.7
[1]
If the on-chip oscillator is used, this input must be connected to VDD1.
[2]
If the internal VLCD generation is used, VLCDOUT, VLCDIN, and VLCDSENSE must be connected together.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
[3]
If an external VLCD is used in the application, then pin VLCDOUT must be left open-circuit, otherwise the chip
will be damaged.
[4]
If only the internal Power-On Reset (POR) is used, this input must be connected to VDD1.
[5]
VDD1 is for the logic supply, VDD2 and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and
VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2, and VDD3 must be
connected together.
[6]
Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes
fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from
the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be
able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK
output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where
the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to
the system SDA line to guarantee a valid LOW level.
[7]
If ENR is connected to VSS, Power-On Reset (POR) is disabled; to enable Power-On Reset (POR) ENR
must be connected to VDD1.
[8]
In the application, this input must be connected to VSS.
[9]
VSS1 and VSS2 must be connected together.
[10] In the application, T2 must be left open-circuit.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
7. Functional description
7.1 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC input must be connected to VDD. An external clock
signal, if used, is connected to this input.
7.2 Power-On Reset (POR)
The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure.
7.3 I2C-bus controller
The I2C-bus controller receives and executes the commands. The PCF8531 acts as an
I2C-bus slave receiver and therefore it cannot control bus communication.
7.4 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.5 Display data RAM
The PCF8531 contains 34  128 bits static RAM for storing the display data, see Figure 7.
The RAM is divided into 6 banks of 128 bytes (6  8  128 bits). Bank 5 is used for icon
data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There
is a direct correspondence between the X address and column output number.
7.6 Timing generator
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not affected by operations on the data buses.
7.7 Address counter
The address counter sets the addresses of the display data RAM for writing.
7.8 Display address counter
The display address counter generates the addresses for read out of the display data.
7.9 Command decoder
The command decoder identifies command words that arrive on the I2C-bus and
determines the destination for the following data bytes.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
7.10 Bias voltage generator
The bias voltage generator generates four buffered intermediate bias voltages. This block
contains the generator for the reference voltages and the four buffers. This block can
operate in two voltage ranges:
• Normal mode: 4.0 V to 9.0 V
• Power save mode: 3.0 V to 9.0 V.
7.11 VLCD generator
The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is
programmed by software.
7.12 Reset
The PCF8531 has the possibility of two reset modes: internal Power-On Reset (POR) or
external reset (RES). The reset mode is selected using the ENR signal. After a reset, the
chip has the following state:
• All row and column outputs are set to VSS (display off)
• RAM data is undefined
• Power-down mode
7.13 Power-down
During power-down, all static currents are switched off (no internal oscillator, no timing
and no LCD segment drive system) and all LCD outputs are internally connected to VSS.
The I2C-bus function remains operational.
7.14 Column driver outputs
The LCD drive section includes 128 column outputs (C0 to C127) which must be
connected directly to the LCD. The column output signals are generated in accordance
with the multiplexed row signals and with the data in the display latch. When less than
128 columns are required, the unused column outputs must be left open-circuit.
7.15 Row driver outputs
The LCD drive section includes 34 row outputs (R0 to R33), which must be connected
directly to the LCD. The row output signals are generated in accordance with the selected
LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused
outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is
R0, R2, ..., R1, R3, etc.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
8. LCD waveforms and DDRAM to data mapping
The LCD waveforms and the DDRAM to display data mapping are shown in Figure 5,
Figure 6 and Figure 7.
IUDPHQ
52:
5W
52:
5W
&2/
&W
&2/
&W
IUDPHQ
9/&'
9
9
9VWDWHW
9VWDWHW
9
9
966
9/&'
9
9
9
9
966
9/&'
9
9
9
9
966
9/&'
9
9
9
9
966
9/&'
9 966
9VWDWHW
9/&' 9
9
9 9
9 9
9
966 9
9 9/&'
9/&'
9/&'
9 966
9VWDWHW
9/&' 9
9
9 9
9 9
9
966 9
9 9/&'
9/&'
PJV
(1) Vstate1(t) = C1(t)  R0(t).
(2) Vstate2(t) = C1(t)  R1(t).
Fig 5.
Typical LCD driver waveforms
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
IUDPHQ
IUDPHQ
RQO\LFRQVDUHGULYHQ
9/&'
9
9
52:WR
9
9
966
9/&'
9
9
52:
9
9
966
9/&'
9
9
&2/RQRII
9
9
966
9/&'
9
9
&2/RIIRQ
9
9
966
9/&'
9
9
&2/RQRQ
9
9
966
9/&'
9
9
&2/RIIRII
9
9
966
PJV
Fig 6.
LCD waveforms, icon mode, multiplex rate 1:2
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
''5$0
EDQN
WRSRI/&'
5
EDQN
5
EDQN
5
/&'
EDQN
5
EDQN
5
5LFRQURZ
EDQN
PJV
Fig 7.
DDRAM to display data mapping
8.1 Addressing
Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8,
Figure 9 and Figure 10. The display RAM has a matrix of 34  128 bits. The columns are
addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to
Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode
(V = 1), the Y address increments after each byte (see Figure 9). After the last Y address
(Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal
addressing mode (V = 0), the X address increments after each byte (see Figure 10). After
the last X address (X = 127), X wraps around to 0 and Y increments to address the next
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to
address (X = 0 and Y = 0). The Y address 5 is reserved for icon data and is not affected
by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is
written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM.
/6%
06%
/6%
<DGGUHVV
06%
/6%
LFRQGDWD
;DGGUHVV
PJV
06%
Fig 8.
RAM format and addressing
LFRQGDWD
Fig 9.
;DGGUHVV
<DGGUHVV
PJV
Sequence of writing data bytes into RAM with vertical addressing (V = 1)
LFRQGDWD
;DGGUHVV
<DGGUHVV
PJV
Fig 10. Sequence of writing data bytes into RAM with horizontal addressing (V = 0)
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
9. Instructions
Only two PCF8531 registers, the instruction register and the data register can be directly
controlled by the MPU. Before internal operation, control information is stored temporarily
in these registers to allow interfacing to various types of MPUs which operate at different
speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is
controlled by the instructions given in Table 12.
Instructions are of four types:
•
•
•
•
Those that define PCF8531 functions e.g. display configuration, etc.
Those that set internal RAM addresses
Those that perform data transfer to/from the internal RAM
Others
In normal mode instructions which perform data transfer to/from the internal RAM are
used most frequently. Automatic incrementing by 1 of internal RAM addresses after each
data write reduces the MPU program load.
9.1 Reset
After reset or internal Power-On Reset (POR) (depending on the application), the LCD
driver is set to the following state:
•
•
•
•
•
•
•
•
Power-down mode (PD = 1)
Horizontal addressing (V = 0)
Display blank (D = 0; E = 0), no icon mode (IM = 0)
Address counter X[6:0] = 0; Y[2:0] = 0
Bias system BS[2:0] = 0
Multiplex rate M[1:0] = 0 (multiplex rate 1:17)
Temperature control mode TC[2:0] = 0
HV-gen control, HVE = 0 the high voltage (HV) generator is switched off, PRS = 0 and
S[1:0] = 0
• VLCD = 0 V
• RAM data is undefined
• Command page definition H[1:0] = 0
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
20 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
9.2 Function set
9.2.1 PD
When PD = 1, the power-down mode of the LCD driver is active:
•
•
•
•
•
•
All LCD outputs at VSS (display off)
Power-On Reset (POR) detection active, oscillator off
VLCD can be disconnected
I2C-bus is operational, commands can be executed
RAM contents not cleared; RAM data can be written
Register settings remain unchanged
9.2.2 V
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as
shown in Figure 10. When V = 1 the vertical addressing is selected. The data is written
into the DDRAM as shown in Figure 9. Icon data is written independently of V when
Y address is 5.
9.3 Set Y address
Bits Y2, Y1, and Y0 define the Y address vector of the display RAM (see Table 7).
Table 7.
Y address
Y2
Y1
Y0
Bank
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5 (icons)
9.4 Set X address
The X address points to the columns. The range of X is 0 to 127 (7Fh).
9.5 Set multiplex rate
M[1:0] selects the multiplex rate (see Table 8).
Table 8.
Multiplex rates
Multiplex rate
M1
M0
1:17
0
0
1:26
1
0
1:34
0
1
9.6 Display control (D, E, and IM)
Bits D and E select the display mode (see Table 14). Bit IM (see Table 13) sets the display
to icon mode.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
21 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
9.7 Set bias system
The bias voltage levels are set in the ratio of R  R  n  R  R  R (see Figure 11).
9 9/&'
5
9
5
9
Qî5
9
5
9
5
9 966
DDD
Fig 11. Voltage divider chain
Different multiplex rates require different bias settings. Bias settings are programmed by
BS[2:0], which sets the binary number n. The optimum value for n is given by:
n =
muxrate – 3
Supported values of n are given in Table 9. Table 10 shows the intermediate bias
voltages.
Table 9.
BS[2:0]
n
Bias system
Comment
000
7
1⁄
11
-
6
1⁄
10
-
5
1⁄
9
-
011
4
1⁄
8
-
100
3
1⁄
7
recommended for 1:34
2
1⁄
6
recommended for 1:26
1
1⁄
5
recommended for 1:17
0
1⁄
4
recommended for icon mode
001
010
101
110
111
PCF8531
Product data sheet
Programming the required bias system
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
22 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
9.8 LCD bias voltage
Table 10.
Intermediate LCD bias voltages
Symbol
Bias voltage
Example for 1⁄7 bias
V1
VLCD
VLCD
V2
n+3
------------  V LCD
n+4
6⁄
7
 VLCD
V3
n+2
------------  V LCD
n+4
5⁄
7
 VLCD
V4
2
------------  V LCD
n+4
2⁄
7
 VLCD
V5
1
------------  V LCD
n+4
1⁄
7
 VLCD
V6
VSS
VSS
9.9 Set VLCD value
VLCD can be set by software. The voltage at intersection temperature [VLCD (T = Tints)] can
be calculated as: VLCD (Tints) = a + VLCD  b
The generated voltage is dependent on the temperature, programmed Temperature
Coefficient (TC) and the programmed voltage at intersection temperature (Tints).
VLCD = VLCD (Tints) [1 + TC (T  Tints)]
The parameter values are given in Table 11. Two overlapping VLCD ranges can be
selected via the command HV-gen control (see Table 11 and Figure 12). The maximum
voltage which can be generated depends on the VDD2 and VDD3 voltages and the display
load current. For multiplex rate 1:34, the optimum VLCD can be calculated as:
1 + 34
V LCD = --------------------------------------  V th = 5.30  V th
1
2   1 – ----------

34
Where Vth is the threshold voltage of the liquid crystal material used.
The practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast.
As the programming range for the internally generated VLCD allows values above the
maximum allowed VLCD, the user must ensure, while setting the VOP register and
selecting the temperature compensation, that the VLCD limit maximum of 9.0 V is never
exceeded under all conditions and including all tolerances.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
23 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 11.
Parameter values for the HV generator programming
Symbol
Value
Unit
PRS = 0
PRS = 1
Tints
27
27
C
a
2.94
6.75
V
b
0.03
0.03
V
programming range
2.94 to 6.75
6.75 to 10.56
V
9/&'
E
D
' (
)
/2:
)
)
)
+,*+
PJO
VOP[6:0] (programmed) [00h to 7Fh] program range LOW to HIGH.
Fig 12. VLCD programming of PCF8531
9.10 Voltage multiplier control S[1:0]
The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal
or external), the voltage multiplier is set to 2  VDD2. The voltage multiplier factors are set
by setting bits S[1:0] (see Table 14).
9.11 Temperature compensation
Due to the temperature dependency of the viscosity of the liquid crystals, the LCD
controlling voltage VLCD should usually be increased at lower temperatures to maintain
optimum contrast. Figure 13 shows VLCD for high multiplex rates.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
24 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
PJV
9/&'
ƒ&
7
Fig 13. VLCD as a function of liquid crystal temperature
Linear temperature compensation is supported in the PCF8531. The temperature
coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see
Table 14).
Table 12.
Instruction set
Instruction
I2C-bus
command[1]
I2C-bus command byte
RS
DB7
R/W
DB6
DB5
Description
DB4
DB3
DB2
DB1
DB0
H1 and H0 = don’t care (H independent command page)
NOP
0
0
0
0
0
0
0
0
0
0
no operation
write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
write data to
display RAM
set default H[1:0]
0
0
0
0
0
0
0
0
0
1
select H[1:0] = 0
H1 = 0 and H0 = 0 (function and RAM command page)
instruction set
0
0
0
0
0
0
1
0
H1
H0
select command
page
function set
0
0
0
0
1
0
0
PD
V
0
power-down
control; entry
mode
set Y address of
RAM
0
0
0
1
0
0
0
Y2
Y1
Y0
set Y address of
RAM; 0  Y  5
set X address of
RAM
0
0
1
X6
X5
X4
X3
X2
X1
X0
set X address of
RAM; 0  X  127
H1 = 0 and H0 = 1 (display setting command page)
multiplex rate
0
0
0
0
0
0
0
1
M1
M0
set multiplex rate
display control
0
0
0
0
0
0
1
D
IM
E
set display
configuration
bias system
0
0
0
0
0
1
0
BS2
BS1
BS0
set bias system
(BSx)
H1 = 1 and H0 = 0 (HV-gen command page)
HV-gen control
0
0
0
0
0
0
0
1
PRS
HVE
set VLCD
programming
range
HV-gen
configuration
0
0
0
0
0
0
1
0
S1
S0
set voltage
multiplication
factor
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
25 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 12.
Instruction set …continued
I2C-bus
command[1]
I2C-bus command byte
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
temperature control
0
0
0
0
1
0
0
TC2
TC1
TC0
set temperature
coefficient
test modes
0
0
0
1
X
X
X
X
X
X
do not use
(reserved for test)
VLCD control
0
0
1
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register
Instruction
[1]
Description
R/W is set to the slave address byte; Co and RS are set in the control byte.
Table 13.
Explanation for symbols in Table 12
Bit
0
1
PD
chip is active
chip is in power-down mode
V
horizontal addressing
vertical addressing
normal mode; full display + icons
icon mode; only icons are displayed
IM
H[1:0]
[1]
see Table 14
D and E
see Table 14
HVE
voltage multiplier disabled
voltage multiplier enabled
PRS
VLCD programming range LOW
VLCD programming range HIGH
TC[2:0]
see Table 14
S[1:0]
see Table 14
[1]
The bits H[1:0] identify the command page (use set default H[1:0] command to set H[1:0] = 0).
Table 14.
Description of bits H, D and E, TC and S
Bits
Value
Description
00
function and RAM command page
01
display setting command page
10
HV-gen command page
00
display blank
10
normal mode
01
all display segments
11
inverse video mode
Command page (H)
H[1:0]
Display modes (D, E)
D and E
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
26 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 14.
Description of bits H, D and E, TC and S …continued
Bits
Value
Description
000
temperature coefficient TC0
001
temperature coefficient TC1
Temperature coefficient (TC)
TC[2:0]
010
temperature coefficient TC2
011
temperature coefficient TC3
100
temperature coefficient TC4
101
temperature coefficient TC5
110
temperature coefficient TC6
111
temperature coefficient TC7
00
2  voltage multiplier
01
3  voltage multiplier
10
4  voltage multiplier
11
5  voltage multiplier
Voltage multiplier factor (S)
S[1:0]
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
10. I2C-bus interface
10.1 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
10.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 14).
6'$
6&/
GDWDOLQH
VWDEOH
GDWDYDOLG
FKDQJH
RIGDWD
DOORZHG
PEF
Fig 14. Bit transfer
10.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 15.
6'$
6'$
6&/
6&/
6
3
67$57FRQGLWLRQ
6723FRQGLWLRQ
PEF
Fig 15. Definition of START and STOP conditions
10.1.3 System configuration
The system configuration is shown in Figure 16.
• Transmitter: the device that sends the data to the bus
• Receiver: the device that receives the data from the bus
• Master: the device that initiates a transfer, generates clock signals and terminates a
transfer
• Slave: the device addressed by a master
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
• Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message
• Arbitration: procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock signals of two or more devices.
0$67(5
75$160,77(5
5(&(,9(5
6/$9(
5(&(,9(5
6/$9(
75$160,77(5
5(&(,9(5
0$67(5
75$160,77(5
0$67(5
75$160,77(5
5(&(,9(5
6'$
6&/
PJD
Fig 16. System configuration
10.1.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 17.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
GDWDRXWSXW
E\WUDQVPLWWHU
QRWDFNQRZOHGJH
GDWDRXWSXW
E\UHFHLYHU
DFNQRZOHGJH
6&/IURP
PDVWHU
6
67$57
FRQGLWLRQ
FORFNSXOVHIRU
DFNQRZOHGJHPHQW
PEF
Fig 17. Acknowledge on the I2C-bus
10.2 I2C-bus protocol
This driver does not support read. The PCF8531 is a slave receiver. Therefore, it only
responds when R/W = 0 in the slave address byte.
Before any data is transmitted on the I2C-bus, the device that must respond is addressed
first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531.
The least significant bit of the slave address is set by connecting the input SA0 to either
logic 0 (VSS) or logic 1 (VDD).
The I2C-bus protocol is shown in Figure 18.
The sequence is initiated with a START condition (S) from the I2C-bus master, and is
followed by the slave address. All slaves with the corresponding address acknowledge in
parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more
command words follow, which define the status of the addressed slaves. A command
word consists of a control byte, which defines Co and RS, plus a data byte (see Figure 19
and Table 12).
The last control byte is tagged with a cleared most significant bit, the continuation bit Co.
The control and data bytes are also acknowledged by all addressed slaves on the bus.
After the last control byte, depending on the RS bit setting, either a series of display data
bytes or command data bytes may follow. If the RS bit was set logic 1, these display bytes
are stored in the display RAM at the address specified by the data pointer.
The data pointer is automatically updated and the data is directed to the intended
PCF8531 device. If the RS bit of the last control byte was set logic 0, these command
bytes will be decoded and the setting of the device will be changed according to the
received commands. The acknowledgement after each byte is made only by the
addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP
condition (P).
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
VODYHDGGUHVV
6
FRQWUROE\WH
6$ 5:
$
&R
56
;
;
;
;
;
;
PJV
Fig 18. Slave address and control byte
DFNQRZOHGJH
IURP3&)
6
6 $ $ 56
VODYHDGGUHVV
5: &R
DFNQRZOHGJH
IURP3&)
FRQWUROE\WH
$
DFNQRZOHGJH
IURP3&)
GDWDE\WH
Q•E\WHV
$ 56
&R
DFNQRZOHGJH
IURP3&)
FRQWUROE\WH
E\WH
$
DFNQRZOHGJH
IURP3&)
GDWDE\WH
$ 3
Q•E\WHV
06%/6%
PJV
Fig 19. Master transmits to slave receiver; write mode
10.3 Command decoder
The command decoder identifies command words that arrive on the I2C-bus. The most
significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates
that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it
indicates that a series of data bytes (either command or RAM data) may follow. The DB6
bit of a control byte is the RAM data/command bit RS. When this bit is logic 1, it indicates
that another RAM data byte will be transferred next. If the bit is logic 0, it indicates that
another command byte will be transferred next.
• Pairs of bytes; information in the second byte, the first byte determines whether
information is display or instruction data
• Stream of information bytes after Co = 0; display or instruction data, depending on last
RS.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
31 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
11. Internal circuitry
3$'6WR
3$'6WR
3$'6WR
9''
9''
9''
966
966
3$'6WR
966
966
3$'6WR
3$'6WR
3$'6WR
3$'6WR
9/&',16833/<
966
9/&'287
9/&'6(16(
966
966
966
9/&',1
9''
3$'6
3$'6WR
6&/6'$6'$&.
966
966
9''
9''
3$'6
3$'
7
26&6$7775(6(15
966
966
PJV
For all diagrams the maximum forward current is 5 mA and the maximum reverse voltage is 5 V.
Fig 20. Device protection diagrams
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
32 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
12. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
33 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
13. Limiting values
Table 15. Limiting values [1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD1
supply voltage 1
logic supply
0.5
+6.5
V
VDD2
supply voltage 2
multiplier supply
0.5
+6.5
V
VDD3
supply voltage 3
multiplier supply
0.5
+6.5
V
VLCD
LCD supply voltage
0.5
+10.0
V
VI
input voltage
0.5
VDD + 0.5
V
VO
output voltage
0.5
VDD + 0.5
V
IDD
supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
II
input current
10
+10
mA
IO
output current
10
+10
mA
Ptot
total power dissipation
-
300
mW
P/out
power dissipation per
output
-
30
mW
VESD
electrostatic discharge
voltage
Ilu
latch-up current
Tj
junction temperature
Tstg
storage temperature
Tamb
ambient temperature
HBM
[2]
-
1500
V
MM
[3]
-
200
V
[4]
-
200
mA
-
+150
C
65
+150
C
40
+85
C
[5]
operating device
[1]
Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages are referenced to VSS unless
otherwise specified.
[2]
Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”.
[3]
Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”.
[4]
Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[5]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
34 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
14. Static characteristics
Table 16. Static characteristics
VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3  VLCD  9.0 V;
Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
4.0
-
9.0
V
[1]
3.0
-
9.0
V
1.9
-
5.5
V
Supplies
VLCD
LCD supply voltage
icon mode
VDD1
supply voltage 1
logic supply
Tamb  25 C
1.8
-
5.5
V
VDD2
supply voltage 2
multiplier supply; LCD
voltage internally generated
2.5
-
5.5
V
VDD3
supply voltage 3
multiplier supply; LCD
voltage internally generated
2.5
-
5.5
V
IDD
supply current
power-down mode; internal
VLCD
-
2
10
A
[2][3]
-
170
350
A
normal mode; external VLCD
[2]
-
10
50
A
normal mode; external VLCD
[2][4]
-
25
100
A
icon mode; external VLCD
[2][5]
-
15
70
A
0.9
1.2
1.6
V
normal mode; internal VLCD
IDD(LCD)
VPOR
LCD supply current
[6]
power-on reset voltage
Logic
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
VDD
V
IOL(SDA)
LOW-level output current
on pin SDA
VOL = 0.4 V; VDD = 5.0 V
3.0
-
-
mA
ILI
input leakage current
VI = VDD or VSS
1
-
+1
A
-
12
20
k
Column and row outputs
[7]
RO
output resistance
column outputs: C0 to C127
row outputs: R0 to R33
-
12
20
k
Vbias
bias voltage variation
outputs R0 to R33 and
C0 to C127
100
0
+100
mV
VLCD
LCD voltage variation
TC1 to TC7
-
-
3.9
%
TC
temperature coefficient
Tamb = 20 C to +70 C
TC0; TC[2:0] = 000
-
0
-
%/K
TC1; TC[2:0] = 001
-
0.026
-
%/K
TC2; TC[2:0] = 010
-
0.039
-
%/K
TC3; TC[2:0] = 011
-
0.052
-
%/K
TC4; TC[2:0] = 100
-
0.078
-
%/K
TC5; TC[2:0] = 101
-
0.13
-
%/K
TC6; TC[2:0] = 110
-
0.19
-
%/K
[8]
TC7; TC[2:0] = 111
Tints
intersection temperature
PCF8531
Product data sheet
-
0.26
-
%/K
-
27
-
C
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
35 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
[1]
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure,
while setting the VOP register and selecting the temperature compensation, that the VLCD maximum limit of 9 V will never be exceeded
under all conditions and including all tolerances.
[2]
LCD outputs are open circuit, inputs at VDD or VSS; bus inactive.
[3]
VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3  VDD; fosc = 34 kHz.
[4]
VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fosc = 34 kHz.
[5]
VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fosc = 34 kHz.
[6]
Resets all logic when VDD1 VPOR.
[7]
Iload  50 A; outputs are tested one at a time.
[8]
VLCD  7.7 V.
15. Dynamic characteristics
Table 17. Dynamic characteristics
VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3  VLCD  9.0 V;
Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
ffr(LCD)
LCD frame frequency
VDD = 3.0 V
fosc
oscillator frequency
fclk(ext)
external clock frequency
tw(RESL)
RES LOW pulse width
tsu(RESL)
RES LOW set-up time
Serial bus interface (see Figure
[1]
[2]
Min
Typ
Max
Unit
40
66
135
Hz
20
34
65
kHz
20
-
65
kHz
300
-
-
ns
-
-
30
s
22)[3]
fSCL
SCL clock frequency
0
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
0.9
s
20 + 0.1Cb -
300
ns
20 + 0.1Cb -
300
ns
tr
rise time of both SDA and
SCL signals
[4]
tf
fall time of both SDA and
SCL signals
[4]
Cb
capacitive load for each
bus line
-
-
400
pF
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tSP
pulse width of spikes that
on bus
must be suppressed by the
input filter
-
-
50
ns
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
36 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
[1]
ffr = fclk(ext)/480 or fosc/480.
[2]
A reset is generated if tw(RESL)  3 ns (see Figure 21).
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an
input voltage swing of VSS to VDD.
[4]
Cb = total capacitance of one bus line in pF.
9''
5(6
9,/
WVX5(6/
WZ5(6/
PJV
Fig 21. Reset timing
6'$
W%8)
W/2:
WI
6&/
W+'67$
WU
W+''$7
W+,*+
W68'$7
6'$
W6867$
W68672
PJD
Fig 22. I2C-bus timing
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
37 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
PJV
PJV
,''
—$
,''
—$
î
î
î
î
9/&' 9
9
9
9''DQG9''9
PJV
9/&'
9/&'9
VDD1 = 2 V; 4  voltage multiplier; Tamb = 27 C; TC = 0;
BS = 100; no VLCD load.
Fig 23. Supply current as a function of supply
voltage 2 and supply voltage 3
VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 C;
fosc = 34 kHz; no VLCD load.
Fig 24. Supply current as a function of LCD supply
voltage; different multiplication factors
PJV
,
—$
9
,''/&'
7&
7&
,''
7&
7&
7ƒ&
Fig 25. LCD supply voltage as a function of
temperature
Product data sheet
9/&'9
VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 C;
no VLCD load.
PCF8531
VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD;
Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
Fig 26. Supply current as a function of LCD supply
voltage
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
38 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
PJV
PJV
, ''
—$
,
—$
, ''/&'
, ''
IN+]
VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD;
Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
Fig 27. Supply current as a function of frequency
PCF8531
Product data sheet
9/&'9
VDD1 = 1.8 V; VDD2 = 2.5 V; 2  voltage multiplier;
Tamb = 27 C; TC = 0; BS = 111; no VLCD load.
Fig 28. Supply current as a function of LCD supply
voltage
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
39 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
16. Application information
16.1 Typical system configuration
9/&'
9''WR9''
9'',&
FROXPQGULYHUV
URZGULYHUV
5(6
/&'3$1(/
(15
6$
6&/
6'$
5SX
3&)
6'$&.
5SX
+267
0,&52352&(6625
0,&52&21752//(5
966
966
966
5(6
6&/
6'$
966966
PJV
Fig 29. Typical system configuration
The host microprocessor/microcontroller and the PCF8531 are both connected to the
I2C-bus. The SDA and SCL lines must be connected to the positive power supply via
pull-up resistors. The internal oscillator requires no external components. The appropriate
intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and suitable capacitors for decoupling VLCD and VDD.
16.2 Power supply connections for internal VLCD generation
99WR9
9''
9''
—)
9WR9
—)
*1'
9''
9''
966
966
9WR9
9''
9''
—)
*1'
966
966
DDD
DDD
Fig 30. Recommended VDD connections for internal VLCD generation
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
40 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
9/&',1
—)
9/&'287
966
9/&'6(16(
DDD
Fig 31. Recommended VLCD connections for internal VLCD generation
16.3 Power supply connections for external VLCD generation
99WR9
9/&',1
9''
9WR9
9/&',1
—)
9WR9
9''
9''
*1'
QF
9/&'287
RU
QF
9/&'287
—)
966
966
9/&'6(16(
9/&'6(16(
DDD
Remark: When using an external VLCD, the internal VLCD generator must never be switched on
otherwise damages will occur.
Fig 32. Recommended VDD connections for external VLCD generation
16.4 Information about VLCD connections
VLCDIN — This input is used for generating the 5 LCD bias levels. It is the power supply for
the bias level buffers.
VLCDOUT — This is the VLCD output if VLCD is generated internally. It is the output of the
charge pump. In this case pin VLCDOUT must be connected to VLCDIN and to VLCDSENSE
(see Figure 31). VLCDOUT must be left open circuit when VLCD is supplied from an external
source (see Figure 32).
VLCDSENSE — When using the internal VLCD generation, this pin must be connected to
VLCDOUT and VLCDIN (see Figure 31). When using an external VLCD supply it must be
connected to VLCDIN or to ground (see Figure 32).
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
41 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
16.5 Chip-on-glass application
',63/$<î3,;(/6
3&)
5 ,2
5VXSSO\
&H[W
,2
9''
WR
9''
966
966 9/&'
PJV
Fig 33. Chip-on-glass application
The required minimum values for the external capacitors in a chip-on-glass application
are:
• Cext = 100 nF between VLCD and VSS1, VSS2; Cext = 470 nF between VDD1, VDD2, VDD3
and VSS1, VSS2.
• Higher capacitor values are recommended for ripple reduction.
• For COG applications, the recommended ITO track resistance must be minimized for
the I/O and supply connections. Optimized values for these tracks are below 50  for
the supply (Rsupply) and below 100  for the I/O connections (RI/O).
• To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application,
NXP strongly recommended implementing a series input resistance in the reset line
(recommended minimum value 8 k) on the glass (ITO). If the reset input is not used,
this input must be connected to VDD1 using a short connection.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
42 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
16.6 Programming example
Table 18.
Step
Programming example for PCF8531
Serial bus byte
Display
Operation
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
1
1
1
0
SA0
0
start; slave address; R/W = 0
2
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
3
0
0
0
0
0
0
0
1
H[1:0] independent
command; select function
and RAM command page
(H[1:0] = 00)
4
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
5
0
0
1
0
0
0
1
0
function and RAM command
page PD = 0 and V = 1
6
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
7
0
0
0
0
1
0
0
1
function and RAM command
page select display setting
command page H[1:0] = 01
8
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
9
0
0
0
0
1
1
0
0
display setting command
page; set normal mode
(D = 1; IM = 0 and E = 0)
10
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
11
0
0
0
0
0
1
0
1
select multiplex rate 1:34
12
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
13
0
0
0
0
0
0
0
1
H[2:0] independent
command; select function
and RAM command page
H[1:0] = 00
14
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
15
0
0
0
0
1
0
1
0
function and RAM command
page; select HV-gen
command page H[1:0] = 10
16
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
17
0
0
0
0
1
0
1
1
HV-gen command page;
select voltage multiplication
factor 5 S[1:0] = 11
18
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
19
0
0
1
0
0
0
1
0
HV-gen command page;
select temperature
coefficient 2 TC[2:0] = 010
20
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
21
0
0
0
0
0
1
1
1
HV-gen command page;
select high VLCD
programming range
(PRS = 1); voltage multiplier
off (HVE = 1)
22
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
43 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 18.
Step
Programming example for PCF8531 …continued
Serial bus byte
Display
Operation
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
23
1
0
1
0
0
0
0
0
HV-gen command page; set
VLCD = 7.71 V;
VOP[6:0] = 0100000
24
0
1
0
0
0
0
0
0
control byte; Co = 0; RS = 1
25
0
0
0
1
1
1
1
1
data write; Y and X are
initialized to 0 by default, so
they are not set here
PJV
26
0
0
0
0
0
1
0
1
data write
PJV
27
0
0
0
0
0
1
1
1
data write
PJV
28
0
0
0
0
0
0
0
0
data write
PJV
29
0
0
0
1
1
1
1
1
data write
PJV
30
0
0
0
0
0
1
0
0
data write
PJV
31
0
0
0
1
1
1
1
1
data write; last data and stop
transmission
PJV
32
0
1
1
1
1
0
SA0
0
repeated start; slave address;
R/W = 0
PJV
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
44 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Table 18.
Step
Programming example for PCF8531 …continued
Serial bus byte
Display
Operation
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
33
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
PJV
34
0
0
0
0
0
0
0
1
H[1:0] independent
command; select function
and RAM command page
H[1:0] = 00
35
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
36
0
0
0
0
1
0
0
1
function and RAM command
page; select display setting
command page H[1:0] = 01
PJV
37
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
38
0
0
0
0
0
0
0
1
H[1:0] independent
command; select function
and RAM command page
H[1:0] = 00
39
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
40
0
0
0
0
1
1
0
1
display control; set inverse
video mode (D = 1; E = 1
and IM = 0)
PJV
41
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
PJV
42
1
0
0
0
0
0
0
0
set X address of RAM; set
address to ‘0000000’
PJV
43
0
1
0
0
0
0
0
0
control byte; Co = 0; RS = 1
PJV
44
0
0
0
0
0
0
0
0
data write
PJV
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
45 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
17. Package outline
Not applicable.
18. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
19. Packing information
Table 19.
Tray dimensions (see Figure 34)
Symbol
Description
Value
A
pocket pitch in x direction
13.72 mm
B
pocket pitch in y direction
4.17 mm
C
pocket width in x direction
12.34 mm
D
pocket width in y direction
2.05 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
x
number of pockets, x direction
3
y
number of pockets, y direction
10
[
$
&
\
'
%
)
(
PJV
Fig 34. Tray details
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
46 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
3&)
PJV
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die
surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad
location diagram (Figure 2) for the orientation and position of the type name on the die surface.
Fig 35. Tray alignment
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
47 of 56
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF8531
Product data sheet
20. Appendix
20.1 LCD graphic driver selection
Table 20.
Selection of LCD graphic drivers
Type name
Max display
resolution
rows  col.
Rev. 8 — 12 September 2014
All information provided in this document is subject to legal disclaimers.
Multiplex
rates
VDD1 (V)
PCA8539DUG 18  100
1:12, 1:18
2.5 to 5.5 2.5 to 5.5 4 to 16
45 to 360[1] Y
Y
40 to 105 I2C, SPI
bare die
Y
PCF8539DUG 18  100
1:12, 1:18
2.5 to 5.5 2.5 to 5.5 4 to 16
45 to 360[1] Y
Y
40 to 85
I2C, SPI
bare die
N
bare die
N
bare die
N
PCF8531U
34  128 or
33  128 plus
128 icons
1:17, 1:26,
1:34
PCF8811U
80  128 or
79  129 plus
128 icons
1:16 to 1:80 2 to 3.3
in steps of 8
[1]
VDD2 (V)
VLCD (V) ffr (Hz)
1.8 to 5.5 2.5 to 4.5 4 to 9
1.8 to 3.3 3 to 9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
Interface Package AECQ100
66
Y
Y
40 to 85
I2C
30 to 60[1]
Y
Y
40 to 85
I2C, SPI,
parallel
Can be selected by command.
PCF8531
34 x 128 pixel matrix driver
48 of 56
© NXP Semiconductors N.V. 2014. All rights reserved.
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
21. Abbreviations
Table 21.
Acronym
PCF8531
Product data sheet
Abbreviations
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
COG
Chip-On-Glass
DDRAM
Double Data Random Access Memory
EMC
ElectroMagnetic Compatibility
ESD
ElectroStatic Discharge
HBM
Human Body Model
HV
High Voltage
IC
Integrated Circuit
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MPU
MicroProcessor Unit
POR
Power-On Reset
RAM
Random Access Memory
RC
Resistance-Capacitance
TC
Temperature Coefficient
SCL
Serial CLock line
SDA
Serial DAta line
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
49 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
22. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10706 — Handling bare die
[3]
AN10853 — ESD and EMC sensitivity of IC
[4]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[5]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[6]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[7]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[9]
JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] UM10569 — Store and transport requirements
[12] UM10204 — I2C-bus specification and user manual
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
50 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
23. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8531 v.8
20140912
Product data sheet
-
PCF8531 v.7
Modifications:
PCF8531 v.7
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Increased VLCD, VDD1, VDD2, VDD3 max values in Table 15
Increased VDD2, VDD3 max values in Table 16
20131212
Product data sheet
-
PCF8531 v.6
PCF8531 v.6
20110516
Product data sheet
-
PCF8531 v.5
PCF8531 v.5
20100810
Product data sheet
-
PCF8531_4
PCF8531_4
20080613
Product data sheet
-
PCF8531_3
PCF8531_3
20000211
Product data sheet
-
PCF8531_2
PCF8531_2
19990810
Product data sheet
-
PCF8531_SDS_1
PCF8531_SDS_1
19990322
Product data sheet
-
-
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
51 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF8531
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
52 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
53 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Pad allocation table . . . . . . . . . . . . . . . . . . . . . .5
Alignment markers for PCF8531 . . . . . . . . . . . .5
Bonding pad dimensions . . . . . . . . . . . . . . . . . .6
Bonding pad description . . . . . . . . . . . . . . . . . .6
Y address . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Multiplex rates . . . . . . . . . . . . . . . . . . . . . . . . .21
Programming the required bias system . . . . . .22
Intermediate LCD bias voltages . . . . . . . . . . . .23
Parameter values for the HV generator
programming . . . . . . . . . . . . . . . . . . . . . . . . . .24
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . .25
Explanation for symbols in Table 12 . . . . . . . .26
Description of bits H, D and E, TC and S . . . .26
Limiting values [1] . . . . . . . . . . . . . . . . . . . . . . .34
Static characteristics . . . . . . . . . . . . . . . . . . . .35
Dynamic characteristics . . . . . . . . . . . . . . . . . .36
Programming example for PCF8531 . . . . . . . .43
Tray dimensions (see Figure 34) . . . . . . . . . . .46
Selection of LCD graphic drivers . . . . . . . . . . .48
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .49
Revision history . . . . . . . . . . . . . . . . . . . . . . . .51
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
54 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Block diagram of PCF8531 . . . . . . . . . . . . . . . . . .3
Bonding pad location for PCF8531 . . . . . . . . . . . .4
Alignment markers . . . . . . . . . . . . . . . . . . . . . . . . .5
Chip dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .6
Typical LCD driver waveforms . . . . . . . . . . . . . . .16
LCD waveforms, icon mode, multiplex rate 1:2 . .17
DDRAM to display data mapping. . . . . . . . . . . . .18
RAM format and addressing . . . . . . . . . . . . . . . .19
Sequence of writing data bytes into RAM with
vertical addressing (V = 1) . . . . . . . . . . . . . . . . . .19
Sequence of writing data bytes into RAM with
horizontal addressing (V = 0). . . . . . . . . . . . . . . .19
Voltage divider chain . . . . . . . . . . . . . . . . . . . . . .22
VLCD programming of PCF8531. . . . . . . . . . . . . .24
VLCD as a function of liquid crystal temperature. .25
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Definition of START and STOP conditions. . . . . .28
System configuration . . . . . . . . . . . . . . . . . . . . . .29
Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .30
Slave address and control byte . . . . . . . . . . . . . .31
Master transmits to slave receiver; write mode . .31
Device protection diagrams . . . . . . . . . . . . . . . . .32
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I2C-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Supply current as a function of supply voltage
2 and supply voltage 3 . . . . . . . . . . . . . . . . . . . . .38
Supply current as a function of LCD supply voltage;
different multiplication factors . . . . . . . . . . . . . . .38
LCD supply voltage as a function of temperature 38
Supply current as a function of LCD supply
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Supply current as a function of frequency . . . . . .39
Supply current as a function of LCD supply
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Typical system configuration . . . . . . . . . . . . . . . .40
Recommended VDD connections for internal VLCD
generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Recommended VLCD connections for internal VLCD
generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Recommended VDD connections for external VLCD
generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chip-on-glass application . . . . . . . . . . . . . . . . . .42
Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
55 of 56
PCF8531
NXP Semiconductors
34 x 128 pixel matrix driver
28. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
8
8.1
9
9.1
9.2
9.2.1
9.2.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
10
10.1
10.1.1
10.1.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 14
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 14
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 14
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Display data RAM . . . . . . . . . . . . . . . . . . . . . . 14
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 14
Address counter . . . . . . . . . . . . . . . . . . . . . . . 14
Display address counter . . . . . . . . . . . . . . . . . 14
Command decoder . . . . . . . . . . . . . . . . . . . . . 14
Bias voltage generator . . . . . . . . . . . . . . . . . . 15
VLCD generator . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Column driver outputs. . . . . . . . . . . . . . . . . . . 15
Row driver outputs . . . . . . . . . . . . . . . . . . . . . 15
LCD waveforms and DDRAM to data
mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Set Y address . . . . . . . . . . . . . . . . . . . . . . . . . 21
Set X address . . . . . . . . . . . . . . . . . . . . . . . . . 21
Set multiplex rate . . . . . . . . . . . . . . . . . . . . . . 21
Display control (D, E, and IM). . . . . . . . . . . . . 21
Set bias system . . . . . . . . . . . . . . . . . . . . . . . 22
LCD bias voltage . . . . . . . . . . . . . . . . . . . . . . 23
Set VLCD value . . . . . . . . . . . . . . . . . . . . . . . . 23
Voltage multiplier control S[1:0] . . . . . . . . . . . 24
Temperature compensation . . . . . . . . . . . . . . 24
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 28
Characteristics of the I2C-bus. . . . . . . . . . . . . 28
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
START and STOP conditions . . . . . . . . . . . . . 28
10.1.3
System configuration . . . . . . . . . . . . . . . . . . .
10.1.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
10.2
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
10.3
Command decoder . . . . . . . . . . . . . . . . . . . .
11
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
12
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
14
Static characteristics . . . . . . . . . . . . . . . . . . .
15
Dynamic characteristics. . . . . . . . . . . . . . . . .
16
Application information . . . . . . . . . . . . . . . . .
16.1
Typical system configuration . . . . . . . . . . . . .
16.2
Power supply connections for internal VLCD
generation . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3
Power supply connections for external VLCD
generation . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4
Information about VLCD connections . . . . . . .
16.5
Chip-on-glass application. . . . . . . . . . . . . . . .
16.6
Programming example. . . . . . . . . . . . . . . . . .
17
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
18
Handling information . . . . . . . . . . . . . . . . . . .
19
Packing information . . . . . . . . . . . . . . . . . . . .
20
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.1
LCD graphic driver selection . . . . . . . . . . . . .
21
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
22
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Revision history . . . . . . . . . . . . . . . . . . . . . . .
24
Legal information . . . . . . . . . . . . . . . . . . . . . .
24.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
24.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
24.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Contact information . . . . . . . . . . . . . . . . . . . .
26
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
30
31
32
33
34
35
36
40
40
40
41
41
42
43
46
46
46
48
48
49
50
51
52
52
52
52
53
53
54
55
56
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 September 2014
Document identifier: PCF8531
Similar pages