Data Sheet

PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
Product data sheet
1. General description
The PCE85176AUG is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. The
PCE85176AUG is compatible with most microcontrollers and communicates via the
two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM
with auto-incremented addressing and by display memory switching (static and duplex
drive modes).
For a selection of NXP LCD segment drivers, see Table 31 on page 40.
2. Features and benefits















1.
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
 Up to 20 7-segment alphanumeric characters
 Up to 10 14-segment alphanumeric characters
 Any graphics of up to 160 elements
40  4-bit RAM for display data storage
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
 From 2.5 V for low-threshold LCDs
 Up to 5.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
No external components required
Compatible with Chip-On-Glass (COG) technology
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCE85176AUG
Name
Description
Version
bare die
59 bumps
PCE85176AUG
3.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCE85176AUG/DA
PCE85176AUG/DAKP
chip with gold bumps in tray
1
935304709026
4. Marking
Table 3.
Marking codes
Product type number
Marking code
PCE85176AUG/DA
PC85176A-1
5. Block diagram
%3
%3
%3
%3
6WR6
9/&'
%$&.3/$1(
2873876
',63/$<6(*0(17
2873876
/&'
92/7$*(
6(/(&725
',63/$<
5(*,67(5
',63/$<
&21752//(5
/&'%,$6
*(1(5$725
287387%$1.6(/(&7
$1'%/,1.&21752/
966
&/.
&/2&.6(/(&7
$1'7,0,1*
26&
26&,//$725
%/,1.(5
7,0(%$6(
',63/$<5$0
3&($8*
&200$1'
'(&2'(5
:5,7('$7$
&21752/
'$7$32,17(5$1'
$872,1&5(0(17
9''
6&/
6'$
,1387
),/7(56
O&%86
&21752//(5
6$
Fig 1.
7WR7
DDD
Block diagram of PCE85176AUG
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
6. Pinning information
6
6
6.1 Pinning
6
6
%3
%3
%3
%3
9/&'
966
7
7
26&
7
6$
9''
7
&/.
6&/
3&($8*
6
6
4
[
6
\
6'$
6
&
DDD
Viewed from active side. For mechanical details, see Figure 27.
Fig 2.
Pinning diagram for PCE85176AUG (bare die)
6.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
PCE85176AUG
Product data sheet
Symbol
Pin
Type
Description
SDA
1, 58, 59
input/output
I2C-bus serial data line
SCL
2, 3
input
I2C-bus serial clock
T1
4
input/output
test pin; must be left open
CLK
5
input/output
clock line
VDD
6
supply
supply voltage
OSC
7
input
internal oscillator enable
T2 to T4
8 to 10
input
test pins; must be tied to VSS
SA0
11
input
I2C-bus address input
VSS
12
supply
ground supply voltage
VLCD
13
supply
LCD supply voltage
BP0, BP2,
BP1, BP3
14 to 17
output
LCD backplane outputs
S0 to S39
18 to 57
output
LCD segment outputs
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7. Functional description
The PCE85176AUG is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 9). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
40 segments.
7.1 Commands of PCE85176AUG
The commands available to the PCE85176AUG are defined in Table 5.
Table 5.
Definition of PCE85176AUG commands
Bit position labeled as - is not used.
Command
Operation Code
Reference
Bit
7
6
5
4
3
2
1
mode-set
C
1
0
-
E
B
M[1:0]
0
load-data-pointer
C
0
P[5:0]
initialize-RAM
C
1
1
0
0
0
0
0
Table 12
bank-select
C
1
1
1
1
0
I
O
Table 14
blink-select
C
1
1
1
0
AB
BF[1:0]
Table 8
Table 10
Table 16
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 22. When this bit is set logic 1, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that
the command byte is the last in the transfer. Further bytes are regarded as display data
(see Table 6).
PCE85176AUG
Product data sheet
Table 6.
C bit description
Bit
Symbol
7
C
Value
Description
continue bit
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command as
well
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 7.
Mode-set command bit allocation
Bit position labeled as - is not used.
Bit
7
6
5
4
3
2
Symbol
C
1
0
-
E
B
1
0
M[1:0]
Table 8.
Mode-set command bit description
Bit position labeled as - is not used.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 6
6, 5
-
10
fixed value
4
-
-
unused
3
E
2
0
disabled (blank)[2]
1
enabled
LCD bias configuration[3]
B
1 to 0
[1]
display status[1]
0
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00
1:4 multiplex; BP0, BP1, BP2, BP3
The possibility to disable the display allows implementation of blinking under external control.
[2]
The display is disabled by setting all backplane and segment outputs to VLCD.
[3]
Not applicable for static drive mode.
7.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data is sent to.
Table 9.
Load-data-pointer command bit allocation
Bit
7
6
Symbol
C
0
5
4
3
2
1
0
P[5:0]
Table 10. Load-data-pointer command bit description
See Section 7.3.1.
PCE85176AUG
Product data sheet
Bit
Symbol
Value
Description
7
C
0, 1
see Table 6
6
0
0
fixed value
5 to 0
P[5:0]
000000 to
100111
6-bit binary value, 0 to 39; transferred to
the data pointer to define one of 40 display
RAM addresses
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.1.3 Command: Initialize-RAM
Table 11.
Initialize-RAM command bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
C
1
1
0
0
0
0
0
Table 12. Initialize-RAM command bit description
See Section 7.3.1.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 6
6 to 0
-
1100000
initializing the RAM access
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
Table 13.
Bank-select command bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
C
1
1
1
1
0
I
O
Table 14. Bank-select command bit description
See Section 7.3.4.
Bit
Symbol
Value
Description
1:2 multiplex[1]
Static
7
C
0, 1
6 to 2
-
11110
1
I
see Table 6
fixed value
input bank selection; storage of arriving
display data
0
1
0
[1]
PCE85176AUG
Product data sheet
O
RAM row 0
RAM rows 0 and 1
RAM row 2
RAM rows 2 and 3
output bank selection; retrieval of LCD
display data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 15.
Blink-select command bit allocation
Bit
7
6
5
4
3
2
Symbol
C
1
1
1
0
AB
1
0
BF[1:0]
Table 16. Blink-select command bit description
See Section 7.2.4.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 6
6 to 3
-
1110
fixed value
2
AB
1 to 0
blink mode selection
0
normal blinking[1]
1
alternate RAM bank blinking[2]
BF[1:0]
blink frequency selection (see Table 17)
00
off
01
1
10
2
11
3
[1]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.2 Clock and frame frequency
7.2.1 Internal clock
The internal logic of the PCE85176AUG and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS.
7.2.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.2.3 Timing
The PCE85176AUG timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
f clk
the internal or an external clock: f fr = ------24
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.2.4 Blinking
The display blinking capabilities of the PCE85176AUG are very versatile. The whole
display can blink at frequencies selected by the blink-select command (see Table 16). The
blink frequencies are derived from the clock frequency. The ratio between the clock and
blink frequencies depends on the selected blink mode (see Table 17).
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. With the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blink frequency. This mode can also be
specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 8).
Table 17.
Blink frequencies
Blink mode
Blink frequency[1]
off
-
1
f clk
f blink = --------768
2
f clk
f blink = -----------1536
3
f clk
f blink = -----------3072
[1]
The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see
Table 25.
7.3 Display RAM
The display RAM is a static 40  4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
GLVSOD\5$0DGGUHVVHVFROXPQVVHJPHQWRXWSXWV6
GLVSOD\5$0ELWV
URZV
EDFNSODQHRXWSXWV
%3
PEH
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 3.
Display RAM bitmap
When display data is transmitted to the PCE85176AUG, the received display bytes are
stored in the display RAM in accordance with the selected LCD drive mode. The data is
stored as it arrives and depending on the current multiplex drive mode the bits are stored
singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a
7-segment display showing all drive modes is given in Figure 4; the RAM filling
organization depicted applies equally to other LCD types.
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.3.2)
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 48
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
/&'VHJPHQWV
6Q
6Q
VWDWLF
E
F
URZV
GLVSOD\5$0 URZVEDFNSODQH
RXWSXWV%3
'3
D
6Q
%3
F
6Q
'3
G
6Q
D
E
6Q
%3
F
10 of 48
© NXP Semiconductors N.V. 2015. All rights reserved.
%3
J
H
%3
F
G
Q
Q
F
[
[
[
E
[
[
[
D
[
[
[
I
[
[
[
J
[
[
[
H
[
[
[
G
[
[
[
'3
[
[
[
06%
/6%
F E D
I
J H G '3
URZV
GLVSOD\5$0 URZVEDFNSODQH
RXWSXWV%3
Q
Q
Q
Q
D
E
[
[
I
J
[
[
H
F
[
[
G
'3
[
[
06%
D E
/6%
I
J H F G '3
Q
URZV
GLVSOD\5$0 E
URZVEDFNSODQH
'3
RXWSXWV%3
F
[
Q
Q
D
G
J
[
I
H
[
[
06%
/6%
E '3 F D G J
I
H
'3
%3
Q
URZV
GLVSOD\5$0 D
URZVEDFNSODQH
F
%3 RXWSXWV%3 E
'3
Q
I
H
J
G
06%
D F E '3 I
/6%
H J G
DDM
x = data bit unchanged.
Fig 4.
Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCE85176AUG
E
I
PXOWLSOH[
Q
FROXPQV
GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV
E\WH
E\WH
E\WH
E\WH
E\WH
D
6Q
6Q
%3
'3
G
Q
FROXPQV
GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV
E\WH
E\WH
E\WH
J
H
Q
%3
I
PXOWLSOH[
Q
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
All information provided in this document is subject to legal disclaimers.
E
H
Q
FROXPQV
GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV
E\WH
E\WH
J
6Q
Q
%3
I
PXOWLSOH[
%3
6Q
6Q
G
6Q
6Q
6Q
J
H
WUDQVPLWWHGGLVSOD\E\WH
FROXPQV
GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV
E\WH
I
6Q
GLVSOD\5$0ILOOLQJRUGHU
D
6Q
6Q
/&'EDFNSODQHV
NXP Semiconductors
PCE85176AUG
Product data sheet
GULYHPRGH
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.3.1 Writing to RAM
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM.
The sequence always commences with the initialize-RAM command (see Table 12).
Following this command, the data pointer has to be set to the desired RAM address using
the load-data-pointer command (see Table 10). After this an arriving data byte is stored at
the display RAM address indicated by the data pointer. The RAM writing procedure is
illustrated in Figure 5 and the filling order of the RAM is shown in Figure 4.
6HQGLQLWLDOL]H5$0
FRPPDQG
6HWGDWDSRLQWHU
3>@
:ULWHWR5$0
6723
DDD
Fig 5.
RAM writing procedure
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, then the state of the data pointer is unknown.
So, the data pointer must be rewritten before further RAM accesses.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.3.2 Writing to RAM in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 18 (see Figure 4 as
well).
Table 18. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 19.
Table 19. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 19 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• The data-pointer (see Section 7.3.1 on page 11) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used. But it has to be considered in the module
layout process as well as in the driver software design.
7.3.3 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. In this case, the additional bits will be
discarded.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.3.4 Bank selection
7.3.4.1
Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCE85176AUG includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.3.4.2
Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 14). The input bank selector functions independently to the output bank selector.
7.3.4.3
RAM bank switching
The PCE85176AUG includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see
Figure 6). The RAM bank switching gives the provision for preparing display information in
an alternative bank and to be able to switch to it once it is complete.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
GLVSOD\5$0DGGUHVVHVFROXPQVVHJPHQWRXWSXWV6
6WDWLFGULYHPRGH
GLVSOD\5$0ELWVURZVEDFNSODQHRXWSXWV%3
EDQN
EDQN
0XOWLSOH[GULYHPRGH
EDQN
EDQN
DDD
Fig 6.
RAM banks in static and multiplex driving mode 1:2
There are two banks; bank 0 and bank 1. Figure 6 shows the location of these banks
relative to the RAM map. Input and output banks can be set independently from one
another with the Bank-select command (see Table 14). Figure 7 shows the concept.
LQSXWEDQNVHOHFWLRQ
FRQWUROVWKHLQSXW
GDWDSDWK
RXWSXWEDQNVHOHFWLRQ
FRQWUROVWKHRXWSXW
GDWDSDWK
%$1.
0,&52&21752//(5
5$0
',63/$<
%$1.
DDD
Fig 7.
Bank selection
In the static drive mode, the bank-select command may request the contents of row 2 to
be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
In Figure 8 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
RXWSXW5$0EDQN
URZV
WRWKH/&'
GLVSOD\5$0URZV
EDFNSODQHRXWSXWV %3
WRWKH5$0
LQSXW5$0EDQN
DDD
Fig 8.
Example of the Bank-select command with multiplex drive mode 1:2
7.4 Initialization
At power-on the status of the I2C-bus and the registers of the PCE85176AUG is
undefined. Therefore the PCE85176AUG should be initialized as quickly as possible after
power-on to ensure a proper bus communication and to avoid display artifacts. The
following instructions should be accomplished for initialization:
• I2C-bus (see Section 8) initialization
– generating a START condition
– sending 0h and ignoring the acknowledge
– generating a STOP condition
• Mode-set command (see Table 8), setting
– bit E = 0
– bit B to the required LCD bias configuration
– bits M[1:0] to the required LCD drive mode
• Load-data-pointer command (see Table 10), setting
– bits P[5:0] to 0h (or any other required address)
• Initialize-RAM command (see Table 12)
• Bank-select command (see Table 14), setting
– bit I to 0
– bit O to 0
• Blink-select command (see Table 16), setting
– bit AB to 0 or 1
– bits BF[1:0] to 00 (or to a desired blinking mode)
• writing meaningful information (for example, a logo) into the display RAM
After the initialization, the display can be switched on by setting bit E = 1 with the
mode-set command.
7.5 Possible display configurations
The possible display configurations of the PCE85176AUG is depending on the number of
active backplane outputs required. A selection of display configurations is shown in
Table 20. All of these configurations can be implemented in the typical system shown in
Figure 10.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
GRWPDWUL[
VHJPHQWZLWKGRW
VHJPHQWZLWKGRWDQGDFFHQW
DDD
Fig 9.
Example of displays suitable for PCE85176AUG
Table 20.
Selection of possible display configurations
Number of
Backplanes
4
Icons
Digits/Characters
160
7-segment[1]
14-segment[2]
Dot matrix/
Elements
20
10
160 (4  40)
3
120
15
7
120 (3  40)
2
80
10
5
80 (2  40)
1
40
5
2
40 (1  40)
[1]
7 segment display has 8 elements including the decimal point.
[2]
14 segment display has 16 elements including decimal point and accent dot.
9''
9/&'
WU
5”
&%
Q)
9''
VHJPHQWGULYHV
6'$
+267
0,&52
&21752//(5
Q)
/&'3$1(/
6&/
3&(
26&
7
7
7
EDFNSODQHV
XSWR
HOHPHQWV
6$ 966
966
DDD
The resistance of the power lines must be kept to a minimum.
Fig 10. Typical system configuration
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCE85176AUG. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD,
VSS, and VLCD) and the LCD panel chosen for the application.
7.5.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
7.5.2 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.5.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 21.
Table 21.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off  RMS 
------------------------V LCD
V on  RMS 
-----------------------V LCD
V on  RMS 
D = -----------------------V off  RMS 
static
1
2
static
0
1

3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
1:3 multiplex 3
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:2 multiplex 2
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on  RMS  =
V LCD
a 2 + 2a + n
-----------------------------2
n  1 + a
(1)
where the values for n are
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off  RMS  =
V LCD
a 2 – 2a + n
-----------------------------2
n  1 + a
(2)
Discrimination is a term which is defined as the ratio of the on and off RMS voltages
(Von(RMS) to Voff(RMS)) across a segment. It can be thought of as a measurement of
contrast. Discrimination is determined from Equation 3:
V on  RMS 
D = ---------------------- =
V off  RMS 
2
a + 2a + n
--------------------------2
a – 2a + n
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6  V off  RMS  = 2.449V off  RMS 
4  3
- = 2.309V off  RMS 
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off  RMS  when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.5.3.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 11. For a good contrast performance, the following rules should be followed:
V on  RMS   V th  on 
(4)
V off  RMS   V th  off 
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
5HODWLYH7UDQVPLVVLRQ
9WKRII
2))
6(*0(17
9WKRQ
*5(<
6(*0(17
9506>9@
21
6(*0(17
DDD
Fig 11. Electro-optical characteristic: relative transmission curve of the liquid
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
19 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.5.4 LCD drive mode waveforms
7.5.4.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in
Figure 12.
7IU
/&'VHJPHQWV
9/&'
%3
966
VWDWH
RQ
9/&'
VWDWH
RII
6Q
966
9/&'
6Q
966
D:DYHIRUPVDWGULYHU
9/&'
VWDWH
9
9/&'
9/&'
VWDWH
9
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t)  VBP0(t).
Voff(RMS) = 0 V.
Fig 12. Static drive mode waveforms
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
20 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.5.4.2
1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCE85176AUG allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 13
and Figure 14.
7IU
9/&'
%3
/&'VHJPHQWV
9/&'
966
VWDWH
9/&'
%3
VWDWH
9/&'
966
9/&'
6Q
966
9/&'
6Q
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 13. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
21 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7IU
9/&'
%3
%3
/&'VHJPHQWV
9/&'
9/&'
966
VWDWH
9/&'
9/&'
VWDWH
9/&'
966
9/&'
6Q
9/&'
9/&'
966
9/&'
6Q
9/&'
9/&'
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9/&'
9
9/&'
9/&'
9/&'
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 14. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
22 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.5.4.3
1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 15.
7IU
%3
9/&'
9/&'
/&'VHJPHQWV
9/&'
966
VWDWH
9/&'
%3
%3
6Q
6Q
6Q
VWDWH
9/&'
9/&'
966
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 15. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
23 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.5.4.4
1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 16.
7IU
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
VWDWH
9/&'
9/&'
9/&'
9
9/&'
9/&'
9/&'
VWDWH
9/&'
9/&'
9/&'
9
9/&'
9/&'
9/&'
/&'VHJPHQWV
VWDWH
VWDWH
D:DYHIRUPVDWGULYHU
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 16. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
24 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
7.6 Backplane and segment outputs
7.6.1 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the
same signals and may also be paired to increase the drive capabilities.
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.6.2 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
25 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 17).
6'$
6&/
GDWDOLQH
VWDEOH
GDWDYDOLG
FKDQJH
RIGDWD
DOORZHG
PED
Fig 17. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P.
The START and STOP conditions are illustrated in Figure 18.
6'$
6'$
6&/
6&/
6
3
67$57FRQGLWLRQ
6723FRQGLWLRQ
PEF
Fig 18. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 19.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
26 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
0$67(5
75$160,77(5
5(&(,9(5
6/$9(
75$160,77(5
5(&(,9(5
6/$9(
5(&(,9(5
0$67(5
75$160,77(5
5(&(,9(5
0$67(5
75$160,77(5
6'$
6&/
PJD
Fig 19. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 20.
GDWDRXWSXW
E\WUDQVPLWWHU
QRWDFNQRZOHGJH
GDWDRXWSXW
E\UHFHLYHU
DFNQRZOHGJH
6&/IURP
PDVWHU
6
67$57
FRQGLWLRQ
FORFNSXOVHIRU
DFNQRZOHGJHPHQW
PEF
Fig 20. Acknowledgement of the I2C-bus
8.5 I2C-bus controller
The PCE85176AUG acts as an I2C-bus slave receiver. It does not initiate I2C-bus
transfers or transmit data to an I2C-bus master receiver. The only data outputs from the
PCE85176AUG are the acknowledge signals.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
27 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCE85176AUG. The entire I2C-bus slave address byte is shown in Table 22.
Table 22.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
0
LSB
1
1
1
0
0
SA0
R/W
The PCE85176AUG is a write-only device and will not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCE85176AUG
responds to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for
logic 1).
The I2C-bus protocol is shown in Figure 21. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible
PCE85176AUG slave addresses available.
5:
6
DFNQRZOHGJHE\
3&(
DFNQRZOHGJHE\
3&(
VODYHDGGUHVV
6
$ $ &
E\WH
&200$1'
$ &
Q•E\WH
&200$1'
$
3
Q•E\WH
DDD
Fig 21. I2C-bus protocol
The last command byte sent is identified by resetting its most significant bit, continuation
bit C (see Figure 22).
06%
&
/6%
5(672)23&2'(
PVD
Fig 22. Format of command byte
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
28 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
9. Internal circuitry
9''
9''
966
966
9/&'
966
966
DDD
(1) SA0, CLK, OSC, T1 to T4.
(2) BP0 to BP3, S0 to S39.
(3) VLCD, SCL, SDA.
Fig 23. Device protection diagram
10. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
29 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
11. Limiting values
Table 23. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+6.5
V
VLCD
LCD supply voltage
0.5
+6.5
V
VI
input voltage
on each of the pins CLK,
SDA, SCL, T1 to T4, SA0,
OSC
0.5
+6.5
V
VO
output voltage
on each of the pins S0 to
S39, BP0 to BP3
0.5
+6.5
V
II
input current
10
+10
mA
IO
output current
10
+10
mA
IDD
supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
VESD
electrostatic discharge
voltage
Ilu
-
100
mW
[1]
-
3500
V
latch-up current
[2]
-
100
mA
Tstg
storage temperature
[3]
55
+150
C
Tamb
ambient temperature
40
+85
C
[1]
HBM
operating device
Pass level; Human Body Model (HBM), according to Ref. 9 “JESD22-A114”
[2]
Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[3]
According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
30 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
12. Static characteristics
Table 24. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
[1]
2.5
-
5.5
V
supply current
[2]
-
3.5
7
A
-
2.7
-
A
-
23
32
A
-
13
-
A
VSS
-
0.3VDD
V
0.7VDD
-
VDD
V
on pin CLK
1
-
-
mA
on pin SDA
3
-
-
mA
IDD
fclk(ext) = 1536 Hz
VDD = 3.0 V; Tamb = 25 C
IDD(LCD)
LCD supply current
[2]
fclk(ext) = 1536 Hz
VLCD = 3.0 V;
Tamb = 25 C
Logic[3]
VIL
LOW-level input voltage
on pins CLK, T2 to T4, OSC,
SA0, SCL, SDA
VIH
HIGH-level input voltage
on pins CLK, OSC, T2 to T4,
SA0, SCL, SDA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 5 V
[4][5]
IOH(CLK)
HIGH-level output current
on pin CLK
output source current;
VOH = 4.6 V; VDD = 5 V
1
-
-
mA
IL
leakage current
VI = VDD or VSS;
on pins CLK, SCL, SDA, T2
to T4 and SA0
1
-
+1
A
IL(OSC)
leakage current on pin
OSC
VI = VDD
1
-
+1
A
CI
input capacitance
-
-
7
pF
100
-
+100
mV
on pins BP0 to BP3
-
1.5
-
k
on pins S0 to S39
-
6.0
-
k
[6]
LCD outputs
VO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
RO
output resistance
VLCD = 5 V
[7]
[1]
VLCD > 3 V for 1⁄3 bias.
[2]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3]
The I2C-bus interface of PCE85176AUG is 5 V tolerant.
[4]
When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 23 (see Figure 23
as well).
[5]
Propagation delay of driver between clock (CLK) and LCD driving signals.
[6]
Periodically sampled, not 100 % tested.
[7]
Outputs measured one at a time.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
31 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
13. Dynamic characteristics
Table 25. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
fclk(int)
internal clock frequency
fclk(ext)
external clock frequency
ffr
frame frequency
[1]
1440
1850
2640
Hz
960
-
2640
Hz
internal clock
60
77
110
Hz
external clock
40
-
110
Hz
tclk(H)
HIGH-level clock time
60
-
-
s
tclk(L)
LOW-level clock time
60
-
-
s
-
-
30
s
tPD(drv)
driver propagation delay
VLCD = 5 V
[2]
I2C-bus[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tr
rise time of both SDA and
SCL signals
-
-
0.3
s
-
-
1.0
s
tf
fall time of both SDA and
SCL signals
-
-
0.3
s
Cb
capacitive load for each
bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
fSCL = 400 kHz
fSCL < 125 kHz
on the I2C-bus
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
Not tested in production.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
32 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
IFON
WFON+
WFON/
9''
&/.
9''
%3Q6Q
W3'GUY
DDD
Fig 24. Driver timing waveforms
6'$
W%8)
W/2:
WI
6&/
W+'67$
WU
W+''$7
W+,*+
W68'$7
6'$
W6867$
W68672
PJD
Fig 25. I2C-bus timing waveforms
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
33 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
14. Application information
14.1 Track resistance on the I2C-bus lines
The SDA line of an I2C device is an open-drain output which therefore needs an external
pull-up resistor (RPU). In Chip-On Glass (COG) applications, the track resistance (RITO)
from the SDA pin to the SDA system line can be significant. For this reason, it is possible
that the two resistances are forming a voltage divider. Such a divider could prevent that
the acknowledge cycle generated by the PCE85176AUG can be interpreted as logic 0 by
the master. To guarantee a valid LOW level, it is necessary that the RITO from the SDA pin
to the SDA system line is minimized.
9''
/&'JODVV
538
0&8
/&'GULYHU
5,6'$
6'$
92ORJ
6'$
966
5,966
966
966
DDD
(1) Includes track resistance RITO.
Fig 26. Track resistances on the SDA and VSS line
The logic output voltage is calculated with Equation 6:
R I(SDA) + R I(VSS)
V O(log) = -------------------------------------------------------  V DD
R PU + R I(SDA) + R I(VSS)
(6)
For further information on this topic, see Ref. 1 “AN10170”.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
34 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
15. Bare die outline
%DUHGLHEXPSV
3&($8*
'
\
[
<
(
;
/
$
E
$
$
GHWDLO;
GHWDLO<
1RWHV
0DUNLQJFRGH3&$
)LJXUHQRWGUDZQWRVFDOH
2XWOLQH
YHUVLRQ
SFHDXJBGR
5HIHUHQFHV
,(&
-('(&
-(,7$
(XURSHDQ
SURMHFWLRQ
,VVXHGDWH
3&($8*
Fig 27. Bare die outline of PCE85176AUG
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
35 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Table 26. Dimensions of PCE85176AUG
Original dimensions are in mm.
Unit (mm)
A
A1
A2
b
D
E
L
max
-
-
-
-
-
-
-
nom
0.40
0.015
0.38
0.051
2.1
1.8
0.054
min
-
-
-
-
-
-
-
Table 27. Bump location for PCE85176AUG
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip (see Figure 27).
Symbol
PCE85176AUG
Product data sheet
Bump
Location
Pitch
Description
X (m)
Y (m)
X (m) Y (m)
SDA
1
52.4
843.7
-
-
I2C-bus serial data input/output
SCL
2
91.5
843.7
143.9
0
I2C-bus serial clock input
SCL
3
163.5
843.7
72
0
T1
4
347.6
843.7
184.1
0
CLK
5
451.1
843.7
103.5
0
external clock input/output
VDD
6
559.1
843.7
108
0
supply voltage
OSC
7
722.9
843.7
163.8
0
internal oscillator enable input
T2
8
817.8
843.7
94.9
0
test pins
T3
9
972.5
612.9
-
-
T4
10
972.5
495.9
0
117
SA0
11
972.5
378.9
0
117
I2C-bus address input; bit 0
VSS
12
972.5
203.4
0
175.5
ground supply voltage
test pin
VLCD
13
972.5
27.8
0
231.2
LCD supply voltage
BP0
14
972.5
174.5
0
146.7
LCD backplane outputs
BP2
15
972.5
250.8
0
76.3
BP1
16
972.5
327.0
0
76.2
BP3
17
972.5
403.2
0
76.2
S0
18
972.5
511.2
0
108
S1
19
972.5
583.2
0
72
S2
20
972.5
655.2
0
72
S3
21
972.5
727.2
0
72
S4
22
329.2
843.7
-
-
S5
23
246.0
843.7
83.2
0
S6
24
162.7
843.7
83.3
0
S7
25
79.5
843.7
83.2
0
S8
26
3.8
843.7
83.3
0
S9
27
87.0
843.7
83.2
0
S10
28
170.3
843.7
83.3
0
S11
29
253.5
843.7
83.2
0
S12
30
336.8
843.7
83.3
0
S13
31
420.0
843.7
83.2
0
S14
32
503.3
843.7
83.3
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
LCD segment outputs
© NXP Semiconductors N.V. 2015. All rights reserved.
36 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Table 27. Bump location for PCE85176AUG …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip (see Figure 27).
Symbol
Bump
Location
X (m)
Pitch
Y (m)
Description
X (m) Y (m)
S15
33
586.5
843.7
83.2
0
S16
34
669.8
843.7
83.3
0
S17
35
753.0
843.7
83.2
0
S18
36
972.5
643.6
-
-
S19
37
972.5
559.6
0
84
S20
38
972.5
476.2
0
83.4
S21
39
972.5
392.8
0
83.4
S22
40
972.5
309.4
0
83.4
S23
41
972.5
225.9
0
83.5
S24
42
972.5
142.5
0
83.4
S25
43
972.5
59.1
0
83.4
S26
44
972.5
24.4
0
83.5
S27
45
972.5
107.8
0
83.4
S28
46
972.5
191.2
0
83.4
S29
47
972.5
274.7
0
83.5
S30
48
972.5
358.1
0
83.4
S31
49
972.5
441.5
0
83.4
S32
50
972.5
525.0
0
83.5
S33
51
972.5
607.6
0
82.6
S34
52
753.0
843.7
-
-
S35
53
681.0
843.7
72
0
S36
54
609.0
843.7
72
0
S37
55
537.0
843.7
72
0
S38
56
465.0
843.7
72
0
S39
57
393.0
843.7
72
0
SDA
58
214.4
843.7
178.6
0
SDA
59
124.4
843.7
90
0
5()
4
LCD segment outputs
I2C-bus serial data input/output
5()
&
DDD
The approximate positions of the alignment marks are shown in Figure 27.
Fig 28. Alignment marks of PCE85176AUG
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
37 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Table 28. Alignment marks
All x/y coordinates represent the position of the REF point (see Figure 28) with respect to the center
(x/y = 0) of the chip (see Figure 2, and Figure 27).
Symbol
Location
Dimension (m)
X (m)
Y (m)
Q1
987.1
778.0
45  45
C1
955.4
778.0
45  45
Table 29.
Gold bump hardness
Type number
Min
Max
Unit[1]
PCE85176AUG/DA
60
120
HV
[1]
Pressure of diamond head: 10 g to 50 g.
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
17.1 Tray information for PCE85176AUG
$
*
&
+
[
'
)
%
\
\
(
[
DDD
Fig 29. Tray details for PCE85176AUG
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
38 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Table 30. Dimensions of tray for PCE85176AUG
See Figure 29.
Symbol
Description
Value
A
pocket pitch in x direction
3.2 mm
B
pocket pitch in y direction
3.0 mm
C
pocket width in x direction
2.2 mm
D
pocket width in y direction
1.9 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
G
pitch from edge of tray to pocket center in
x direction
4.6 mm
H
pitch from edge of tray to pocket center in
y direction
4.4 mm
N
number of pockets, x direction
14
M
number of pockets, y direction
15
The orientation of the IC in a pocket is indicated by the position of the IC type name on the
die surface with respect to the chamfer on the upper left corner of the tray (see Figure 30).
Refer to the bare die outline drawing (see Figure 27) for the orientation and position of the
type name on the die surface.
PDUNLQJFRGH
DDM
Fig 30. Tray alignment for PCE85176AUG tray
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
39 of 48
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCE85176AUG
Product data sheet
18. Appendix
18.1 LCD segment driver selection
Table 31.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
PCA8553DTT
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
88
-
-
-
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA8543AHL
60
60
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
Y
Y
40 to 95
I2C
TQFP64
Y
Y
Y
40 to 95
SPI
TQFP64
Y
Y
40 to 105
I2C
LQFP80
Y
Y
40 to 105
I2C
Bare die
Y
PCF8537BH
44
88
-
176 276 352 -
40 of 48
© NXP Semiconductors N.V. 2015. All rights reserved.
PCA8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
2.5 to 5.5 2.5 to 9
60 to
300[1]
60 to
300[1]
PCA9620H
PCA9620U
60
60
120 120 -
240 320 480 240 320 480 -
2.5 to 5.5 2.5 to 9
Y
Y
PCF8576DU
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
N
PCE85176AUG
PCA8536AT
I2C
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
PCA85134H
-
176 -
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Software programmable.
[2]
Hardware selectable.
-
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
PCE85176AUG
41 of 48
© NXP Semiconductors N.V. 2015. All rights reserved.
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
All information provided in this document is subject to legal disclaimers.
[1]
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
NXP Semiconductors
PCE85176AUG
Product data sheet
Table 31.
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
19. Abbreviations
Table 32.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DC
Direct Current
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
RAM
Random Access Memory
RC
Resistance and Capacitance
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta Line
20. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10365 — Surface mount reflow soldering description
[3]
AN10439 — Wafer Level Chip Size Package
[4]
AN10706 — Handling bare die
[5]
AN10853 — ESD and EMC sensitivity of IC
[6]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[7]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[8]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[9]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] R_10015 — Chip-On-Glass (COG) - a cost-effective and reliable technology for
LCD displays
[13] UM10204 — I2C-bus specification and user manual
[14] UM10569 — Store and transport requirements
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
42 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
21. Revision history
Table 33.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCE85176AUG v.1
20150112
Product data sheet
-
-
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
43 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCE85176AUG
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
44 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
45 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3
Definition of PCE85176AUG commands . . . . . .4
C bit description . . . . . . . . . . . . . . . . . . . . . . . . .4
Mode-set command bit allocation . . . . . . . . . . .5
Mode-set command bit description . . . . . . . . . .5
Load-data-pointer command bit allocation . . . . .5
Load-data-pointer command bit description . . . .5
Initialize-RAM command bit allocation . . . . . . . .6
Initialize-RAM command bit description . . . . . . .6
Bank-select command bit allocation . . . . . . . . .6
Bank-select command bit description . . . . . . . .6
Blink-select command bit allocation . . . . . . . . . .7
Blink-select command bit description . . . . . . . .7
Blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .8
Standard RAM filling in 1:3 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Entire RAM filling by rewriting in 1:3
multiplex drive mode. . . . . . . . . . . . . . . . . . . . .12
Selection of possible display configurations . . .16
Biasing characteristics . . . . . . . . . . . . . . . . . . .17
I2C slave address byte . . . . . . . . . . . . . . . . . . .28
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .30
Static characteristics . . . . . . . . . . . . . . . . . . . .31
Dynamic characteristics . . . . . . . . . . . . . . . . . .32
Dimensions of PCE85176AUG. . . . . . . . . . . . .36
Bump location for PCE85176AUG . . . . . . . . .36
Alignment marks . . . . . . . . . . . . . . . . . . . . . . . .38
Gold bump hardness . . . . . . . . . . . . . . . . . . . .38
Dimensions of tray for PCE85176AUG . . . . . .39
Selection of LCD segment drivers . . . . . . . . . .40
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .42
Revision history . . . . . . . . . . . . . . . . . . . . . . . .43
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
46 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Block diagram of PCE85176AUG . . . . . . . . . . . . .2
Pinning diagram for PCE85176AUG (bare die) . . .3
Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . .9
Relationship between LCD layout, drive mode,
display RAM filling order, and display data
transmitted over the I2C-bus . . . . . . . . . . . . . . . .10
RAM writing procedure . . . . . . . . . . . . . . . . . . . . 11
RAM banks in static and multiplex
driving mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . .14
Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Example of the Bank-select command with
multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .15
Example of displays suitable for PCE85176AUG 16
Typical system configuration . . . . . . . . . . . . . . . .16
Electro-optical characteristic: relative transmission
curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .19
Static drive mode waveforms . . . . . . . . . . . . . . . .20
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Definition of START and STOP conditions. . . . . .26
System configuration . . . . . . . . . . . . . . . . . . . . . .27
Acknowledgement of the I2C-bus . . . . . . . . . . . .27
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .28
Format of command byte . . . . . . . . . . . . . . . . . . .28
Device protection diagram . . . . . . . . . . . . . . . . . .29
Driver timing waveforms . . . . . . . . . . . . . . . . . . .33
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .33
Track resistances on the SDA and VSS line . . . . .34
Bare die outline of PCE85176AUG . . . . . . . . . . .35
Alignment marks of PCE85176AUG . . . . . . . . . .37
Tray details for PCE85176AUG . . . . . . . . . . . . . .38
Tray alignment for PCE85176AUG tray. . . . . . . .39
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
47 of 48
PCE85176AUG
NXP Semiconductors
4 × 40 LCD segment driver for Chip-On-Glass
26. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.4.1
7.3.4.2
7.3.4.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.3.1
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
7.5.4.4
7.6
7.6.1
7.6.2
8
8.1
8.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Commands of PCE85176AUG . . . . . . . . . . . . . 4
Command: mode-set . . . . . . . . . . . . . . . . . . . . 5
Command: load-data-pointer . . . . . . . . . . . . . . 5
Command: Initialize-RAM . . . . . . . . . . . . . . . . . 6
Command: bank-select. . . . . . . . . . . . . . . . . . . 6
Command: blink-select . . . . . . . . . . . . . . . . . . . 7
Clock and frame frequency. . . . . . . . . . . . . . . . 7
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Writing to RAM . . . . . . . . . . . . . . . . . . . . . . . . 11
Writing to RAM in 1:3 multiplex drive mode . . 12
Writing over the RAM address boundary . . . . 12
Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 13
Output bank selector . . . . . . . . . . . . . . . . . . . 13
Input bank selector . . . . . . . . . . . . . . . . . . . . . 13
RAM bank switching . . . . . . . . . . . . . . . . . . . . 13
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Possible display configurations . . . . . . . . . . . 15
LCD bias generator . . . . . . . . . . . . . . . . . . . . 17
Display register . . . . . . . . . . . . . . . . . . . . . . . . 17
LCD voltage selector . . . . . . . . . . . . . . . . . . . 17
Electro-optical performance . . . . . . . . . . . . . . 18
LCD drive mode waveforms . . . . . . . . . . . . . . 20
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 20
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 21
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 23
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 24
Backplane and segment outputs . . . . . . . . . . 25
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 25
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 25
Characteristics of the I2C-bus . . . . . . . . . . . . 26
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
START and STOP conditions . . . . . . . . . . . . . 26
8.3
8.4
8.5
8.6
8.7
9
10
11
12
13
14
14.1
15
16
17
17.1
18
18.1
19
20
21
22
22.1
22.2
22.3
22.4
23
24
25
26
System configuration . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Track resistance on the I2C-bus lines . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Tray information for PCE85176AUG . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD segment driver selection . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
27
27
28
28
29
29
30
31
32
34
34
35
38
38
38
40
40
42
42
43
44
44
44
44
45
45
46
47
48
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 January 2015
Document identifier: PCE85176AUG
Similar pages