Data Sheet

PCF8579
LCD column driver for dot matrix graphic displays
Rev. 05 — 11 May 2009
Product data sheet
1. General description
The PCF8579 is a low power CMOS1 LCD column driver, designed to drive dot matrix
graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has 40 outputs
and can drive 32 × 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be
cascaded and up to 32 devices may be used on the same I2C-bus (using the two slave
addresses). The device is optimized for use with the PCF8578 LCD row/column driver.
Together these devices form a general purpose LCD dot matrix driver chip set, capable of
driving displays of up to 40960 dots. The PCF8579 is compatible with most
microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). To allow
partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a
diode connected to VDD. Communication overhead is minimized by a display RAM with
auto-incremented addressing and display bank switching.
2. Features
n LCD column driver
n Used in conjunction with the PCF8578, this device forms part of a chip set capable of
driving up to 40960 dots
n 40 column outputs
n Selectable multiplex rates; 1:8, 1:16, 1:24 or 1:32
n Externally selectable bias configuration, 5 or 6 levels
n Easily cascadable for large applications (up to 32 devices)
n 1280-bit RAM for display data storage
n Display memory bank switching
n Auto-incremented data loading across hardware subaddress boundaries (with
PCF8578)
n Power-On Reset (POR) blanks display
n Logic voltage supply range 2.5 V to 6 V
n Maximum LCD supply voltage 9 V
n Low power consumption
n I2C-bus interface
n Compatible with most microcontrollers
n Optimized pinning for single plane wiring in multiple device applications (with
PCF8578)
n Space saving 56-lead small outline package and 64-pin quad flat pack
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
3. Applications
n
n
n
n
n
Automotive information systems
Telecommunication systems
Point-of-sale terminals
Industrial computer terminals
Instrumentation
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
PCF8579T/1
VSO56
plastic very small outline package; 56 leads
SOT190-1
PCF8579H/1
LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm[1]
SOT314-2
PCF8579HT/1
TQFP64
plastic thin quad flat package; 64 leads;
body 10 × 10 × 1.0 mm
SOT357-1
[1]
Version
Should not be used for new designs.
5. Marking
Table 2.
Marking codes
Type number
Marking code
PCF8579T/1
PCF8579T
PCF8579H/1
PCF8579H
PCF8579HT/1
PCF8579HT
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
6. Block diagram
C39 - C0
VDD
V3
COLUMN(1)
DRIVERS
V4
PCF8579
VLCD
OUTPUT
CONTROLLER
TEST
VSS
Y DECODER
AND SENSING
AMPLIFIERS
POWER-ON
RESET
A3
A2
A1
A0
INPUT
FILTERS
SDA
DISPLAY
DECODER
X DECODER
SUBADDRESS
COUNTER
SCL
32 × 40 BIT
DISPLAY RAM
RAM DATA POINTER
Y
I2C-BUS
CONTROLLER
X
SYNC
TIMING
GENERATOR
CLK
COMMAND
DECODER
msa919
n.c.
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
Fig 1.
Block diagram
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
7. Pinning information
7.1 Pinning
SDA
1
56 C0
SCL
2
55 C1
SYNC
3
54 C2
CLK
4
53 C3
VSS
5
52 C4
TEST
6
51 C5
SA0
7
50 C6
A3
8
49 C7
A2
9
48 C8
A1 10
47 C9
A0 11
46 C10
VDD 12
45 C11
n.c. 13
44 C12
V3 14
V4 15
43 C13
PCF8579T
42 C14
VLCD 16
41 C15
C39 17
40 C16
C38 18
39 C17
C37 19
38 C18
C36 20
37 C19
C35 21
36 C20
C34 22
35 C21
C33 23
34 C22
C32 24
33 C23
C31 25
32 C24
C30 26
31 C25
C29 27
30 C26
C28 28
29 C27
001aaj888
Top view. For mechanical details, see Figure 25.
Fig 2.
Pinning diagram of PCF8579T/1 (VSO56)
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
49 C21
50 C20
51 C19
52 C18
53 C17
54 C16
55 C15
56 C14
57 C13
58 C12
59 C11
60 C10
61 C9
62 C8
63 C7
64 C6
LCD column driver for dot matrix graphic displays
C5
1
48 C22
C4
2
47 C23
C3
3
46 C24
C2
4
45 C25
C1
5
44 C26
C0
6
43 C27
SDA
7
42 C28
SCL
8
SYNC
9
41 C29
PCF8579H
40 C30
C37 32
C38 31
C39 30
n.c. 29
n.c. 28
n.c. 27
n.c. 26
n.c. 25
VLCD 24
33 C36
V4 23
34 n.c.
A2 16
V3 22
35 C35
n.c. 15
n.c. 21
36 C34
A3 14
VDD 20
37 C33
SA0 13
n.c. 19
38 C32
TEST 12
A0 18
39 C31
VSS 11
A1 17
CLK 10
001aaj954
Top view. For mechanical details, see Figure 26.
Fig 3.
Pinning diagram of PCF8579H/1 (LQFP64)
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
5 of 41
PCF8579
NXP Semiconductors
49 C21
50 C20
51 C19
52 C18
53 C17
54 C16
55 C15
56 C14
57 C13
58 C12
59 C11
60 C10
61 C9
62 C8
63 C7
64 C6
LCD column driver for dot matrix graphic displays
C5
1
48 C22
C4
2
47 C23
C3
3
46 C24
C2
4
45 C25
C1
5
44 C26
C0
6
43 C27
SDA
7
42 C28
SCL
8
SYNC
9
41 C29
PCF8579HT
40 C30
C37 32
C38 31
C39 30
n.c. 29
n.c. 28
n.c. 27
n.c. 26
n.c. 25
VLCD 24
33 C36
V4 23
34 n.c.
A2 16
V3 22
35 C35
n.c. 15
n.c. 21
36 C34
A3 14
VDD 20
37 C33
SA0 13
n.c. 19
38 C32
TEST 12
A0 18
39 C31
VSS 11
A1 17
CLK 10
001aaj841
Top view. For mechanical details, see Figure 27.
Fig 4.
Pinning diagram of PCF8579HT/1 (TQFP64)
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VSO56
LQFP64,
TQFP64
SDA
1
7
I2C-bus serial data input/output
SCL
2
8
I2C-bus serial clock input
SYNC
3
9
cascade synchronization output
CLK
4
10
external clock input/output
VSS
5
11
ground
TEST[1]
6
12
test pin
SA0
7
13
I2C-bus slave address input (bit 0)
A3 to A0
8 to 11
14, 16 to 18
I2C-bus subaddress inputs
supply voltage
VDD
12
20
n.c.[2]
13
15, 19, 21, 25 not connected
to 29, 34
V3, V4
14, 15
22, 23
LCD bias voltage inputs
VLCD
16
24
LCD supply voltage
C39 to C0
17 to 56
30 to 33, 35
to 64, 1 to 6
LCD column driver outputs
[1]
The TEST pin must be connected to VSS.
[2]
Do not connect, these pins are reserved.
8. Functional description
The PCF8579 column driver is designed for use with the PCF8578. Together they form a
general purpose LCD dot matrix chip set.
Typically up to 16 PCF8579s may be used with one PCF8578 (examples of cascading the
devices see Table 16, Figure 21, Figure 22, Figure 23 and Figure 24). Each of the
PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave
addresses. The two slave addresses are set by the logic level on input SA0.
8.1 Power-on reset
At power-on the PCF8579 resets to a defined starting condition as follows:
1. Display blank (in conjunction with PCF8578)
2. 1:32 multiplex rate
3. Start bank 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
7 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
Remark: Do not transfer data on the I2C-bus for at least 1 ms after power-on to allow the
reset action to complete.
8.2 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast depend on the multiplex rate and
the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the
LCD exhibits 10 % contrast. Table 4 shows the optimum voltage bias levels and Table 5
the discrimination ratios (D) for the different multiplex rates as functions of Voper.
(1)
V oper = V DD – V LCD
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
V on ( RMS ) =
V oper
1
n–1
--- + -----------------------n n( n + 1)
(2)
and the RMS off-state voltage (Voff(RMS)) with the equation
V off ( RMS ) =
V oper
2( n – 1)
------------------------------2n( n + 1)
(3)
where the values for n are determined by the multiplex rate (1:n). Valid values for n are:
n = 8 for 1:8 multiplex
n = 16 for 1:16 multiplex
n = 24 for 1:24 multiplex
n = 32 for 1:32 multiplex
Table 4.
Optimum LCD voltages
Bias ratios
Multiplex rate
1:8
1:16
1:24
1:32
V2
-------------V oper
0.739
0.800
0.830
0.850
V3
-------------V oper
0.522
0.600
0.661
0.700
V4
-------------V oper
0.478
0.400
0.339
0.300
V5
-------------V oper
0.261
0.200
0.170
0.150
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
Table 5.
Discrimination ratios
Discrimination
ratios
Multiplex rate
1:8
1:16
1:24
1:32
V off ( RMS )
------------------------V oper
0.297
0.245
0.214
0.193
V on ( RMS )
----------------------V oper
0.430
0.316
0.263
0.230
V on ( RMS )
D = ------------------------V off ( RMS )
1.447
1.291
1.230
1.196
V oper
-------------V th
3.370
4.080
4.680
5.190
Figure 5 shows the values of Table 4 as graphs.
msa838
1.0
Vbias
Voper
V2/Voper
0.8
V3/Voper
0.6
V4/Voper
0.4
V5/Voper
0.2
0
1:8
1:16
1:24
1:32
multiplex rate
Vbias = V2, V3, V4, V5; see Table 4.
Fig 5.
Vbias/Voper as a function of the multiplex rate
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
9 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.3 LCD drive mode waveforms
Tfr
ROW 0
COLUMN
0
VDD
V2
V3
V4
V5
VLCD
1
2
ON
3
4
5
6
OFF
7
1:8
VDD
V2
V3
V4
V5
VLCD
SYNC
ROW 0
COLUMN
VDD
V2
V3
V4
V5
VLCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1:16
VDD
V2
V3
V4
V5
VLCD
SYNC
VDD
V2
ROW 0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
V3
V4
V5
VLCD
1:24
VDD
V2
COLUMN
V3
V4
V5
VLCD
SYNC
VDD
V2
ROW 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
V3
V4
V5
VLCD
1:32
VDD
V2
COLUMN
V3
V4
V5
VLCD
SYNC
msa841
Fig 6.
column
display
LCD row and column waveforms
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
10 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
Tfr
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
VLCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
VLCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
VLCD
COL 2
C2 (t)
VDD
V2
V3
V4
V5
VLCD
state 1 (OFF)
state 2 (ON)
dot matrix
1:8 multiplex rate
Voper
0.261 Voper
Vstate 1(t)
0V
0.261 Voper
Voper
Voper
0.478 Voper
0.261 Voper
Vstate 2(t)
0V
0.261 Voper
0.478 Voper
Voper
msa840
Vstate1(t) = C1(t) − R1(t).
V on ( RMS )
----------------------- =
V oper
1
8–1
--- + ------------------------ = 0.430
8 8( 8 + 1)
Vstate2(t) = C2(t) − R2(t).
V off ( RMS )
------------------------ =
V oper
Fig 7.
2( 8 – 1)
------------------------------2- = 0.297
8( 8 + 1)
LCD drive mode waveforms for 1:8 multiplex rate
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
11 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
state 1 (OFF)
state 2 (ON)
Tfr
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
VLCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
VLCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
VLCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
VDD
V2
V3
V4
V5
VLCD
Voper
Vstate 1(t)
0.2 Voper
0V
0.2 Voper
Voper
Voper
0.6 Voper
Vstate 2(t)
0.2 Voper
0V
0.2 Voper
0.6 Voper
Voper
msa836
Vstate1(t) = C1(t) − R1(t).
V on ( RMS )
----------------------- =
V oper
1
16 – 1
------ + ------------------------------ = 0.316
16 16 ( 16 + 1 )
Vstate2(t) = C2(t) − R2(t).
V off ( RMS )
------------------------ =
V oper
Fig 8.
2 ( 16 – 1 )
------------------------------------2- = 0.254
16 ( 16 + 1 )
LCD drive mode waveform for 1:16 multiplex rate
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
12 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.4 Timing generator
The timing generator of the PCF8579 organizes the internal data flow from the RAM to the
display drivers. An external synchronization pulse SYNC is received from the PCF8578.
This signal maintains the correct timing relationship between cascaded devices.
8.5 Column drivers
Outputs C0 to C39 are column drivers which must be connected to the LCD. Unused
outputs should be left open-circuit.
8.6 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.6.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this
moment will be interpreted as control signals.
8.6.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP
condition (P).
8.6.3 System configuration
A device transmitting a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message flow is the master and the devices which
are controlled by the master are the slaves.
8.6.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal the end of a data transmission to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
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PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
SDA
SCL
data line
stable;
data valid
Fig 9.
change
of data
allowed
mba607
Bit transfer
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 10. Definition of START and STOP condition
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mba605
Fig 11. System configuration
clock pulse for
acknowledgement
START
condition
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
mba606
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig 12. Acknowledgement on the I2C-bus
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
14 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.6.5 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display
data bytes. It performs the conversion of the data input (serial-to-parallel) and the data
output (parallel-to-serial). The PCF8579 acts as an I2C-bus slave transmitter/receiver.
Device selection depends on the I2C-bus slave address, the hardware subaddress and
the commands transmitted.
8.6.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6.7 I2C-bus protocol
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578
and PCF8579. The least significant bit of the slave address is set by connecting input SA0
to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can
be distinguished on the same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large
applications (see Table 16).
2. The use of two types of LCD multiplex schemes on the same I2C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The I2C-bus protocol is shown in Figure 13. All communications are initiated with a START
condition (S) from the I2C-bus master, which is followed by the desired slave address and
read/write bit. All devices with this slave address acknowledge in parallel. All other devices
ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands
follow the slave address acknowledgement. The commands are also acknowledged by all
addressed devices on the bus. The last command must clear the continuation bit C.
After the last command a series of data bytes may follow. The acknowledgement after
each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with
its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus
master issues a STOP condition (P).
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from
the RAM following the slave address acknowledgement. After this acknowledgement the
master transmitter becomes a master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the reception of each byte in turn. The
master receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices.
PCF8579_5
Product data sheet
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Rev. 05 — 11 May 2009
15 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)
are connected to VSS or VDD to represent the desired hardware subaddress code. If two or
more devices share the same slave address, then each device must be allocated a
unique hardware subaddress.
acknowledge
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
acknowledge by
all addressed
PCF8578s / PCF8579s
R/ W
slave address
S
0 1 1 1 1 0 A 0 A C
0
S
A
COMMAND
DISPLAY DATA
n ≥ 0 byte(s)
1 byte
A
P
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
(a)
msa830
a. Master transmits to slave receiver (write mode)
acknowledge by
all addressed
PCF8578s / PCF8579s
slave address
S
acknowledge
from master
slave address
S
0 1 1 1 1 0 A 0 A C
0
R/ W
COMMAND
A S
n ≥ 1 byte
S
0 1 1 1 1 0 A 1 A
0
DATA
no acknowledge
from master
A
DATA
n bytes
R/W
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
1
P
last byte
update data pointers
and if necessary
subaddress counter
msa832
(b)
b. Master reads after sending command string (write commands; read data)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
S
S
0 1 1 1 1 0 A 1 A
0
R/ W
DATA
A
n bytes
(c)
DATA
1
P
last byte
update data pointers
and if necessary,
subaddress counter
msa831
c. Master reads slave immediately after sending slave address (read mode)
Fig 13. I2C-bus protocol
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
16 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.7 Display RAM
The PCF8579 contains a 32 × 40-bit static RAM which stores the display data. The RAM
is divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to or from the RAM via the I2C-bus.
8.7.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows an individual data byte or a series of data bytes to be written into, or read from, the
display RAM, controlled by commands sent on the I2C-bus.
8.7.2 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress
counter. Storage and retrieval take place only when the contents of the subaddress
counter matches with the hardware subaddress at pins A0, A1, A2 and A3.
8.8 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus.
The five commands available to the PCF8579 are defined in Table 6.
Table 6.
Definition of PCF8579 commands
Command
Operation code
Reference
Bit
7
6
5
4
3
set-mode
C
1
0
T
E[1:0]
set-start-bank
C
1
1
1
1
device-select
C
1
1
0
A[3:0]
RAM-access
C
1
1
1
G[1:0]
load-X-address
C
0
X[5:0]
2
1
1
0
M[1:0]
Table 8
B[1:0]
Table 9
Table 10
Y[1:0]
Table 11
Table 12
The most-significant bit of a command is the continuation bit C (see Table 7 and
Figure 14). Commands are transferred in WRITE mode only.
Table 7.
C bit description
Bit
Symbol
7
C
Value
Description
continue bit
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command too
MSB
C
LSB
REST OF OPCODE
msa833
C = 0; last command.
C = 1; commands continue.
Fig 14. General information of command byte
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
17 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
Table 8.
Set-mode - command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 7
6, 5
-
10
fixed value
4
T
3, 2
display mode
0
PCF8578 row only
1
PCF8578 mixed mode
E[1:0]
display status
00
blank
01
normal
10
all segments on
11
1, 0
inverse video
M[1:0]
Table 9.
Bit
LCD drive mode
01
1:8 MUX (8 rows)
10
1:16 MUX (16 rows)
11
1:24 MUX (24 rows)
00
1:32 MUX (32 rows)
Set-start-bank - command bit description
Symbol
Value
Description
7
C
0, 1
see Table 7
6 to 2
-
11111
fixed value
1, 0
B[1:0]
[1]
start bank pointer (see Figure 18)[1]
00
bank 0
01
bank 1
10
bank 2
11
bank 3
Useful for scrolling, pseudo-motion and background preparation of new display content.
Table 10.
Device-select - command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 7
6 to 4
-
110
3 to 0
A[3:0]
0 to
fixed value
15[1]
hardware subaddress;
4 bit binary value; transferred to the subaddress
counter to define one of sixteen hardware
subaddresses
[1]
Values shown in decimal.
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
18 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
Table 11.
RAM-access - command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 7
6 to 4
-
111
3, 2
G[1:0]
fixed value
RAM access mode;
defines the auto-increment behavior of the
address for RAM access (see Figure 17)
1, 0
Y[1:0]
00
character
01
half-graphic
10
full-graphic
11
not allowed[1]
0 to 3[2]
RAM row address;
two bits of immediate data, transferred to the
Y-address pointer to define one of four display
RAM rows (see Figure 15)
[1]
See operation code for set-start-bank in Table 9.
[2]
Values shown in decimal.
Table 12.
Load-X-address - command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 7
6
-
0
5 to 0
X[5:0]
0 to
fixed value
39[1]
RAM column address;
six bits of immediate data, transferred to the
X-address pointer to define one of forty display
RAM columns (see Figure 15)
[1]
Values shown in decimal.
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
19 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.9 RAM access
1 byte
0
LSB
Y address
Y max
MSB
0
X address
X max
001aaj920
Fig 15. RAM addressing scheme
There are three RAM-access modes:
• Character
• Half-graphic
• Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. The
RAM-access command controls the order in which data is written to or read from the RAM
(see Figure 17).
To store RAM data, the user specifies the location into which the first byte will be loaded
(see Figure 16):
• Device subaddress (specified by the device-select command)
• RAM X-address (specified by the bits X[5:0] of the load-X-address command)
• RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes will be written or read according to the chosen RAM-access mode.
Device subaddresses are automatically incremented between devices until the last device
is reached. If the last device has subaddress 15, further display data transfers will lead to
a wrap-around of the subaddress to 0.
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
20 of 41
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NXP Semiconductors
PCF8579_5
Product data sheet
DEVICE SELECT:
subaddress 12
RAM ACCESS:
bank 0
character mode
bank 1
bank 1
bank 2
RAM
bank 3
Rev. 05 — 11 May 2009
LOAD X-ADDRESS: X-address = 8
R/ W
slave address
READ
DATA
A
R /W
slave address
S
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
S
0 1 1 1 1 0 A 0 A 1 1 1 0 1 1 0 0 A 1 0 0 0 1 0 0 0 A 0 1 1 1 0 0 0 1 A
0
last command
WRITE
DATA
A
DATA
A
msa835
PCF8579
21 of 41
© NXP B.V. 2009. All rights reserved.
Fig 16. Example of commands specifying initial data byte RAM locations
LCD column driver for dot matrix graphic displays
S
S 0 1 1 1 1 0 A 1 A
0
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PCF8579
driver 1
driver 2
NXP Semiconductors
PCF8579_5
Product data sheet
PCF8578/PCF8579
driver k
bank 0
bank 1
RAM
4 bytes
bank 2
bank 3
PCF8578/PCF8579 system RAM
1 ≤ k ≤ 16
40-bits
Rev. 05 — 11 May 2009
1 byte
0
1
2
3
4
5
6
7
8
LSB
9 10 11
character mode
MSB
2
4
6
8 10 12 14 16 18 20 22
1
3
5
7
9 11 13 15 17 19 21 23
half-graphic mode
4
8 12 16 20 24 28 32 36 40 44
1
5
9 13 17 21 25 29 33 37 41 45
2
6 10 14 18 22 26 30 34 38 42 46
3
7 11 15 19 23 27 31 35 39 43 47
4 bytes
22 of 41
© NXP B.V. 2009. All rights reserved.
RAM data bytes are
written or read as
indicated above
Fig 17. RAM access mode
full-graphic mode
msa849
PCF8579
0
LCD column driver for dot matrix graphic displays
0
2 bytes
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
8.9.1 Display control
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD
via the column outputs. The number of rows scanned depends on the multiplex rate set by
bits M[1:0] of the set-mode command.
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
msa851
1:32 multiplex rate and start bank = 2.
Fig 18. Relationship between display and set-start-bank
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
23 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0]
of the set-mode command. For bank switching, the RAM bank corresponding to the top of
the display is set by the bits B[1:0] of the set-start-bank command. This is shown in
Figure 18. This feature is useful when scrolling in alphanumeric applications.
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
−0.5
+8.0
V
VLCD
LCD supply voltage
VDD − 11
+8.0
V
VI
input voltage
−0.5
+8.0
V
VDD − 11
+8.0
V
−0.5
+8.0
V
VDD − 11
+8.0
V
VDD related;
on pins SDA, SCL,
CLK, TEST, SA0
and OSC
VLCD related;
V3 and V4
VO
output voltage
VDD related;
SYNC and CLK
VLCD related;
R0 to R7, R8/C8 to
R31/C31 and C32
to C39
II
input current
−10
+10
mA
IO
output current
−10
+10
mA
IDD
supply current
−50
+50
mA
IDD(LCD)
LCD supply current
−50
+50
mA
ISS
ground supply current
−50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
-
100
mW
−65
+150
°C
Tstg
[1]
per package
storage temperature
According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
PCF8579_5
Product data sheet
[1]
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
24 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
10. Static characteristics
Table 14. Static characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
2.5
-
6.0
V
VLCD
LCD supply voltage
VDD − 9
-
VDD − 3.5
V
IDD
supply current
[1]
-
9
20
µA
[2]
-
1.3
1.8
V
VPOR
fclk = 2 kHz
power-on reset voltage
Logic
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
VDD
V
IL
leakage current
at pins SDA, SCL,
SYNC, CLK, TEST
and SA0, A0 to A3;
Vi = VDD or VSS
−1
-
+1
mA
IOL
LOW-level output current
at pin SDA;
VOL = 0.4 V;
VDD = 5 V
3
-
-
mA
Ci
input capacitance
at pin SCL and SDA
-
-
5
pF
−2
-
+2
µA
-
±20
-
mV
-
3
6
kΩ
[3]
LCD outputs
IL
leakage current
at pins V3 and V4;
Vi = VDD or VLCD
Voffset(DC)
DC offset voltage
on pins C0 to C39
output resistance
RO
on pins at C0 to C39
[4]
[1]
Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor.
[2]
Resets all logic when VDD < VPOR.
[3]
Periodically sampled; not 100 % tested.
[4]
Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and VLCD) when the specified current flows
through one output under the following conditions (see Table 4):
a) Voper = VDD − VLCD = 9 V.
b) V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; Iload = 100 µA.
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
25 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
11. Dynamic characteristics
Table 15. Dynamic characteristics
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 V to 6 V; VSS = 0 V;
VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
fclk
clock frequency
50 % duty factor
tPD(drv)
driver propagation delay
VDD − VLCD = 9 V;
with test load of 45 pF
Min
[1]
Typ
Max
Unit
-
-
10
kHz
-
-
100
µs
I2C-bus
fSCL
SCL clock frequency
-
-
100
kHz
tw(spike)
spike pulse width
-
-
100
ns
tBUF
bus free time between a STOP
and START condition
4.7
-
-
µs
tSU;STA
set-up time for a repeated START
condition
4.7
-
-
µs
tHD;STA
hold time (repeated) START
condition
4.0
-
-
µs
tLOW
LOW period of the SCL clock
4.7
-
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
-
µs
tr
rise time of both SDA and SCL
signals
-
-
1
µs
tf
fall time of both SDA and SCL
signals
-
-
0.3
µs
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
4.0
-
-
µs
[1]
Typically 0.9 kHz to 3.3 kHz.
0.7 V
0. V
0. V
V
0
−V
V
0. V
013aaa031
Fig 19. Driver timing waveforms
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
26 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 20. I2C-bus timing waveforms
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
27 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
12. Application information
Large display configurations of one PCF8578 and up to 32 PCF8579 can be recognized
on the same I2C-bus by using the 4-bit hardware subaddress A[3:0] and the I2C-bus slave
address SA0.
Table 16. Example of addressing one PCF8578 and 32 PCF8579
Pins connected to VSS are logic 0; pins connected to VDD are logic 1.
Cluster
SA0
A3
A2
A1
A0
Device
0
-
-
-
-
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
0
0
0
0
16
0
0
0
1
17
0
0
1
0
18
0
0
1
1
19
0
1
0
0
20
0
1
0
1
21
0
1
1
0
22
0
1
1
1
23
1
0
0
0
24
1
0
0
1
25
1
0
1
0
26
1
0
1
1
27
1
1
0
0
28
1
1
0
1
29
1
1
1
0
30
1
1
1
1
31
PCF8578
PCF8579
1
2
1
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
28 of 41
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NXP Semiconductors
PCF8579_5
Product data sheet
VDD
VDD
C
V2
C
R
C
(4 2 3)R
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
32
R
LCD DISPLAY
rows
V3
8
V4
C
PCF8578
(ROW MODE)
R
40
columns
unused columns
40
columns
subaddress 0
40
columns
subaddress 1
subaddress k−1
C
VSS
SA0
R
VLCD
VLCD
VSS
VDD
VDD
VLCD
OSC
V3
Rext(OSC)
VSS SDA SCL CLK SYNC
VSS
A0
#1
PCF8579
VDD
VDD
A1
VLCD
A2
V3
A0
VDD
VDD
#2
A1
VLCD
PCF8579
A2
V3
A0
#k
A1
PCF8579
A2
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
VSS
VSS
VSS
VDD
SCL
SDA
PCF8579
29 of 41
© NXP B.V. 2009. All rights reserved.
Fig 21. Typical LCD driver system with 1:32 multiplex rate
msa845
LCD column driver for dot matrix graphic displays
Rev. 05 — 11 May 2009
V5
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VSS
A2
#k
PCF8579
A1
C
R
C
R
SA0 SDA SCL CLK SYNC VSS
A3
V3
V4
A2
VLCD
A1
VDD
40
columns
subaddress 1
VDD
#1
PCF8579
V4
VLCD
VDD
A0
VDD
40
columns
subaddress 0
1:16 multiplex rate
16 × 40 × k dots (k ≤ 16)
(10240 dots max.)
16
1:16 multiplex rate
16 × 40 × k dots (k ≤ 16)
(10240 dots max.)
PCF8578
8
(ROW MODE)
unused columns
V4
#2
PCF8579
A0
rows
V3
R
VDD
LCD DISPLAY
rows
V2
C
A1
VSS
40
columns
40
columns
subaddress 0
40
columns
subaddress 1
subaddress k 1
V5
C
SA0
R
VLCD
VLCD
VDD
VSS/VDD
VDD
V3
VSS
OSC
VSS SDA SCL CLK SYNC
A0
VLCD
#1
PCF8579
V4
Rext(OSC)
VSS
VSS
VSS
SYNC CLK
VDD
VDD
A0
A1
VLCD
A2
V3
A3
V4
SCL SDA SA0
VSS
VSS
VSS
#2
PCF8579
VDD
VDD
A0
A1
VLCD
A2
V3
A3
V4
#k
PCF8579
A1
A2
A3
SYNC CLK SCL SDA SA0
VSS
SYNC CLK SCL SDA SA0
VSS
VSS
VSS
VDD
SCL
SDA
msa847
PCF8579
30 of 41
© NXP B.V. 2009. All rights reserved.
Fig 22. Split screen application with 1:16 multiplex rate for improved contrast
LCD column driver for dot matrix graphic displays
Rev. 05 — 11 May 2009
R
A2
16
VDD
C
V4
VLCD
40
columns
subaddress k 1
VDD
VDD
SA0 SDA SCL CLK SYNC VSS
V3
A3
VDD
A0
VSS
VDD
SA0 SDA SCL CLK SYNC VSS
V3
A3
NXP Semiconductors
PCF8579_5
Product data sheet
VDD
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VSS
SA0 SDA SCL CLK SYNC VSS
SA0 SDA SCL CLK SYNC VSS
A3
V3
A3
V4
A2
V4
A2
VLCD
A1
VLCD
A1
#k
PCF8579
VDD
PCF8579
VDD
A0
40
columns
subaddress 1
VDD
V3
#1
PCF8579
V4
VLCD
VDD
A0
VDD
40
columns
subaddress 0
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
LCD DISPLAY
32
V2
32
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
(4 2 3)R
rows
V3
C
PCF8578
8
(ROW MODE)
unused columns
V4
R
#2
40
columns
40
columns
subaddress 0
40
columns
subaddress 1
subaddress k 1
V5
C
SA0
R
VLCD
VDD
VSS/VDD
VDD
V3
VLCD
VSS
VSS
OSC
SDA SCL CLK SYNC
A0
VLCD
#1
PCF8579
V4
Rext(OSC)
VSS
VSS SYNC CLK
VSS
VDD
VDD
A1
VLCD
A2
V3
A3
V4
SCL SDA SA0
VSS
A0
#2
PCF8579
VDD
VDD
A1
VLCD
A2
V3
A3
V4
A0
#k
PCF8579
A1
A2
VSS SYNC CLK SCL
SDA SA0
A3
VSS SYNC CLK SCL
SDA SA0
VSS
VSS
VSS
VSS
VDD
SCL
SDA
msa846
PCF8579
31 of 41
© NXP B.V. 2009. All rights reserved.
Fig 23. Split screen application with 1:32 multiplex rate
LCD column driver for dot matrix graphic displays
Rev. 05 — 11 May 2009
VDD
C
VDD
40
columns
subaddress k 1
VDD
R
VSS
V3
A0
C
VDD
A3
A1
R
VSS
SA0 SDA SCL CLK SYNC VSS
A2
C
VDD
NXP Semiconductors
PCF8579_5
Product data sheet
VDD
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF8579_5
Product data sheet
VSS
SCL VDD
VLCD
SDA
R0
R
Rext(OSC)
(4 2 3)R
R R
R
n.c.
n.c.
LCD DISPLAY
PCF8578
Rev. 05 — 11 May 2009
R31/C31
C0
C27
C28
C39
C0
C28
C39
PCF8579
c.
n.
c.
n.
to other
PCF8579s
msa852
PCF8579
32 of 41
© NXP B.V. 2009. All rights reserved.
Fig 24. Example of single plane wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode)
LCD column driver for dot matrix graphic displays
PCF8579
C27
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
13. Package outline
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
HE
v M A
Z
56
29
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
detail X
28
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
3.3
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
2.25
1.6
1.4
1.45
1.30
0.2
0.1
0.1
0.90
0.55
inches
0.13
0.012
0.004
0.12
0.11
0.01
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.62
0.0295
0.43
0.60
0.089
0.063
0.055
0.057
0.035
0.008 0.004 0.004
0.051
0.022
θ
7o
o
0
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
97-08-11
03-02-19
SOT190-1
Fig 25. Package outline of PCF8579T/1 (VSO56)
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
33 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 26. Package outline PCF8579H/1 (LQFP64)
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
34 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
(A 3)
A2 A
1
wM
pin 1 index
θ
bp
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.2
0.15
0.05
1.05
0.95
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.1
Z D(1) Z E(1)
1.45
1.05
1.45
1.05
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT357-1
137E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
02-03-14
Fig 27. Package outline PCF8579HT/1 (TQFP64)
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
35 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
36 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and 18
Table 17.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 18.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
37 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 19.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DC
Direct Current
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
POR
Power-On Reset
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial Clock Line
SDA
Serial Data Line
SMD
Surface Mount Device
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
38 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
16. Revision history
Table 20.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8579_5
20090511
Product data sheet
-
PCF8579_4
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Added package type TQFP64
Removed bare die types
Rearranged information in data sheet
Changed letter symbols to NXP approved symbols
Added RAM addressing scheme (Figure 15)
Added addressing example (Table 16)
PCF8579_4
20030901
Product data sheet
-
PCF8579_3
PCF8579_3
19970401
Product data sheet
-
PCF8579_2
PCF8579_2
19961025
Product data sheet
-
PCF8579_1
PCF8579_1
19940125
Product data sheet
-
-
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
39 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8579_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 11 May 2009
40 of 41
PCF8579
NXP Semiconductors
LCD column driver for dot matrix graphic displays
19. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.7
8.7.1
8.7.2
8.8
8.9
8.9.1
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multiplexed LCD bias generation . . . . . . . . . . . 8
LCD drive mode waveforms . . . . . . . . . . . . . . 10
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 13
Column drivers . . . . . . . . . . . . . . . . . . . . . . . . 13
Characteristics of the I2C-bus . . . . . . . . . . . . . 13
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
START and STOP conditions . . . . . . . . . . . . . 13
System configuration . . . . . . . . . . . . . . . . . . . 13
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 15
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 15
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Subaddress counter . . . . . . . . . . . . . . . . . . . . 17
Command decoder . . . . . . . . . . . . . . . . . . . . . 17
RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Display control . . . . . . . . . . . . . . . . . . . . . . . . 23
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24
Static characteristics. . . . . . . . . . . . . . . . . . . . 25
Dynamic characteristics . . . . . . . . . . . . . . . . . 26
Application information. . . . . . . . . . . . . . . . . . 28
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33
Soldering of SMD packages . . . . . . . . . . . . . . 36
Introduction to soldering . . . . . . . . . . . . . . . . . 36
Wave and reflow soldering . . . . . . . . . . . . . . . 36
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 36
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 37
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39
Legal information. . . . . . . . . . . . . . . . . . . . . . . 40
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17.4
18
19
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 May 2009
Document identifier: PCF8579_5
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