Data Sheet

PCF8577C
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
Product data sheet
1. General description
The PCF8577C is an LCD driver which drives up to 32 segments directly, or 64 segments
in a duplex configuration.
The two-line I2C-bus interface substantially reduces wiring overheads in remote display
applications. I2C-bus traffic is minimized in multiple IC applications by automatic address
incrementing, hardware subaddressing and display memory switching (direct drive
mode).To allow partial VDD shutdown, the ESD protection system of the SCL and SDA
pins does not use a diode connected to VDD.
For a selection of NXP LCD segment drivers, see Table 13 on page 25.
2. Features and benefits












Direct/duplex drive modes with up to 32/64 LCD-segment drive capability per device
Operating supply voltage: 2.5 V to 6 V
Low power consumption
I2C-bus interface
Optimized pinning for single plane wiring
Single-pin built-in oscillator
Auto-incremented loading across device subaddress boundaries
Display memory switching in direct drive mode
May be used as I2C-bus output expander
System expansion up to 256 segments
Power-on reset blanks display
I2C-bus address: 0111 0100.
3. Ordering information
Table 1.
Ordering information
Type number
PCF8577CT
Package
Name
Description
Version
VSO40
plastic very small outline package; 40
leads
SOT158-1
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
3.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF8577CT/3
PCF8577CT/3,112
935278866112
tube
3
PCF8577CT/3
PCF8577CT/3,118
935278866118
tape and reel, 13 inch
3
4. Marking
Table 3.
Marking codes
Type number
Marking code
PCF8577CT/3
PCF8577CT
5. Block diagram
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Block diagram of PCF8577C
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
6. Pinning information
6.1 Pinning
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PCF8577C
Product data sheet
Pin configuration for PCF8577CT
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
6.2 Pin description
Table 4.
Pin description
Symbol
Pin
Type
Description
S32 to S1
1 to 32
outputs
segment outputs
BP1
33
input/output
cascaded sync input/backplane output
A2/BP2
34
input/output
hardware address line and cascade sync
input/backplane output
VDD
35
supply
supply voltage
A1
36
input
hardware address line input
A0/OSC
37
input
hardware address line and oscillator pin input
VSS
38
supply
ground supply
SCL
39
input
I2C-bus clock line input
SDA
40
input/output
I2C-bus data line input/output
7. Functional description
7.1 Hardware subaddress lines A0, A1, and A2
The hardware subaddress lines A0, A1, and A2 are used to program the device
subaddress for each PCF8577C connected to the I2C-bus. Lines A0 and A2 are shared
with OSC and BP2 respectively to reduce pinout requirements.
1. Line A0 is defined as LOW (logic 0) when this pin is used for the local oscillator or
when connected to VSS. Line A0 is defined as HIGH (logic 1) when connected to VDD.
2. Line A1 must be defined as LOW (logic 0) or as HIGH (logic 1) by connection to VSS
or VDD respectively.
3. In the direct drive mode, the second backplane signal BP2 is not used and the
A2/BP2 pin is exclusively the A2 input. Line A2 is defined as LOW (logic 0) when
connected to VSS or, if this is not possible, by leaving it unconnected (internal
pull-down). Line A2 is defined as HIGH (logic 1) when connected to VDD.
4. In the duplex drive mode, the second backplane signal BP2 is required and the
A2 signal is undefined. In this mode, device selection is made exclusively from
lines A0 and A1.
7.2 Oscillator A0/OSC
The PCF8577C has a single-pin built-in oscillator which provides the modulation for the
LCD segment driver outputs. One external resistor and one external capacitor are
connected to the A0/OSC pin to form the oscillator (see Figure 13 and Figure 14). For
correct start-up of the oscillator after power-on, the resistor and capacitor must be
connected to the same VSS/VDD as the chip. In an expanded system containing more than
one PCF8577C the backplane signals are usually common to all devices and only one
oscillator is required. The devices which are not used for the oscillator are put into the
cascade mode by connecting the A0/OSC pin to either VDD or VSS depending on the
required state for A0. In the cascade mode, each PCF8577C is synchronized from the
backplane signals.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
7.3 User-accessible registers
There are nine user-accessible 1-byte registers. The first is a control register which is
used to control the loading of data into the segment byte registers and to select display
options. The other eight are segment byte registers, split into two banks of storage, which
store the segment data. The set of even-numbered segment byte registers is called
BANK A. Odd-numbered segment byte registers are called BANK B.
There is one slave address for the PCF8577C (see Table 7). All addressed devices load
the second byte into the control register and each device maintains an identical copy of
the control byte in the control register always (see I2C-bus protocol, Figure 10), i.e. all
addressed devices respond to control commands sent on the I2C-bus.
The control register is shown in more detail in Figure 3. The least-significant bits select
which device and which segment byte register is loaded next. This part of the register is
therefore called the Segment Byte Vector (SBV).
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Fig 3.
PCF8577C register organization
The upper three bits of the SBV (V5 to V3) are compared with the hardware subaddress
input signals A2, A1 and A0. If they are the same, then the device is enabled for loading, if
not the device ignores incoming data but remains active.
The three least-significant bits of the SBV (V2 to V0) address one of the segment byte
registers within the enabled chip for loading segment data.
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
The control register also has two display control bits. These bits are named MODE and
BANK. The MODE bit selects whether the display outputs are configured for direct or
duplex drive displays. The BANK bit allows the user to display BANK A or BANK B.
7.4 Auto-incremented loading
After each segment byte is loaded, the SBV is incremented automatically. Thus
auto-incremented loading occurs if more than one segment byte is received in a data
transfer.
Since the SBV addresses both device and segment registers in all addressed chips,
auto-incremented loading may proceed across device boundaries if the hardware
subaddresses are arranged contiguously.
7.5 Direct drive mode
The PCF8577C is set to the direct drive mode by loading the MODE control bit with
logic 0. In this mode, only four bytes are required to store the data for the 32 segment
drivers. Setting the BANK bit to logic 0 selects even bytes (BANK A), setting the BANK bit
to logic 1 selects odd bytes (BANK B).
In the direct drive mode, the SBV is auto-incremented by two after the loading of each
segment byte register. This means, that auto-incremented loading of BANK A or BANK B
is possible. Either bank may be completely or partially loaded irrespective of which bank is
being displayed. Direct drive output waveforms are shown in Figure 4.
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Fig 4.
Direct drive mode display output waveforms
7.6 Duplex mode
The PCF8577C is set to the duplex mode by loading the MODE bit with logic 1. In this
mode, a second backplane signal (BP2) is needed and pin A2/BP2 is used for this;
therefore A2 and its equivalent SBV bit V5 are undefined. The SBV auto-increments by
one between loaded bytes.
All of the segment bytes are required to store data for the 32 segment drivers and the
BANK bit is ignored.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
Duplex mode output waveforms are shown in Figure 5.
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Von(RMS) = 0.791(VDD  VSS); Voff(RMS) = 0.354(VDD  VSS).
Fig 5.
Duplex mode display output waveforms
7.7 Display memory mapping
The mapping between the eight segment registers and the segment outputs S1 to S32 is
given in Table 5 and Table 6.
Since only one register bit per segment is needed in the direct drive mode, the BANK bit
allows swapping of display information. If BANK is set to logic 0, even bytes (BANK A) are
displayed; if BANK is set to logic 1 odd bytes (BANK B) are displayed. BP1 is always used
for the backplane output in the direct drive mode. In duplex mode, even bytes (BANK A)
correspond to backplane 1 (BP1) and odd bytes (BANK B) correspond to backplane 2
(BP2).
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
Table 5.
Segment byte-segment driver mapping in direct drive mode
Mode
Bank
V2
V1 V0 Segment/
Bit/
Register
7
MSB
6
5
4
3
2
1
0
LSB
Backplane
0
0
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
S1
BP1
0
1
0
0
1
1
S8
S7
S6
S5
S4
S3
S2
S1
BP1
0
0
0
1
0
2
S16
S15
S14
S13
S12
S11
S10
S9
BP1
0
1
0
1
1
3
S16
S15
S14
S13
S12
S11
S10
S9
BP1
0
0
1
0
0
4
S24
S23
S22
S21
S20
S19
S18
S17
BP1
0
1
1
0
1
5
S24
S23
S22
S21
S20
S19
S18
S17
BP1
0
0
1
1
0
6
S32
S31
S30
S29
S28
S27
S26
S25
BP1
0
1
1
1
1
7
S32
S31
S30
S29
S28
S27
S26
S25
BP1
Mapping example: bit 0 of register 7 controls the LCD segment S25 if BANK bit is a
logic 1.
Table 6.
Segment byte-segment driver mapping in duplex mode
Mode
Bank
V2
V1 V0 Segment/
Bit/
Register
7
MSB
6
5
4
3
2
1
0
LSB
Backplane
1
X[1]
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
S1
BP1
1
X[1]
0
0
1
1
S8
S7
S6
S5
S4
S3
S2
S1
BP2
1
X[1]
0
1
0
2
S16
S15
S14
S13
S12
S11
S10
S9
BP1
1
X[1]
0
1
1
3
S16
S15
S14
S13
S12
S11
S10
S9
BP2
1
X[1]
1
0
0
4
S24
S23
S22
S21
S20
S19
S18
S17
BP1
1
X[1]
1
0
1
5
S24
S23
S22
S21
S20
S19
S18
S17
BP2
1
X[1]
1
1
0
6
S32
S31
S30
S29
S28
S27
S26
S25
BP1
1
X[1]
1
1
1
7
S32
S31
S30
S29
S28
S27
S26
S25
BP2
[1]
Don’t care.
Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2.
7.8 Power-on reset
At power-on reset the PCF8577C resets to a defined starting condition as follows:
1. Both backplane outputs are set to VSS in master mode; to 3-state in cascade mode
2. All segment outputs are set to VSS
3. The segment byte registers and control register are cleared
4. The I2C-bus interface is initialized.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
8. I2C-bus interface
8.1 Characteristics of the I2C-Bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the I2C-bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals.
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8.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the I2C-bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P).
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Fig 7.
Definition of START and STOP conditions
8.1.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
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Fig 8.
System configuration
8.1.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The
acknowledge bit is a HIGH level put on the I2C-bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each byte. Also a master must
generate an acknowledge after the reception of each byte that has been clocked out of
the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, set-up and hold times must be taken into account. A master
receiver must signal an end of data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In this event, the transmitter must
leave the data line HIGH to enable the master to generate a STOP condition.
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Fig 9.
Acknowledgement of the I2C-bus
8.2 Slave address
The PCF8577C slave address is shown in Table 7.
Table 7.
I2C slave address byte
Slave address
Bit
R/W
7
MSB
6
5
4
3
2
1
0
LSB
0
1
1
1
0
1
0
0
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always done with the first byte transmitted after the
start procedure.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
8.3 I2C-bus protocol
The PCF8577C I2C-bus protocol is shown in Figure 10.
The PCF8577C is a slave receiver and has a fixed slave address (see Table 7). All
PCF8577Cs with the same slave address acknowledge the slave address in parallel.
The second byte is always the control byte and is loaded into the control register of each
PCF8577C connected to the I2C-bus. All addressed devices acknowledge the control
byte. Subsequent data bytes are loaded into the segment registers of the selected device.
Any number of data bytes may be loaded in one transfer and in an expanded system
rollover of the SBV from 111 111 to 000 000 is allowed. If a STOP (P) condition is given
after the control byte acknowledge, the segment data remains unchanged. This allows the
BANK bit to be toggled without changing the segment register contents. During loading of
segment data, only the selected PCF8577C gives an acknowledge. Loading is terminated
by generating a STOP (P) condition.
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Fig 10. I2C-bus protocol
9. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+8.0
V
VDD  8.0
VDD
V
0.5
VDD + 0.5
V
0.5
+8.0
V
input current
20
+20
mA
output current
25
+25
mA
IDD
supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
Ptot
total power dissipation
-
500
mW
Po
output power
VLCD
LCD supply voltage
VI
input voltage
VO
output voltage
II
IO
VESD
electrostatic discharge
voltage
[1]
on each of the pins
S1 to S32 and BP1 and BP2
[1]
-
100
mW
HBM
[2]
-
2000
V
MM
[3]
-
200
V
Ilu
latch-up current
[4]
-
100
mA
Tstg
storage temperature
[5]
65
+150
C
Tamb
ambient temperature
40
+85
C
operating device
[1]
Values with respect to VDD.
[2]
Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.
[3]
Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[4]
Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[5]
According to the store and transport requirements (see Ref. 12 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
11. Static characteristics
Table 9.
Static characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to 85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.5
-
6
V
Supplies
VDD
supply voltage
IDD
supply current
no load;
ROSC = 1 M;
COSC = 680 pF
fSCL = 100 kHz
[1]
-
50
125
A
fSCL = 0 Hz
[1]
-
25
75
A
[1]
-
25
40
A
[1]
-
10
20
A
[2]
-
1.1
2.0
V
on pin A0
0
-
0.05
V
on pins A1, SCL, SDA
0
-
0.3VDD
V
on pin A2
0
-
0.1
V
on pin A0
VDD  0.05 -
VDD
V
on pin A1
0.7VDD
-
VDD
V
VDD = 5 V;
Tamb = 25 C
no load;
fSCL = 0 Hz;
A0/OSC = VDD;
VDD = 5 V;
Tamb = 25 C
VPOR
[1]
power-on reset voltage
Logic
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
on pin A2
VDD  0.1
-
VDD
V
on pins SCL, SDA
0.7VDD
-
6
V
-
-
7
pF
3
-
-
mA
on pins A1, SCL, SDA
1
-
+1
A
on pins A2/BP2, BP1
5
-
+5
A
VI = VDD;
on pin A0/OSC
1
-
-
A
[3]
CI
input capacitance
IOL
LOW-level output current
output sink current;
on pin SDA;
VOL = 0.4 V;
VDD = 5 V;
IL
leakage current
VI = VDD or VSS
Ipd
pull-down current
VI = VDD;
on pin A2/BP2
5
1.5
-
A
Istartup
startup current
oscillator;
VI = VSS
-
1.2
5
A
PCF8577C
Product data sheet
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PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
Table 9.
Static characteristics …continued
VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to 85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
20
-
mV
LCD outputs
VDC
DC component of LCD
driver
IOL
LOW-level output current
on pins S1 to S32;
VDD = 5 V;
VOL = 0.8 V
[4]
0.3
-
-
mA
IOH
HIGH-level output current
on pins S1 to S32;
VDD = 5 V;
VOH = VDD  0.8 V
[4]
-
-
0.3
mA
Ro
output resistance
on pins BP1, BP2;
Vo = VSS or VDD or
1⁄ (V
2 SS + VDD)
[5]
-
0.4
5
k
[1]
Inputs at VSS or VDD.
[2]
Resets all logic when VDD < VPOR.
[3]
Periodically sampled, not 100 % tested.
[4]
Outputs measured one at a time.
[5]
Outputs measured one at a time; VDD = 5 V; Iload = 100 A.
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
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14 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
12. Dynamic characteristics
Table 10. Dynamic characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to 85 C; unless otherwise specified. All the timing values are valid within the
operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
fLCD
display frequency
ROSC = 1 M;
COSC = 680 pF
65
90
120
Hz
tBS
driver delays with test
loads
VDD = 5 V
-
20
100
s
-
-
100
kHz
-
-
100
ns
[2]
I2C-bus
fSCL
SCL clock frequency
tSW
tolerable spike width on
I2C-bus
tBUF
bus free time between a
STOP and START
condition
4.7
-
-
s
tSU;STA
set-up time for a repeated
START condition
4.0
-
-
s
tHD;STA
hold time (repeated)
START condition
4.0
-
-
s
tLOW
LOW period of the SCL
clock
4.7
-
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
-
s
tr
rise time of both SDA and
SCL signals
-
-
1.0
s
tf
fall time of both SDA and
SCL signals
-
-
0.3
s
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
4.0
-
-
s
Tamb = 25 C
[1]
Typical conditions: VDD = 5 V; Tamb = 25 C
[2]
Test loads:.
6&/6'$
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Nȍ
9''
6WR6
SLQVWR
Nȍ
9''966
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PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
9
9'' 9
6[
9
W%6
9
9''
%3%3
9'' 9
9
DDD
Fig 11. Driver timing waveforms
6'$
W%8)
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WI
6&/
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WU
W+''$7
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Fig 12. I2C-bus timing diagram; rise and fall times refer to VIL and VIH
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 33
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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NXP Semiconductors
PCF8577C
Product data sheet
13. Application information
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PCF8577C
17 of 33
© NXP Semiconductors N.V. 2014. All rights reserved.
DDD
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
All information provided in this document is subject to legal disclaimers.
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF8577C
Product data sheet
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18 of 33
© NXP Semiconductors N.V. 2014. All rights reserved.
Fig 14. Duplex display; expansion to 2  128 segments using four PCF8577Cs
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
All information provided in this document is subject to legal disclaimers.
&26&
6
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9''
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NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
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DDD
MODE bit must always be set to logic 0 (direct drive).
Bank switching is permitted.
BP1 must always be connected to VSS and A0/OSC must be connected to either VDD or VSS (no
LCD modulation).
Fig 15. Use of PCF8577C as a 32-bit output expander in an I2C-bus application
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
14. Package outline
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Fig 16. Package outline SOT158-1 (VSO40) of PCF8577CT
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
20 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
15. Packing information
15.1 Tape and reel information
For tape and reel packing information, see Ref. 10 “SOT158-1_118” on page 27.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
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PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Table 11.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 12.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
22 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Footprint information
PCF8577C
Product data sheet
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Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
23 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
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Fig 18. Footprint information for reflow soldering of SOT158-1 (VSO40) of PCF8577CT
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
24 of 33
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF8577C
Product data sheet
18. Appendix
18.1 LCD segment driver selection
Table 13.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
PCA8553DTT
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
88
-
-
-
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA8543AHL
60
60
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
Y
Y
40 to 95
I2C
TQFP64
Y
Y
Y
40 to 95
SPI
TQFP64
Y
Y
40 to 105
I2C
LQFP80
Y
Y
40 to 105
I2C
Bare die
Y
PCF8537BH
44
88
-
176 276 352 -
25 of 33
© NXP Semiconductors N.V. 2014. All rights reserved.
PCA8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
2.5 to 5.5 2.5 to 9
60 to
300[1]
60 to
300[1]
PCA9620H
PCA9620U
60
60
120 120 -
240 320 480 240 320 480 -
2.5 to 5.5 2.5 to 9
Y
Y
PCF8576DU
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
N
PCF8577C
PCA8536AT
I2C
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
PCA85134H
-
176 -
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Software programmable.
[2]
Hardware selectable.
-
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
PCF8577C
26 of 33
© NXP Semiconductors N.V. 2014. All rights reserved.
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
All information provided in this document is subject to legal disclaimers.
[1]
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
NXP Semiconductors
PCF8577C
Product data sheet
Table 13.
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
19. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10853 — ESD and EMC sensitivity of IC
[3]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[4]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[6]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8]
JESD78 — IC Latch-Up Test
[9]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] SOT158-1_118 — VSO40; Reel pack; SMD, 13", packing information
[11] UM10204 — I2C-bus specification and user manual
[12] UM10569 — Store and transport requirements
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
20. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8577C v.5
20141010
Product data sheet
-
PCF8577C v.4
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Removed obsolete product types.
PCF8577C v.4
19980730
Product data sheet
-
PCF8577C v.3
PCF8577C v.3
19970328
Product data sheet
-
PCF8577C v.2
PCF8577C v.2
19950608
Product data sheet
-
PCF8577C v.1
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF8577C
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
23. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Ordering information . . . . . . . . . . . . . . . . . . . . .1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Segment byte-segment driver mapping in
direct drive mode . . . . . . . . . . . . . . . . . . . . . . . .8
Segment byte-segment driver mapping in
duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
I2C slave address byte . . . . . . . . . . . . . . . . . . .10
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .12
Static characteristics . . . . . . . . . . . . . . . . . . . .13
Dynamic characteristics . . . . . . . . . . . . . . . . . .15
SnPb eutectic process (from J-STD-020D) . . .22
Lead-free process (from J-STD-020D) . . . . . .22
Selection of LCD segment drivers . . . . . . . . . .25
Revision history . . . . . . . . . . . . . . . . . . . . . . . .28
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
31 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
24. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Block diagram of PCF8577C . . . . . . . . . . . . . . . . .2
Pin configuration for PCF8577CT . . . . . . . . . . . . .3
PCF8577C register organization . . . . . . . . . . . . . .5
Direct drive mode display output waveforms . . . . .6
Duplex mode display output waveforms . . . . . . . .7
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Definition of START and STOP conditions. . . . . . .9
System configuration . . . . . . . . . . . . . . . . . . . . . .10
Acknowledgement of the I2C-bus . . . . . . . . . . . .10
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Driver timing waveforms . . . . . . . . . . . . . . . . . . .16
I2C-bus timing diagram; rise and fall times refer
to VIL and VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Direct display driver; expansion to 256 segments
using eight PCF8577Cs . . . . . . . . . . . . . . . . . . . .17
Duplex display; expansion to 2  128 segments
using four PCF8577Cs . . . . . . . . . . . . . . . . . . . .18
Use of PCF8577C as a 32-bit output expander
in an I2C-bus application . . . . . . . . . . . . . . . . . . .19
Package outline SOT158-1 (VSO40) of
PCF8577CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Footprint information for reflow soldering of
SOT158-1 (VSO40) of PCF8577CT . . . . . . . . . .24
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
32 of 33
PCF8577C
NXP Semiconductors
LCD direct/duplex driver with I²C-bus interface
25. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.3
9
10
11
12
13
14
15
15.1
16
16.1
16.2
16.3
16.4
17
18
18.1
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Hardware subaddress lines A0, A1, and A2 . . . 4
Oscillator A0/OSC . . . . . . . . . . . . . . . . . . . . . . 4
User-accessible registers . . . . . . . . . . . . . . . . . 5
Auto-incremented loading. . . . . . . . . . . . . . . . . 6
Direct drive mode . . . . . . . . . . . . . . . . . . . . . . . 6
Duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Display memory mapping . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 9
Characteristics of the I2C-Bus . . . . . . . . . . . . . 9
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
START and STOP conditions . . . . . . . . . . . . . . 9
System configuration . . . . . . . . . . . . . . . . . . . . 9
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12
Static characteristics. . . . . . . . . . . . . . . . . . . . 13
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Application information. . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Packing information . . . . . . . . . . . . . . . . . . . . 21
Tape and reel information . . . . . . . . . . . . . . . . 21
Soldering of SMD packages . . . . . . . . . . . . . . 21
Introduction to soldering . . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
Footprint information . . . . . . . . . . . . . . . . . . . 23
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LCD segment driver selection. . . . . . . . . . . . . 25
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
21
21.1
21.2
21.3
21.4
22
23
24
25
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
29
30
30
31
32
33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 October 2014
Document identifier: PCF8577C
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