Data Sheet

PCF8534A
Universal LCD driver for low multiplex rates
Rev. 6 — 25 July 2011
Product data sheet
1. General description
The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily
cascaded for larger LCD applications. The PCF8534A is compatible with most
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing, and by display memory switching (static and duplex drive
modes).
• PCF8534AHL/1 should not be used for new design-ins. Replacement part is
PCF85134HL/1
2. Features and benefits

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

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1.
AEC-Q100 compliant (PCF8534AH/1) for automotive applications
Single-chip LCD controller and driver
Selectable backplane drive configurations: static or 2, 3, or 4 backplane multiplexing
60 segment outputs allowing to drive:
 30 7-segment numeric characters
 15 14-segment alphanumeric characters
 Any graphics of up to 240 elements
Cascading supported for larger applications
60  4-bit display data storage RAM
Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high
threshold twisted nematic LCDs
Internal LCD bias generation with voltage follower buffers
Selectable display bias configurations: static, 1⁄2, or 1⁄3
Wide logic power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption
400 kHz I2C-bus interface
No external components required
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Silicon gate CMOS process
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCF8534AHL/1[1]
Name
Description
Delivery form Version
LQFP80
plastic low profile quad flat
package; 80 leads;
body 12  12  1.4 mm
tape and reel
SOT315-1
chip in tray
PCF8534AU
PCF8534AU/DA/1 wire bond die 76 bonding pads;
2.91  2.62  0.38 mm
[1]
Not to be used for new designs. Replacement part is PCF85134HL/1.
4. Marking
Table 2.
PCF8534A
Product data sheet
Marking codes
Type number
Marking code
PCF8534AHL/1
PCF8534AHL
PCF8534AU/DA/1
PC8534A-1
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Block diagram
S0 to S59
BP0 BP1 BP2 BP3
60
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
VSS
PCF8534A
CLK
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSC
OSCILLATOR
POWER-ON
RESET
SCL
INPUT
FILTERS
SDA
COMMAND
DECODE
WRITE DATA
CONTROL
I2C-BUS
CONTROLLER
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
SA0
Fig 1.
DISPLAY
RAM
VDD
A0
A1
A2
001aah614
Block diagram of PCF8534A
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
61 S11
62 S12
63 S13
64 S14
65 S15
66 S16
67 S17
68 S18
69 S19
70 S20
71 S21
72 S22
73 S23
74 S24
75 S25
76 S26
77 S27
78 S28
79 S29
80 S30
6.1 Pinning
S31
1
60 S10
S32
2
59 S9
S33
3
58 S8
S34
4
57 S7
S35
5
56 S6
S36
6
55 S5
S37
7
54 S4
S38
8
53 S3
S39
9
52 S2
S40 10
51 S1
PCF8534AHL
S41 11
50 S0
CLK 40
SCL 39
SDA 38
n.c. 37
n.c. 36
n.c. 35
n.c. 34
BP3 33
BP2 32
BP1 31
BP0 30
41 VDD
S59 29
42 SYNC
S50 20
S58 28
43 OSC
S49 19
S57 27
44 A0
S48 18
S56 26
45 A1
S47 17
S55 25
46 A2
S46 16
S54 24
47 SA0
S45 15
S53 23
48 VSS
S44 14
S52 22
49 VLCD
S43 13
S51 21
S42 12
013aaa158
Top view. For mechanical details, see Figure 25.
Fig 2.
PCF8534A
Product data sheet
Pin configuration for SOT315-1 (PCF8534AHL)
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PCF8534A
NXP Semiconductors
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
11
12
13
14
15
16
17
18
19
20
21
22
23
VSS
VLCD
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
9
10
A2
SA0
F
8
3
7
CLK
A1
2
A0
SCL
6
1
5
SDA
OSC
70
71
72
73
74
75
76
SYNC
S57
S58
S59
BP0
BP1
BP2
BP3
C2
PCF8534A-1
4
64
65
66
67
68
69
VDD
S51
S52
S53
S54
S55
S56
S50
S49
S48
S47
S46
C1
63
62
61
60
59
Universal LCD driver for low multiplex rates
Top view
43
42
41
40
39
38
37
S30
S29
S28
S27
S26
S25
S24
36
35
34
33
32
31
30
29
28
27
26
25
24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
001aai648
Viewed from active side. For mechanical details, see Figure 26.
Fig 3.
PCF8534A
Product data sheet
Pin configuration for the wire bond die (PCF8534AU)
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3.
Symbol
S31 to S59
Product data sheet
Pin
SOT315-1
Wire bond die
1 to 29
44 to 72
Type
Description
output
LCD segment output 31 to 59
BP0 to BP3 30 to 33
73 to 76
output
LCD backplane output 0 to 3
n.c.
34 to 37
-
-
not connected; do not connect and do
not use as feed through
SDA
38
1
input/output
I2C-bus serial data input and output
SCL
39
2
input
I2C-bus serial clock input
CLK
40
3
input/output
external clock input and internal clock
output
VDD
41
4
supply
supply voltage
SYNC
42
5
input/output
cascade synchronization input and
output (active LOW)
OSC
43
6
input
enable input for internal oscillator
A0 to A2
44 to 46
7 to 9
input
subaddress counter input 0 to 2
SA0
47
10
input
I2C-bus slave address input 0
VSS
48
11[1]
supply
ground
VLCD
49
12
supply
input of LCD supply voltage
S0 to S30
50 to 80
13 to 43
output
LCD segment output 0 to 30
[1]
PCF8534A
Pin description
The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8534A is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
60 segments.
The display configurations possible with the PCF8534A depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 4.
All of the display configurations given in Table 4 can be implemented in a typical system
as shown in Figure 5.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 4.
Example of displays suitable for PCF8534A
Table 4.
Selection of possible display configurations
Number of
Backplanes
PCF8534A
Product data sheet
Icons
Digits/Characters
7-segment[1]
14-segment[2]
Dot matrix/
Elements
4
240
30
15
240 (4  60)
3
180
22
11
180 (3  60)
2
120
15
7
120 (2  60)
1
60
7
3
60 (1  60)
[1]
7-segment display has eight elements including the decimal point.
[2]
14-segment display has 16 elements including decimal point and accent dot.
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
VDD
R≤
tr
2Cb
VDD
VLCD
60 segment drives
SDA
HOST
MICROPROCESSOR/
MICROCONTROLLER
LCD PANEL
SCL
PCF8534A
4 backplanes
OSC
A0
A1
A2
(up to 240
elements)
SA0 VSS
001aah616
VSS
Fig 5.
Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF8534A.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8534A resets to the following starting conditions:
•
•
•
•
•
•
•
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 1⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
Display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. If the 1⁄2 bias voltage level
for the 1:2 multiplex drive mode configuration is selected, the center impedance is
bypassed by switch. The LCD voltage can be temperature compensated externally, using
the supply to pin VLCD.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 5.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 5.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off  RMS 
------------------------V LCD
V on  RMS 
-----------------------V LCD
V on  RMS 
D = -----------------------V off  RMS 
static
1
2
static
0
1

3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
1:3 multiplex 3
4
1⁄
3
0.333
0.638
1.915
1:4 multiplex 4
4
1⁄
3
0.333
0.577
1.732
1:2 multiplex 2
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on  RMS  =
V LCD
a 2 + 2a + n
-----------------------------2
n  1 + a
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off  RMS  =
V LCD
a 2 – 2a + n
-----------------------------2
n  1 + a
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
V on  RMS 
D = ----------------------- =
V off  RMS 
2
a + 2a + n
--------------------------2
a – 2a + n
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6  V off  RMS  = 2.449V off  RMS 
4  3
- = 2.309V off  RMS 
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off  RMS  when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determines the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
V on  RMS   V th  on 
(4)
V off  RMS   V th  off 
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Fig 6.
PCF8534A
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 7.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t)  VBP0(t).
Voff(RMS) = 0 V.
Fig 7.
PCF8534A
Product data sheet
Static drive mode waveforms
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8534A allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 8 and
Figure 9.
Tfr
VLCD
BP0
LCD segments
VLCD/2
VSS
state 1
VLCD
BP1
state 2
VLCD/2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
state 1
0V
−VLCD/2
−VLCD
VLCD
VLCD/2
state 2
0V
−VLCD/2
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 8.
PCF8534A
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr
BP0
BP1
Sn
Sn+1
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
PCF8534A
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 10.
Tfr
BP0
BP1
BP2
Sn
Sn+1
Sn+2
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8534A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
15 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 11.
Tfr
BP0
VLCD
2VLCD/3
VLCD/3
VSS
BP1
VLCD
2VLCD/3
VLCD/3
VSS
BP2
VLCD
2VLCD/3
VLCD/3
VSS
BP3
VLCD
2VLCD/3
VLCD/3
VSS
Sn
VLCD
2VLCD/3
VLCD/3
VSS
Sn+1
VLCD
2VLCD/3
VLCD/3
VSS
Sn+2
VLCD
2VLCD/3
VLCD/3
VSS
Sn+3
VLCD
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
state 2
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t)  VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t)  VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 11. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF8534A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
16 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency
fclk. It equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr).
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8534A in the system.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
Remark: A clock signal must always be supplied to the device. Removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8534A timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8534A in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock.
Table 6.
LCD frame frequencies
Operating mode ratio
Frame frequency with respect to fclk (typical)
Unit
fclk = 1536 Hz
f clk
f fr = -------24
64
Hz
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which should be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 60 segment outputs are required, the unused segment outputs must be left
open-circuit.
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PCF8534A
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Universal LCD driver for low multiplex rates
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode BP0 and BP2, respectively, BP1 and BP3 carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 60  4-bit RAM which stores LCD data. A logic 1 in the RAM
bit map indicates the on-state (Von(RMS)) of the corresponding LCD element. Similarly, a
logic 0 indicates the off-state (Voff(RMS)). For more information on Von(RMS) and Voff(RMS),
see Section 7.3.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 12, shows row 0 to row 3 which correspond with the
backplane outputs BP0 to BP3, and column 0 to column 59 which correspond with the
segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the
display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1
with BP1, and so on).
columns
display RAM addresses/segment outputs (S)
0
rows
1
2
3
4
55
56
57
58
59
0
display RAM rows/
backplane outputs 1
(BP)
2
3
013aaa212
The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 12. Display RAM bit map
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Sn+2
Sn+3
static
display RAM filling order
b
f
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
g
e
Sn+6
Sn
Sn+7
c
DP
d
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
a
b
f
g
multiplex
Sn+2
BP1
e
Sn+3
c
Sn+1
1:3
Sn+2
DP
d
a
b
Sn
multiplex
BP1
c
b
f
BP0
g
19 of 52
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Sn+1
BP1
c
d
g e d DP
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged.
Fig 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCF8534A
multiplex
e
f
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
BP2
DP
d
c b a
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
e
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
BP0
f
LSB
Universal LCD driver for low multiplex rates
Rev. 6 — 25 July 2011
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Sn+1
MSB
columns
display RAM address/segment outputs (s)
byte1
byte2
BP0
1:2
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
a
Sn+4
Sn+5
LCD backplanes
NXP Semiconductors
PCF8534A
Product data sheet
LCD segments
drive mode
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
When display data is transmitted to the PCF8534A, the display bytes received are stored
in the display RAM in accordance with the selected LCD multiplex drive mode. The data is
stored as it arrives and depending on the current multiplex drive mode, data is stored
singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a
7-segment display showing all drive modes is given in Figure 13. The RAM filling
organization depicted applies equally to other LCD types.
The following applies to Figure 13:
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and row 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, row
1, and row 2 as three successive 3-bit RAM words, with bit 3 of the third address left
unchanged. It is not recommended to use this bit in a display because of the difficult
addressing. This last bit may, if necessary, be controlled by an additional transfer to
this address. But care should be taken to avoid overwriting adjacent data because
always full bytes are transmitted (see Section 7.10.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, row 1, row 2, and row 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 13. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten before further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 13). If the content of the subaddress counter
and the hardware subaddress do not match, then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
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PCF8534A
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In cascaded applications each PCF8534A in the cascade must be addressed separately.
Initially, the first PCF8534A is selected by sending the device-select command matching
the first hardware subaddress. Then the data pointer is set to the preferred display RAM
address by sending the load-data-pointer command.
Once the display RAM of the first PCF8534A has been written, the second PCF8534A is
selected by sending the device-select command again. This time however the command
matches the hardware subaddress of the second device. Next the load-data-pointer
command is sent to select the preferred display RAM address of the second PCF8534A.
This last step is very important because during writing data to the first PCF8534A, the
data pointer of the second PCF8534A is incremented. In addition, the hardware
subaddress should not be changed while the device is being accessed on the I2C-bus
interface.
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 13 as
well).
Table 7.
Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 8.
Table 8.
Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8, and so on, have to be connected to elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
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PCF8534A
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• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used. But it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Bank selector
7.10.4.1
Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The SYNC signal resets these sequences to the following starting points:
•
•
•
•
row 3 for 1:4 multiplex
row 2 for 1:3 multiplex
row 1 for 1:2 multiplex
row 0 for static mode
The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.10.4.2
Input bank selector
The input bank selector loads display data into the display data in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 14). The input bank selector functions independently to the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF8534A are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequency depends on the blink mode selected (see Table 9).
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Universal LCD driver for low multiplex rates
Table 9.
Blink frequencies
Blink mode
Operating mode ratio
Blink frequency with respect to fclk (typical)
Unit
fclk = 1536 Hz
off
-
blinking off
Hz
1
f clk
f blink = --------768
2
Hz
2
f clk
f blink = -----------1536
1
Hz
3
f clk
f blink = -----------3072
0.5
Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. With the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blink frequency. This mode can also be
specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCF8534A are defined in Table 10.
Table 10.
Definition of commands
Command
PCF8534A
Product data sheet
Operation code
Reference
7
6
5
4
3
2
1
0
mode set
1
1
0
0
E
B
M[1:0]
load data pointer
0
P[6:0]
device select
1
1
1
0
0
A[2:0]
bank select
1
1
1
1
1
0
I
blink select
1
1
1
1
0
AB
BF[1:0]
Table 11
Table 12
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Table 13
O
Table 14
Table 15
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PCF8534A
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Universal LCD driver for low multiplex rates
Table 11.
Mode-set command bit description
Bit
Symbol
Value
Description
7 to 4
-
1100
fixed value
3
E
2
display status
0[1]
disabled (blank)[2]
1
enable
LCD bias configuration[3]
B
1 to 0
0[1]
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; one backplane
10
1:2 multiplex; two backplanes
11
1:3 multiplex; three backplanes
00[1]
1:4 multiplex; four backplanes
[1]
Default value.
[2]
The possibility to disable the display allows implementation of blinking under external control.
[3]
Not applicable for static drive mode.
Table 12. Load data pointer command bit description
See Section 7.10.1 on page 20.
Bit
Symbol
Value
Description
7
-
0
fixed value
P[6:0]
0000000[1]
6 to 0
to
0111011
[1]
7-bit binary value, 0 to 59; transferred to the
data pointer to define one of 60 display RAM
addresses
Default value.
Table 13. Device select command bit description
See Section 7.10.2 on page 20.
Bit
Symbol
Value
Description
7 to 3
-
11100
fixed value
A[2:0]
000[1]
2 to 0
[1]
PCF8534A
Product data sheet
to 111
3-bit binary value, 0 to 7; transferred to the
subaddress counter to define one of eight
hardware subaddresses
Default value.
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Table 14. Bank select command bit description
See Section 7.10.4 on page 22.
Bit
Symbol
Value
Description
Static
7 to 2
-
1
I
0
111110
1:2 multiplex[1]
fixed value
input bank selection: storage of arriving
display data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
O
output bank selection: retrieval of LCD display
data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
[1]
The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
[2]
Default value.
Table 15. Blink select command bit description
Section 7.11 on page 22.
Bit
Symbol
Value
Description
7 to 3
-
11110
fixed value
2
AB
1 to 0
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
blink frequency selection[4]
BF[1:0]
00[1]
off
01
1
10
2
11
3
[1]
Default value.
[2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
[4]
For the blink frequencies, see Table 9.
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8534A and coordinates their effects. The display
controller is also responsible for loading display data into the display RAM in the correct
filling order.
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Universal LCD driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 14).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 14. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START
condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
The START and STOP conditions are illustrated in Figure 15.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 15. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 16.
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PCF8534A
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Universal LCD driver for low multiplex rates
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 16. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 17.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 17. Acknowledgement of the I2C-bus
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PCF8534A
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Universal LCD driver for low multiplex rates
8.5 I2C-bus controller
The PCF8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8534A are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF8534A. The entire I2C-bus slave address byte is shown in Table 16.
Table 16.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
SA0
R/W
The PCF8534A is a write-only device and does not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF8534A will
respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 16 PCF8534A for large LCD applications
• The use of two types of LCD multiplex drive
The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the available PCF8534A
slave addresses. All PCF8534A with the same SA0 level acknowledge in parallel to the
slave address. All PCF8534A with the alternative SA0 level ignore the whole I2C-bus
transfer.
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PCF8534A
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Universal LCD driver for low multiplex rates
R/W = 0
slave address
control byte
RAM/command byte
S
C R
S 0 1 1 1 0 0 A 0 A
O S
0
M
A S
B
L
S P
B
EXAMPLES
a) transmit two bytes of RAM data
S
S 0 1 1 1 0 0 A 0 A 0 1
0
RAM DATA
A
RAM DATA
A
A
COMMAND
A 0 0
A
COMMAND
A P
A
COMMAND
A 0 1
A
RAM DATA
A
A P
b) transmit two command bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
c) transmit one command byte and two RAM date bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
RAM DATA
A P
mgl752
Fig 18. I2C-bus protocol
After acknowledgement, the control byte is sent defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 19 and Table 17). In this way it is possible to
configure the device and then fill the display RAM with little overhead.
MSB
7
6
5
CO RS
4
3
2
LSB
0
1
not relevant
mgl753
Fig 19. Control byte format
Table 17.
Control byte description
Bit
Symbol
7
CO
Value
continue bit
0
1
6
5 to 0
RS
-
Description
last control byte
control bytes continue
register selection
0
command register
1
data register
unused
The command bytes and control bytes are also acknowledged by all addressed
PCF8534A connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8534A. After the last display byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be issued to RESTART I2C-bus access.
9. Internal circuitry
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1, A2
VLCD
VSS
VLCD
VSS
BP0, BP1,
BP2, BP3
VSS
VLCD
S0 to S59
VSS
001aah615
Fig 20. Device protection diagram
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
10. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
IDD
Min
Max
Unit
supply voltage
0.5
+6.5
V
supply current
50
+50
mA
VLCD
LCD supply voltage
0.5
+7.5
V
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
VI
input voltage
[1]
0.5
+6.5
V
II
input current
[1]
10
+10
mA
output voltage
[1]
0.5
+6.5
V
[2]
0.5
+7.5
V
10
+10
mA
VO
Product data sheet
[1][2]
IO
output current
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic discharge
voltage
HBM
[3]
-
3000
V
CDM
[4]
-
1000
V
latch-up current
[5]
-
200
mA
Tstg
storage temperature
[6]
65
+150
C
Tamb
ambient temperature
40
+85
C
Ilu
PCF8534A
Conditions
operating device
[1]
Pins SDA, SCL, CLK, SYNC, SA0, OSC, and A0 to A2.
[2]
Pins S0 to S59 and BP0 to BP3.
[3]
Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.
[4]
Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”.
[5]
Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (Tamb(max)).
[6]
According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be
stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long-term storage products
deviant conditions are described in that document.
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 19. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
2.5
-
6.5
V
IDD
supply current
IDD(LCD)
LCD supply current
fclk = 1536 Hz
[1]
-
8
20
A
fclk = 1536 Hz
[1]
-
24
60
A
Logic
VSS  0.5
VI
input voltage
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC, A0 to A2
and SA0
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC, A0 to A2
and SA0
0.7VDD
-
VDD
V
VPOR
power-on reset voltage
1.0
1.3
1.6
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 5 V; on pins CLK
and SYNC
1
-
-
mA
IOH
HIGH-level output current
VOH = 4.6 V; VDD = 5 V; on pin CLK
1
-
-
mA
IL
leakage current
VI = VDD or VSS; on pins SA0, A0 to
A2 and CLK
1
-
+1
A
1
-
+1
A
CI
input capacitance
-
-
7
pF
VSS  0.5
-
5.5
V
pin SCL
VSS
-
0.3VDD
V
pin SDA
VSS
-
0.2VDD
V
0.7VDD
-
5.5
V
3
-
-
mA
1
-
+1
A
-
-
7
pF
VI = VDD; on pin OSC
I2C-bus;
pins SDA and
[2]
SCL[3]
VI
input voltage
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
VOL = 0.4 V; VDD = 5 V; on pin SDA
IL
leakage current
VI = VDD or VSS
Ci
input capacitance
PCF8534A
Product data sheet
VDD + 0.5 V
[2]
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 19. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LCD outputs
Output pins BP0, BP1, BP2 and BP3
VBP
voltage on pin BP
Cbpl = 35 nF
[4]
100
-
+100
mV
RBP
resistance on pin BP
VLCD = 5 V
[5]
-
1.5
10
k
Csgm = 35 nF
[6]
100
-
+100
mV
VLCD = 5 V
[5]
-
6.0
13.5
k
Output pins S0 to S59
voltage on pin S
VS
resistance on pin S
RS
[1]
LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2]
Not tested, design specification only.
[3]
The I2C-bus interface of PCF8534A is 5 V tolerant.
[4]
Cbpl = backplane capacitance.
[5]
Outputs measured individually and sequentially.
[6]
Csgm = segment capacitance.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 20. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
960
1536
3046
Hz
797
1536
3046
Hz
Clock
Internal: output pin CLK
oscillator frequency
fosc
VDD = 5 V
[1]
External: input pin CLK
fclk(ext)
external clock frequency
VDD = 5 V
tclk(H)
HIGH-level clock time
130
-
-
s
tclk(L)
LOW-level clock time
130
-
-
s
Synchronization: input pin SYNC
tPD(SYNC_N)
SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
1
-
-
s
-
-
30
s
Outputs: pins BP0 to BP3 and S0 to S59
tPD(drv)
I2C-bus:
driver propagation delay
VLCD = 5 V
timing[2]
Pin SCL
fSCL
SCL frequency
-
-
400
kHz
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a STOP and
START condition
1.3
-
-
s
tSU;STO
set-up time for STOP condition
0.6
-
-
s
tHD;STA
hold time (repeated) START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated START
condition
0.6
-
-
s
tr
rise time of both SDA and SCL signals
-
-
0.3
s
tf
fall time of both SDA and SCL signals
-
-
0.3
s
Cb
capacitive load for each bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
[1]
Typical output (duty cycle  = 50 %).
[2]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
1 / fclk
tclk(H)
tclk(L)
0.7VDD
CLK
0.3VDD
0.7VDD
SYNC
0.3VDD
tPD(SYNC_N)
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S59
(VDD = 5 V)
0.5 V
tPD(drv)
001aah618
Fig 21. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 22. I2C-bus timing waveforms
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
Large display configurations of up to 16 PCF8534As can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable
I2C-bus slave address (SA0).
Table 21.
Addressing cascaded PCF8534A
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
2
1
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
When cascaded PCF8534A are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF8534A of the cascade contribute
additional segment outputs, but their backplane outputs are left open-circuit
(see Figure 23).
PCF8534A
Product data sheet
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36 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
VDD
VLCD
SDA
60 segment drives
SCL
SYNC
PCF8534A
CLK
(2)
BP0 to BP3
(open-circuit)
OSC
A0
A1
SA0 VSS
A2
LCD PANEL
VLCD
VDD
R≤
HOST
MICROPROCESSOR/
MICROCONTROLLER
tr
2Cb
VDD
VLCD
60 segment drives
SDA
SCL
SYNC
PCF8534A
CLK
4 backplanes
(1)
BP0 to BP3
OSC
A0
A1
A2
VSS
SA0 VSS
013aaa513
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 23. Cascaded PCF8534A configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8534A. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (for example, by noise
in adverse electrical environments or by defining a multiplex drive mode when PCF8534A
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8534A are shown in Figure 24.
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed
for the number of devices in cascade is given in Table 22.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000 
3 to 5
2200 
6 to 10
1200 
11 to 16
700 
The PCF8534A can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 22 and Figure 24 show the timing of the
synchronization signals.
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 24. Synchronization of the cascade for various PCF8534A drive modes
In a cascaded configuration, only one PCF8534A master must be used as clock source.
All other PCF8534A in the cascade must be configured as slave such that they receive
the clock from the master.
PCF8534A
Product data sheet
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Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
38 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
If an external clock source is used, all PCF8534A in the cascade must be configured such
as to receive the clock from that external source (pin OSC connected to VDD). It must be
ensured that the clock tree is designed such that on all PCF8534A the clock propagation
delay from the clock source to all PCF8534A in the cascade is as equal as possible since
otherwise synchronization artifacts may occur.
In mixed cascading configurations, care has to be taken that the specifications of the
individual cascaded devices are met at all times.
PCF8534A
Product data sheet
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Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
39 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y
X
A
60
41
40 Z E
61
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
80
21
detail X
20
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.16
0.04
1.5
1.3
0.25
0.27
0.13
0.18
0.12
12.1
11.9
12.1
11.9
0.5
HD
HE
14.15 14.15
13.85 13.85
L
Lp
v
w
y
1
0.75
0.30
0.2
0.15
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7o
o
0
1.45
1.05
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT315-1
136E15
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 25. Package outline SOT315-1 (LQFP80)
PCF8534A
Product data sheet
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40 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
15. Bare die outline
Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm
PCF8534AU
D
e
A
63
44
C1
C2
e
64
43
PC8534A-1(3)
x
0
76
E
0
y
1
24
3
F
4
23
X
0
0.5
1 mm
scale
P4
P3
DIMENSIONS (mm are the original dimensions)
UNIT
mm
max
nom
min
A
D
E
e
P1(1)
P2(2)
P3(1)
P4(2)
P2
0.38
2.91
2.62
0.06
0.05
0.10
0.09
0.08
P1
detail X
Notes
1. Pad size
2. Passivation opening
3. Marking code
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
PCF8534AU
EUROPEAN
PROJECTION
ISSUE DATE
08-08-06
Fig 26. PCF8534AU die outline
PCF8534A
Product data sheet
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Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
41 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23.
Symbol
PCF8534A
Product data sheet
Bonding pad locations
Pad
Coordinates[1]
X (m)
Y (m)
Description
SDA
1
1384.4
280
I2C-bus serial data input and output
SCL
2
1384.4
760.5
I2C-bus serial clock input
CLK
3
1384.4
945
external clock input and output
VDD
4
978.7
1238
supply voltage
SYNC
5
829.3
1238
cascade synchronization input and output
OSC
6
714.3
1238
enable input for internal oscillator
A0
7
584.3
1238
subaddress counter input
A1
8
454.3
1238
A2
9
324.3
1238
SA0
10
194.3
1238
I2C-bus slave address input 0
VSS
11
64.3
1238
ground
VLCD
12
68.7
1238
input of LCD supply voltage
S0
13
173.7
1238
LCD segment output
S1
14
253.7
1238
S2
15
333.7
1238
S3
16
413.7
1238
S4
17
493.7
1238
S5
18
573.7
1238
S6
19
653.7
1238
S7
20
733.7
1238
S8
21
813.7
1238
S9
22
893.7
1238
S10
23
973.7
1238
S11
24
1384.4
841
S12
25
1384.4
761
S13
26
1384.4
681
S14
27
1384.4
601
S15
28
1384.4
521
S16
29
1384.4
441
S17
30
1384.4
361
S18
31
1384.4
281
S19
32
1384.4
201
S20
33
1384.4
121
S21
34
1384.4
41
S22
35
1384.4
39
S23
36
1384.4
119
S24
37
1384.4
301.6
S25
38
1384.4
381.6
S26
39
1384.4
461.6
S27
40
1384.4
541.6
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23.
Symbol
Product data sheet
Pad
Coordinates[1]
X (m)
Y (m)
S28
41
1384.4
621.6
S29
42
1384.4
701.6
S30
43
1384.4
781.6
S31
44
896.5
1239.4
S32
45
816.5
1239.4
S33
46
736.5
1239.4
S34
47
576.5
1239.4
S35
48
496.5
1239.4
S36
49
416.5
1239.4
S37
50
336.5
1239.4
S38
51
256.5
1239.4
S39
52
176.5
1239.4
S40
53
96.5
1239.4
S41
54
16.5
1239.4
S42
55
63.5
1239.4
S43
56
143.5
1239.4
S44
57
223.5
1239.4
S45
58
303.5
1239.4
S46
59
463.5
1239.4
S47
60
543.5
1239.4
S48
61
623.5
1239.4
S49
62
703.5
1239.4
S50
63
783.5
1239.4
S51
64
1384.4
935
S52
65
1384.4
855
S53
66
1384.4
775
S54
67
1384.4
695
S55
68
1384.4
615
S56
69
1384.4
535
S57
70
1384.4
375
S58
71
1384.4
295
S59
72
1384.4
215
BP0
73
1384.4
125
BP1
74
1384.4
45
BP2
75
1384.4
35
BP3
76
1384.4
115
[1]
PCF8534A
Bonding pad locations …continued
Description
LCD segment output
LCD backplane output
All coordinates are referenced in m to the center of the die (see Figure 26).
All information provided in this document is subject to legal disclaimers.
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
REF
REF
C1
C2
REF
F
001aai649
Fig 27. Alignment marks
Table 24.
Alignment mark locations [1]
Symbol
X (m)
Y (m)
C1
1387
1190
C2
1335
1242
F
1345
1173
[1]
All coordinates are referenced in m to the center of the die (see Figure 26).
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
17. Packing information
A
1.1
2.1
1.2
2.2
C
x.1
3.1
D
1.3
F
B
1.y
y
E
x
001aai625
Fig 28. Tray details for PCF8534AU/DA/1
PC8534A-1
001aai650
Fig 29. Tray alignment for PCF8534AU/DA/1
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 25.
Tray dimensions
Symbol
Description
Value
A
pocket pitch in x direction
5.5 mm
B
pocket pitch in y direction
4.9 mm
C
pocket width in x direction
3.08 mm
D
pocket width in y direction
2.79 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
N
number of pockets, x direction
8
M
number of pockets, y direction
9
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 26 and 27
Table 26.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 27.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.
PCF8534A
Product data sheet
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PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Abbreviations
Table 28.
PCF8534A
Product data sheet
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
IC
Integrated Circuit
LCD
Liquid Crystal Display
MM
Machine Model
RAM
Random Access Memory
All information provided in this document is subject to legal disclaimers.
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48 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
20. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[3]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[4]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid-State Surface Mount Devices
[5]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[6]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[7]
JESD78 — IC Latch-Up Test
[8]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[9]
NX3-00092 — NXP store and transport requirements
[10] SNV-FA-01-02 — Marking Formats Integrated Circuits
[11] UM10204 — I2C-bus specification and user manual
21. Revision history
Table 29.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8534A v.6
20110725
Product data sheet
-
PCF8534A_5
Modifications:
•
•
•
Added design-in and replacement part information
Changed description of Table 17
Added Section 7.10.3
PCF8534A_5
20090806
Product data sheet
-
PCF8534A_4
PCF8534A_4
20090716
Product data sheet
-
PCF8534A_3
PCF8534A_3
20081110
Product data sheet
-
PCF8534A_2
PCF8534A_2
20080604
Product data sheet
-
PCF8534A_1
PCF8534A_1
20080423
Product data sheet
-
-
PCF8534A
Product data sheet
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© NXP B.V. 2011. All rights reserved.
49 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
PCF8534A
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 25 July 2011
© NXP B.V. 2011. All rights reserved.
50 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
22.4 Trademarks
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8534A
Product data sheet
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51 of 52
PCF8534A
NXP Semiconductors
Universal LCD driver for low multiplex rates
24. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
Functional description . . . . . . . . . . . . . . . . . . . 7
7.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 8
7.2
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8
7.3
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9
7.3.1
Electro-optical performance . . . . . . . . . . . . . . 10
7.4
LCD drive mode waveforms . . . . . . . . . . . . . . 12
7.4.1
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12
7.4.2
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
7.4.3
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.4.4
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 16
7.5
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5.1
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.7
Display register . . . . . . . . . . . . . . . . . . . . . . . . 17
7.8
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17
7.9
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18
7.10
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.10.1
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.10.2
Subaddress counter . . . . . . . . . . . . . . . . . . . . 20
7.10.3
RAM writing in 1:3 multiplex drive mode. . . . . 21
7.10.4
Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.10.4.1 Output bank selector . . . . . . . . . . . . . . . . . . . 22
7.10.4.2 Input bank selector . . . . . . . . . . . . . . . . . . . . . 22
7.11
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.12
Command decoder . . . . . . . . . . . . . . . . . . . . . 23
7.13
Display controller . . . . . . . . . . . . . . . . . . . . . . 25
8
Characteristics of the I2C-bus . . . . . . . . . . . . 26
8.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2
START and STOP conditions . . . . . . . . . . . . . 26
8.3
System configuration . . . . . . . . . . . . . . . . . . . 26
8.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.5
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 28
8.6
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.7
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 28
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 30
10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 31
11
Static characteristics. . . . . . . . . . . . . . . . . . . . 32
12
13
13.1
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
21
22
22.1
22.2
22.3
22.4
23
24
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Cascaded operation. . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
36
36
40
41
44
45
46
46
46
47
47
48
49
49
50
50
50
50
51
51
52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 July 2011
Document identifier: PCF8534A
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