Data Sheet

PCF8566
Universal LCD driver for low multiplex rates
Rev. 07 — 25 February 2009
Product data sheet
1. General description
The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 24 segments and can easily be cascaded
for larger LCD applications. The PCF8566 is compatible with most microprocessors or
microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
2. Features
n Single-chip LCD controller/driver
n 24 segment drives:
u Up to twelve 7-segment numeric characters including decimal pointer
u Up to six 14-segment alphanumeric characters
u Any graphics of up to 96 elements
n Versatile blinking modes
n No external components required (even in multiple device applications)
n Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
n Selectable display bias configuration: static, 1⁄2 or 1⁄3
n Internal LCD bias generation with voltage-follower buffers
n 24 × 4-bit RAM for display data storage
n Auto-incremented display data loading across device subaddress boundaries
n Display memory bank switching in static and duplex drive modes
n LCD and logic supplies may be separated
n 2.5 V to 6 V power supply range
n Low power consumption
n Power-saving mode for extremely low power consumption in battery-operated and
telephone applications
n I2C-bus interface
n TTL and CMOS compatible
n Compatible with any 4, 8 or 16-bit microprocessor or microcontroller
n May be cascaded for large LCD applications (up to 1536 segments possible)
n Cascadable with 40-segment LCD driver PCF8576C
n Optimized pinning for plane wiring in both and multiple PCF8566 applications
n Space-saving 40-lead plastic very small outline package (VSO40; SOT158-1)
n Manufactured in silicon gate CMOS process
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF8566P
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
PCF8566T
VSO40
plastic very small outline package; 40 leads
SOT158-1
PCF8566TS[1]
VSO40
plastic very small outline package; 40 leads
SOT158-1
PCF8566U[2]
PCF8566U
wire bond die; 40 bonding pads;
2.5 × 2.91 × 0.381 mm
PCF8566U
[1]
Dark-green version.
[2]
Chip in tray for chip on board.
4. Marking
Table 2.
Marking codes
Type number
Marking code
PCF8566P
PCF8566P
PCF8566T
PCF8566T
PCF8566TS
PCF8566TS
PCF8566U
PC8566-1
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
2 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3
13
VDD
5
14
15
S0 to S23
16
BACKPLANE
OUTPUTS
17 to 40
DISPLAY SEGMENT OUTPUTS
R
LCD
VOLTAGE
SELECTOR
R
R
VLCD
CLK
SYNC
12
LCD BIAS
GENERATOR
SHIFT REGISTER
PCF8566
4
3
DISPLAY LATCH
TIMING
INPUT
BANK
SELECTOR
BLINKER
DISPLAY
RAM
24 × 4 BITS
OUTPUT
BANK
SELECTOR
DISPLAY
CONTROLLER
OSC
VSS
SCL
SDA
6
OSCILLATOR
POWERON
RESET
DATA
POINTER
COMMAND
DECODER
11
2
1
INPUT
FILTERS
SUBADDRESS
COUNTER
I2C-BUS
CONTROLLER
10
7
SA0
A0
8
A1
9
A2
mgg383
Fig 1. Block diagram of PCF8566
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
3 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
SDA
1
40 S23
SCL
2
39 S22
SYNC
3
38 S21
CLK
4
37 S20
VDD
5
36 S19
OSC
6
35 S18
A0
7
34 S17
A1
8
33 S16
A2
9
32 S15
SA0 10
VSS 11
PCF8566
31 S14
30 S13
VLCD 12
29 S12
BP0 13
28 S11
BP2 14
27 S10
BP1 15
26 S9
BP3 16
25 S8
S0 17
24 S7
S1 18
23 S6
S2 19
22 S5
S3 20
21 S4
001aai338
Fig 2. Pin configuration for PCF8566
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
4 of 48
PCF8566
NXP Semiconductors
S8
S7
S6
S5
S4
S3
S2
S1
S0
BP3
Universal LCD driver for low multiplex rates
25
24
23
22
21
20
19
18
17
16
15
BP1
S9
26
14
BP2
S10
27
13
BP0
S11
28
12
VLCD
S12
29
S13
30
11
VSS
S14
31
10
SA0
S15
32
9
A2
S16
33
8
A1
S17
34
7
A0
S18
35
6
OSC
36
37
38
39
40
1
2
3
4
5
S19
S20
S21
S22
S23
SDA
SCL
SYNC
CLK
VDD
PCF8566U
mbh783
Fig 3. Pin configuration for PCF8566U
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SDA
1
I2C-bus data input and output
SCL
2
I2C-bus clock input and output
SYNC
3
cascade synchronization input and output
CLK
4
external clock input and output
VDD
5
positive supply voltage[1]
OSC
6
oscillator select
A0
7
I2C-bus subaddress inputs
A1
8
A2
9
SA0
10
I2C-bus slave address bit 0 input
VSS
11
logic ground
VLCD
12
LCD supply voltage
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
5 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 3.
Pin description …continued
Symbol
Pin
Description
BP0
13
LCD backplane outputs
BP2
14
BP1
15
BP3
16
S0 to S23
17 to 40
[1]
LCD segment outputs
The substrate (rear side of the die) is wired to VDD but should not be electrically connected.
7. Functional description
The PCF8566 is a versatile peripheral device designed to interface any
microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static
or multiplexed LCD containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566 depend on the number of active
backplane outputs required. Display configuration selection is shown in Table 4. All of the
display configurations given in Table 4 can be implemented in the typical system shown in
Figure 4.
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8566.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.
Table 4.
Display configurations
Backplanes Elements
7-segment numeric
14-segment numeric
Digits
Indicator
symbols
Characters
Indicator
symbols
4
96
12
12
6
12
96 (4 × 24)
3
72
9
9
4
16
72 (3 × 24)
2
48
6
6
3
6
48 (2 × 24)
1
24
3
3
1
10
24
PCF8566_7
Product data sheet
Dot matrix
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
6 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
VDD
R≤
trise
2 Cbus
HOST
MICROPROCESSOR/
MICROCONTROLLER
VDD
SDA
SCL
OSC
VLCD
5
12
1
17 to 40
24 segment drives
PCF8566
2
6
13 to 16
7
A0
8
A1
9
A2
10
4 backplanes
LCD PANEL
(up to 96
elements)
11
SA0 VSS
mgg385
VSS
Fig 4. Typical system configuration
7.1 Power-on reset
At power-on the PCF8566 resets to the following starting conditions:
•
•
•
•
•
•
•
All backplane outputs are set to VDD
All segment outputs are set to VDD
Drive mode 1:4 multiplex with 1⁄3 bias is selected
Blinking is switched off
Input and output bank selectors are reset (as defined in Table 8)
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared
Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex
configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D), are given in Table 5.
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
7 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 5.
Preferred LCD drive modes: summary of characteristics
LCD drive mode Number of:
Backplanes
Bias levels
LCD bias
configuration
static
1
2
static
0
1
∞
1:2 multiplex
2
3
1⁄
2
0.354
0.791
2.236
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:2 multiplex
1:3 multiplex
1:4 multiplex
2
3
4
V off ( RMS )
-------------------------V LCD
V on ( RMS )
------------------------V LCD
V on ( RMS )
D = -------------------------V off ( RMS )
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
V on ( RMS ) =
V LCD
2
1
1
--- + ( n – 1 ) ×  -------------
 1 + a
n
-----------------------------------------------------------n
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation:
2
V off ( RMS ) =
V LCD
a – ( 2a + n )
-------------------------------2
n × (1 + a)
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
V on ( RMS )
------------------------ =
V off ( RMS )
2
(a + 1) + (n – 1)
------------------------------------------2
(a – 1) + (n – 1)
(3)
Using Equation 3, the discrimination for an LCD drive mode of
• 1:3 multiplex with 1⁄2 bias is 3 = 1.732
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
8 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
21
3
• 1:4 multiplex with 1⁄2 bias is ---------- = 1.528
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS )
4 × 3)
• 1:4 multiplex (1⁄2 bias): V LCD = (--------------------- = 2.309V off ( RMS )
3
These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
9 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 5.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl745
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = VSn+1(t) − VBP0(t).
Voff(RMS) = 0 V.
Fig 5.
Static drive mode waveforms
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
10 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8566 allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 6 and Figure 7).
Tfr
VLCD
BP0
LCD segments
VLCD / 2
VSS
state 1
VLCD
BP1
state 2
VLCD / 2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD / 2
state 1
0V
−VLCD / 2
−VLCD
VLCD
VLCD / 2
state 2
0V
−VLCD / 2
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl746
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.354VLCD
Fig 6.
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
11 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl747
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) − VBP1(t)
Voff(RMS) = 0.333VLCD.
Fig 7.
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
12 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 8.
Tfr
VLCD
BP0
BP1
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
2VLCD / 3
state 2
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
Sn+1
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl748
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8.
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
13 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 9.
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
BP3
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+3
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl749
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
Waveforms for the 1:4 multiplex mode with 1⁄3 bias
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
14 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext).
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8566s or PCF8576s in the
system.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state.
7.6 Timing
The timing of the PCF8566 sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8566s in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 6). The frame frequency is set by the mode set commands when an internal clock is
used or by the frequency applied to the pin CLK when an external clock is used.
Table 6.
LCD frame frequencies [1]
PCF8566 mode
Frame frequency
Nominal frame frequency (Hz)
normal mode
f clk
f fr = -----------2880
69 [2]
power saving mode
f clk
f fr = --------480
65 [3]
[1]
The possible values for fclk see Table 20.
[2]
For fclk = 200 kHz.
[3]
For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
mode in which the device is operating. In the power-saving mode the reduction ratio is six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a significant reduction in power dissipation.
PCF8566_7
Product data sheet
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I2C-bus. When a device is unable to
process a display data byte before the next one arrives, it holds the SCL line LOW until the
first display data byte is stored. This slows down the transmission rate of the I2C-bus but
no data loss occurs.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
7.8 Shift register
The shift register transfers display information from the display RAM to the display register
while previous data is displayed.
7.9 Segment outputs
The LCD drive section includes 24 segment outputs S0 to S23 which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
24 segment outputs are required, the unused segment outputs should be left open-circuit.
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAM is a static 24 × 4-bit RAM which stores LCD data. Logic 1 in the RAM bit
map indicates the on-state of the corresponding LCD segment; similarly, logic 0 indicates
the off-state. There is a direct relationship between the RAM addresses and the segment
outputs, and between the individual bits of a RAM word and the backplane outputs. The
first RAM row corresponds to the 24 segments operated with respect to backplane BP0
(see Figure 10). In multiplexed LCD applications, the segment data of rows 1 to 4 of the
display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
16 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
19
20
21
22
23
0
display RAM bits
1
(rows)/
backplane outputs
2
(BP)
3
mgg389
Fig 10. Display RAM bit map showing the direct relationship between display RAM
addresses and segment outputs and between bits in a RAM word and backplane
outputs
When display data is transmitted to the PCF8566 the display bytes received are stored in
the display RAM based on the selected LCD drive mode. An example of a 7-segment
numeric display illustrating the storage order for all drive modes is shown in Figure 11.
The RAM storage organization applies equally to other LCD types.
The following applies to Figure 11:
• Static drive mode: the eight transmitted data bits are placed in row 0 to eight
successive display RAM addresses.
• 1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to
four successive display RAM addresses.
• 1:3 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1 and 2 of
three successive addresses, with bit 2 of the third address left unchanged. This last bit
can, if necessary, be controlled by an additional transfer to this address but avoid
overriding adjacent data because always full bytes are transmitted.
• 1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and
3 to two successive display RAM addresses.
7.12 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load data pointer command (see Table 13). After this, the data byte is
stored starting at the display RAM address indicated by the data pointer (see Figure 11).
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
PCF8566_7
Product data sheet
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LCD segments
g
Sn+7
c
Sn+1
DP
BP1
e
Sn+1
DP
b
f
e
BP1
c
Sn
BP2
DP
b
n 6
n 7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n
n 1
n 2
n 3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
n
n 1
n 2
b
DP
c
x
a
d
g
x
f
e
x
x
n
n 1
a
c
b
DP
f
e
g
d
LSB
c b a f
g e d DP
e
BP0
bit/
BP
BP1
c
d
MSB
a b f
LSB
g e c d DP
0
1
2
3
MSB
LSB
b DP c a d g f
e
BP2
g
Sn+1
0
1
2
3
a
f
multiplex
n 5
Sn
bit/
BP
d
1:4
n 4
BP0
a
g
multiplex
bit/
BP
c
d
Sn+2
n 3
b
f
Sn+3
1:3
n 2
BP3
0
1
2
3
MSB
a c b DP f
LSB
e g d
DP
x = data bit unchanged
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCF8566
18 of 48
© NXP B.V. 2009. All rights reserved.
mgl751
Universal LCD driver for low multiplex rates
Rev. 07 — 25 February 2009
Sn+2
0
1
2
3
a
g
multiplex
n 1
BP0
Sn
1:2
n
MSB
bit/
BP
Sn
d
Sn+6
transmitted display byte
Sn+1
e
Sn+5
BP0
b
f
Sn+4
static
display RAM filling order
a
Sn+2
Sn+3
LCD backplanes
NXP Semiconductors
PCF8566_7
Product data sheet
drive mode
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.13 Sub-address counter
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device select command (see Table 14 and Table 21). If the contents of the
subaddress counter and the hardware subaddress do not match then data storage is
blocked but the data pointer will be incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8566 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
7.14 Output bank selector
The output bank selector (see Table 15), selects one of the four bits per display RAM
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
• In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.
• In 1:2 multiplex mode: bits 0 and 1 are selected.
• In the static mode: bit 0 is selected.
The PCF8566 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank select command may request the contents of
bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode,
the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables
preparation of display information in an alternative bank and the ability to switch to it once
it has been assembled.
7.15 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. Using the bank select command, display data can be loaded in
bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank
selector functions independently of the output bank selector.
7.16 Blinker
The display blinking capabilities of the PCF8566 are very versatile. The whole display can
be blinked at frequencies selected by the blink command. The blinking frequencies are
integer fractions of the clock frequency; the ratios between the clock and blinking
frequencies depend on the mode in which the device is operating (see Table 7).
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 7.
Blink frequencies
Blinking mode
Normal operating
mode ratio
Power saving mode
ratio
Blink frequency
off
-
-
blinking off
1
f clk
f blink = --------------92160
f elk
f blink = --------------15360
2 Hz
2
f clk
f blink = ------------------184320
f clk
f blink = --------------30720
1 Hz
3
f clk
f blink = ------------------368640
f clk
f blink = --------------61440
0.5 Hz
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see Table 9).
8. Basic architecture
8.1 Characteristics of the I2C-bus
The I2C-bus provides bidirectional, two-line communication between different IC or
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 12.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 12. Bit transfer
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.1.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 13.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 13. Definition of START and STOP conditions
8.1.2 System configuration
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure 14.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Fig 14. System configuration
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. (See
Figure 15).
Acknowledgement on the I2C-bus is illustrated in
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
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PCF8566
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Universal LCD driver for low multiplex rates
• A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 15. Acknowledgement on the I2C-bus
8.1.4 PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8566 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2C-bus slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8566 is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2C-bus and serves
to slow down fast transmitters. Data loss does not occur.
8.1.5 Input filter
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.2 I2C-bus protocol
Two I2C-bus 7 bit slave addresses (0111 110 and 0111 111) are reserved for the
PCF8566. The least significant bit after the slave address is bit R/W. The PCF8566 is a
write-only device. It will not respond to a read access, so this bit should always be logic 0.
The second bit of the slave address is defined by the level tied at input SA0.
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
R/W
slave address
S
0 1 1 1 1 1 A 0
0
1 byte
001aai455
Fig 16. Slave address structure
Two displays controlled by PCF8566 can be recognized on the same I2C-bus which
allows:
• Up to 16 PCF8566s on the same I2C-bus for very large LCD applications (see
Section 13)
• The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the PCF8566 slave
addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave
address. All PCF8566s with the alternative SA0 level ignore the whole I2C-bus transfer.
After acknowledgement, one or more command bytes (m) follow which define the status of
the addressed PCF8566s. The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8566. After the last display byte, the I2C-bus master issues a STOP condition (P).
R/W
acknowledge
by A0, A1 and A2
selected
PCF8566 only
acknowledge by
all addressed
PCF8566s
slave address
S
S
0 1 1 1 1 1 A 0 A C
0
1 byte
COMMAND
m ≥ 1 byte(s)
A
DISPLAY DATA
A
P
n > 0 byte(s)
update data pointers
and if necessary,
subaddress counter
mgg390
Fig 17. I2C-bus protocol
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Product data sheet
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.3 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All available
commands carry a continuation bit C in their most significant bit position as shown in
Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will
also represent a command. If this bit is reset, it indicates that the command byte is the last
in the transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined in Table 8.
MSB
LSB
C
REST OF OPCODE
msa833
(1) C = 0; last command.
(2) C = 1; commands continue.
Fig 18. General format of byte command
Table 8.
Definition of PCF8566 commands
Command
Opcode
Reference
Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mode set
C
1
0
LP
E
B
M1
M0
Section 8.3.1 defines LCD drive mode, LCD bias
configuration, display status and
power dissipation mode
Load data
pointer
C
0
0
P4
P3
P2
P1
P0
Section 8.3.2 data pointer to define one of 24
display RAM addresses
Device select
C
1
1
0
0
A2
A1
A0
Section 8.3.3 define one of eight hardware
subaddresses
Bank select
C
1
1
1
1
0
I
O
Section 8.3.4 bit I: defines input bank selection
(storage of arriving display data);
bit O: defines output bank selection
(retrieval of LCD display data)
Blink
C
1
1
1
0
A
BF1
BF0
Section 8.3.5 defines the blink frequency and blink
mode
8.3.1 Mode set command
Table 9.
LCD drive mode command bit description
LCD drive mode
Bit
Drive mode
Backplane
M1
M0
static
BP0
0
1
1:2
BP0, BP1
1
0
1:3
BP0, BP1. BP2
1
1
1:4
BP0, BP1. BP2, BP3
0
0
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 10.
LCD bias configuration command bit description
LCD bias
Bit B
1⁄
3
bias
0
1⁄
2
bias
1
Table 11.
Display status command bit description[1]
Display status
Bit E
disabled (blank)
0
enabled
1
[1]
The possibility to disable the display allows implementation of blinking under external control.
Table 12.
Power dissipation mode command bit description
Display status
Bit LP
normal mode
0
power saving mode
1
8.3.2 Load data pointer command
Table 13.
Load data pointer command bit description
Description
Bit
5 bit binary value, 0 to 23
P4
P3
P2
P1
P0
8.3.3 Device select command
Table 14.
Device select command bit description
Description
Bit
3 bit binary value, 0 to 7
A2
A1
A0
8.3.4 Bank select command
Table 15.
Bank select command[1]
Bank
Mode
Static
1:2 MUX
RAM bit 0
RAM bits 0 and 1
RAM bit 2
RAM bits 2 and 3
RAM bit 0
RAM bits 0 and 1
RAM bit 2
RAM bits 2 and 3
Bit
Value
I
0
Input bank
1
Output bank
[1]
0
1
The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
PCF8566_7
Product data sheet
O
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PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.3.5 Blink command
Table 16.
Blink frequency command bit description
Blink frequency
Bit
BF1
BF0
off
0
0
1
0
1
2
1
0
3
1
1
Table 17.
Blink mode command bit description
Blink mode
Bit A
Normal blinking
0
Alternate RAM bank blinking
1
8.4 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8566 and coordinates their effects. The controller
also loads display data into the display RAM as required by the storage order.
9. Internal circuitry
VLCD
VSS
SDA, SCL, SYNC,
CLK, OSC, A0 to A2,
SA0
VDD
BP0 to BP3,
S0 to S23
001aai456
Fig 19. Device protection diagram
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
26 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
10. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
VLCD
LCD supply voltage
VI
input voltage
on each of the pins SCL,
SDA, A0 to A2, OSC, CLK,
SYNC and SA0
VO
output voltage
on each of the pins S0 to S23
and BP0 to BP3
II
Max
Unit
−0.5
7.0
V
−0.5
7.0
V
−0.5
7.0
V
−0.5
7.0
V
input current
−20
+20
mA
IO
output current
−25
+25
mA
IDD
supply current
−50
+50
mA
ISS
ground supply
current
−50
+50
mA
IDD(LCD)
LCD supply current
−50
+50
mA
Ptot
total power
dissipation
-
400
mW
Po
output power
Tstg
storage
temperature
Vesd
electrostatic
discharge voltage
Ilu
[1]
[1]
per package
-
100
mW
[2]
−65
+150
°C
HBM
[3]
-
±2000
V
MM
[4]
-
±200
V
[5]
-
100
mA
latch-up current
[1]
Values with respect to VDD.
[2]
According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
[3]
Pass level; Human Body Model (HBM) according to JESD22-A114.
[4]
Pass level; Machine Model (MM), according to JESD22-A115.
[5]
Pass level; latch-up testing, according to JESD78.
PCF8566_7
Product data sheet
Min
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Rev. 07 — 25 February 2009
27 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 19. Static characteristics
VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
2.5
-
6.0
V
VLCD
LCD supply voltage
VDD − 6.0
-
VDD − 2.5
V
IDD
supply current:
IDD(lp)
low-power mode supply current
fclk = 200 kHz
[1]
-
30
90
µA
VDD = 3.5 V;
VLCD = 0 V;
fclk = 35 kHz;
A0 to A2 tied to
VSS
[1]
-
15
40
µA
Logic
Vi
input voltage
VSS − 0.5
-
VDD + 0.5
V
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
VDD
V
IOL
LOW-level output current
on pins CLK and
SYNC;
VOL = 1.0 V;
VDD = 5.0 V
−1
-
-
mA
IL
leakage current
on pins SA0, CLK,
OSC, A0 to A2;
VI = VDD or VSS
−1
-
+1
µA
IOH(CLK)
HIGH-level output current on pin
CLK
VOH = 4.0 V;
VDD = 5.0 V
-
-
+1
mA
Ipd
pull-down current
on pins OSC and
A0 to A2;
VI = 1.0 V;
VDD = 5.0 V
15
50
150
µA
RPU
pull-up resistance
on pin SYNC
VPOR
CI
I2C-bus;
15
25
60
kΩ
power-on reset voltage
[2]
-
1.3
2
V
input capacitance
[3]
-
-
7
pF
pins SDA and SCL
Vi
input voltage
VSS − 0.5
-
6
V
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
IL
leakage current
VI = VDD or VSS
−1
0
+1
µA
IOL
LOW-level output current
VOL = 0.4 V;
VDD = 5.0 V
−3
-
-
mA
CI
input capacitance
-
-
7
pF
tw(spike)
spike pulse width
-
-
100
ns
[3]
on bus
PCF8566_7
Product data sheet
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28 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 19. Static characteristics …continued
VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBP
voltage on pin BP
BP0 to BP3;
Cbpl = 35 nF
-
±20
-
mV
VS
voltage on pin S
S0 to S23;
Csgm = 5 nF
-
±20
-
mV
Zo
output impedance
on pin BP0 to BP3;
VLCD = VDD − 5 V
[4]
-
1
5
kΩ
on pin S0 to S23;
VLCD = VDD − 5 V
[4]
-
3
7
kΩ
LCD outputs
[1]
Outputs open; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2]
Resets all logic when VDD < VPOR.
[3]
Periodically sampled, not 100 % tested.
[4]
Outputs measured one at a time.
11.1 Typical supply current characteristics
mgg397
40
IDD
(µA)
IDD
(µA)
−40 °C
30
mgg398
24
−40 °C
16
+85 °C
+85 °C
20
8
10
0
0
0
2
4
VLCD = 0 V; fclk(ext) = 200 kHz.
Fig 20. Normal mode
6
VDD (V)
8
0
4
6
VDD (V)
8
VLCD = 0 V; fclk(ext) = 35 kHz.
Fig 21. Low power mode
PCF8566_7
Product data sheet
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29 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
11.2 Typical LCD output characteristics
mgg399
6
RBP
(kΩ)
mgg400
12
RS
(kΩ)
8
4
−40 °C
4
2
+25 °C
+85 °C
0
0
0
2
4
6
VDD (V)
8
VDD = 5 V; Tamb = −40 °C to +85 °C.
0
4
6
VDD (V)
8
VDD = 5 V.
Fig 22. Backplane output impedance BP0 to BP3 (RBP)
Fig 23. Segment output impedance S0 to S23 (RS)
PCF8566_7
Product data sheet
2
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Rev. 07 — 25 February 2009
30 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 20. Dynamic characteristics
VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. [1]
Symbol
Parameter
Conditions
clock frequency
normal mode;
VDD = 5 V
Min
Typ
Max
Unit
125
200
315
kHz
21
31
48
kHz
Clock
fclk
[2]
power saving mode;
VDD = 3.5 V
tclk(H)
HIGH-level clock time
1
-
-
µs
tclk(L)
LOW-level clock time
1
-
-
µs
tPD(SYNC_N)
SYNC propagation delay
-
-
400
ns
tSYNC_NL
SYNC LOW time
1
-
-
µs
tPD(drv)
driver propagation delay
-
-
30
µs
with test loads;
VLCD = VDD − 5 V
I2C-bus
tBUF
bus free time between a STOP and
START condition
4.7
-
-
µs
tHD;STA
hold time (repeated) START condition
4.0
-
-
µs
tLOW
low period of the SCL clock
4.7
-
-
µs
tHIGH
high period of the SCL clock
4.0
-
-
µs
tSU;STA
set-up time for a repeated START
condition
4.7
-
-
µs
tHD;DAT
data hold time
0
-
-
ns
tSU;DAT
data set-up time
250
-
-
ns
tr
rise time of both SDA and SCL signals
-
-
1.0
µs
tf
fall time of both SDA and SCL signals
-
-
300
ns
tSU;STO
set-up time for STOP condition
4.7
-
-
µs
[1]
All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD.
[2]
At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
31 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
1
fclk
tclk(H)
tclk(L)
0.7VDD
CLK
0.3VDD
0.7VDD
SYNC
0.3VDD
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3
S0 to S23
(VDD = 5 V)
0.5 V
tPD(drv)
mgg391
Fig 24. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 25. I2C-bus timing waveforms
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
32 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
Large display configurations of up to sixteen PCF8566s can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable
I2C-bus slave address (SA0).
Table 21.
Addressing cascaded PCF8566
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
2
1
Cascaded PCF8566s are synchronized. They can share the backplane signals from one
of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF8566s of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see
Figure 26).
PCF8566_7
Product data sheet
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33 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
VLCD
VDD
5
12
SDA 1
SCL 2
SYNC
17 to 40
24 segment drives
LCD PANEL
PCF8566
3
CLK
4
OSC 6
7
(up to 1536
elements)
13 to 16
8
A0
9
A1
10
A2
11
SA0 VSS
BP0 to BP3
(open-circuit)
VLCD
VDD
R≤
trise
2 Cbus
VDD
VLCD
5
HOST
MICROPROCESSOR/
MICROCONTROLLER
SDA
SCL
SYNC
CLK
OSC
12
1
17 to 40
2
24 segment drives
PCF8566
3
4
13 to 16
6
4 backplanes
BP0 to BP3
7
A0
8
A1
9
A2
10
11
mgg384
SA0 VSS
VSS
Fig 26. Cascaded PCF8566 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8566s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCF8566s with
differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8566 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8566 are shown in Figure 27.
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
34 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 27. Synchronization of the cascade for the various PCF8566 drive modes
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
35 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Single plane wiring of packaged PCF8566s is illustrated in Figure 28.
SDA
SCL
SYNC
CLK
VDD
VSS
VLCD
SDA
1
40
S23
1
40
S47
SCL
2
39
S22
2
39
S46
SYNC
3
38
S21
3
38
S45
CLK
4
37
S20
4
37
S44
VDD
5
36
S19
5
36
S43
OSC
6
35
S18
6
35
S42
A0
7
34
S17
7
34
S41
A1
8
33
S16
8
33
S40
S39
A2
9
32
S15
9
32
SA0
10
31
S14
10
31
S38
VSS
11
30
S13
11
30
S37
VLCD
12
29
S12
12
29
S36
BP0
13
28
S11
BP0
13
28
S35
BP2
14
27
S10
BP2
14
27
S34
BP1
15
26
S9
BP1
15
26
S33
BP3
16
25
S8
BP3
16
25
S32
S0
17
24
S7
S24
17
24
S31
S1
18
23
S6
S25
18
23
S30
S2
19
22
S5
S26
19
22
S29
S3
20
21
S4
S27
20
21
S28
PCF8566
open-circuit
S23
S0
S24
SEGMENTS
BACKPLANES
PCF8566
S47
mgg386
Fig 28. Single plane wiring of packaged PCF8566s
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
36 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Package outline
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4
1.70
1.14
0.53
0.38
0.36
0.23
52.5
51.5
inches
0.19
0.02
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.1
0.6
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT129-1
051G08
MO-015
SC-511-40
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 29. Package outline SOT129-1 (DIP40)
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
37 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A
X
c
y
HE
v M A
Z
40
21
Q
A2
A
(A 3)
A1
θ
pin 1 index
Lp
L
1
detail X
20
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.7
0.3
0.1
2.45
2.25
0.25
0.42
0.30
0.22
0.14
15.6
15.2
7.6
7.5
0.762
12.3
11.8
2.25
1.7
1.5
1.15
1.05
0.2
0.1
0.1
0.6
0.3
0.012 0.096
0.004 0.089
0.01
0.017 0.0087 0.61
0.012 0.0055 0.60
0.30
0.29
0.03
0.48
0.46
0.089
0.067
0.059
inches
0.11
0.045
0.024
0.008 0.004 0.004
0.041
0.012
θ
o
7
o
0
Notes
1. Plastic or metal protrusions of 0.4 mm (0.016 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
03-02-19
SOT158-1
Fig 30. Package outline SOT158-1 (VSO40)
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
38 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
15. Bare die outline
Wire bond die; 40 bonding pads; 2.5 x 2.91 x 0.381 mm
PCF8566U
D
e
A
24
23
22
21
PC8566-1
25
20
19
18
17
16
C1
15
e
26
14
F
27
13
28
12
29
x
30
0
11
0
31
y
E
10
32
9
33
8
C2
34
7
35
6
P4
P3
P2
36
37
38
39
40
1
2
3
4
5
P1
X
0
0.5
detail X
1 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
max
nom
min
A
D
E
e
P1(1)
P2(2)
P3(1)
P4(2)
0.406
0.381
0.356
2.5
2.91
0.548
0.200
0.018
0.12
0.106
0.12
0.106
Notes
1. Pad size
2. Passivation opening
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
08-06-19
08-09-03
PCF8566U
Fig 31. Bare die outline PCF8566U
PCF8566_7
Product data sheet
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Rev. 07 — 25 February 2009
39 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22. Bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 31).
Symbol
Pad
X (µm)
Y (µm)
Description
SDA
1
200
−1235
I2C-bus data input / output
SCL
2
400
−1235
I2C-bus clock input / output
SYNC
3
604
−1235
cascade synchronization input / output
CLK
4
856
−1235
external clock input / output
VDD
5
1062
−1235
supply voltage
OSC
6
1080
−1235
oscillator select
A0
7
1080
−825
I2C-bus subaddress input
A1
8
1080
−625
A2
9
1080
−425
SA0
10
1080
−225
I2C-bus slave address bit 0 input
VSS
11
1080
−25
logic ground
VLCD
12
1080
347
LCD supply voltage
BP0
13
1080
547
LCD backplane output
BP2
14
1080
747
BP1
15
1080
947
BP3
16
1074
1235
S0
17
874
1235
S1
18
674
1235
S2
19
474
1235
S3
20
274
1235
S4
21
−274
1235
S5
22
−474
1235
S6
23
−674
1235
S7
24
−874
1235
S8
25
−1074
1235
S9
26
−1080
765
S10
27
−1080
565
S11
28
−1080
365
S12
29
−1080
165
S13
30
−1080
−35
S14
31
−1080
−235
S15
32
−1080
−435
S16
33
−1080
−635
S17
34
−1080
−835
S18
35
−1080
−1035
S19
36
−1056
−1235
S20
37
−830
−1235
PCF8566_7
Product data sheet
LCD segment output
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
40 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22. Bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 31).
Symbol
Pad
X (µm)
Y (µm)
S21
38
−630
−1235
S22
39
−430
−1235
S23
40
−230
−1235
Description
REF
REF
C1
F
REF
C2
001aai300
Fig 32. Alignment marks
Table 23.
Alignment marks
Symbol
X (µm)
Y (µm)
C1
1100
1090
C2
325
−625
F
−790
700
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
Tray information for the PCF8566U is shown in Figure 33, Figure 35 and Table 24.
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
41 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
G
A
C
H
D
B
F
E
001aai237
marking code
Fig 33. Tray details
001aaj619
Fig 34. Tray alignment
Table 24.
Tray dimensions
Symbol
Description
Value
A
pocket pitch; x direction
4.43 mm
B
pocket pitch; y direction
4.43 mm
C
pocket width; x direction
3.04 mm
D
pocket width; y direction
3.04 mm
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
42 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 24.
Tray dimensions …continued
Symbol
Description
Value
E
tray width; x direction
50.8 mm
F
tray width; y direction
50.8 mm
G
cut corner to pocket 1,1 center
5.47 mm
H
cut corner to pocket 1,1 center
5.47 mm
x
number of pockets; x direction
10
y
number of pockets; y direction
10
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
43 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 35) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 25 and 26
Table 25.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 26.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 35.
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
44 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 35. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Abbreviations
Table 27.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DC
Direct Current
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LCD
Liquid Crystal Display
MM
Machine Model
MSL
Moisture Sensitivity Level
POR
Power-On Reset
RC
Resistance and Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SMD
Surface Mount Device
TTL
Transistor-Transistor Logic
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
45 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
20. Revision history
Table 28.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8566_7
20090225
Product data sheet
-
PCF8566_6
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Added U and TS type
Added tray information
Changed values in limiting values table from relative to absolute values
Changed letter symbols to NXP approved symbols
Rewritten chapter 7.3
PCF8566_6
19980504
Product specification
-
PCF8566_5
PCF8566_5
19970402
Product specification
-
PCF8566_4
PCF8566_4
19961203
Product specification
-
PCF8566_3
PCF8566_3
19961029
Product specification
-
PCF8566_2
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
46 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
21.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8566_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 25 February 2009
47 of 48
PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
23. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
8
8.1
8.1.1
8.1.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7
LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 7
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7
LCD drive mode waveforms . . . . . . . . . . . . . . 10
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 10
1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 11
1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 13
1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 14
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 15
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Display register . . . . . . . . . . . . . . . . . . . . . . . . 16
Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Sub-address counter . . . . . . . . . . . . . . . . . . . 19
Output bank selector. . . . . . . . . . . . . . . . . . . . 19
Input bank selector . . . . . . . . . . . . . . . . . . . . . 19
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Basic architecture . . . . . . . . . . . . . . . . . . . . . . 20
Characteristics of the I2C-bus . . . . . . . . . . . . . 20
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
START and STOP conditions . . . . . . . . . . . . . 21
System configuration . . . . . . . . . . . . . . . . . . . 21
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCF8566 I2C-bus controller . . . . . . . . . . . . . . 22
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22
Command decoder . . . . . . . . . . . . . . . . . . . . . 24
Mode set command . . . . . . . . . . . . . . . . . . . . 24
Load data pointer command . . . . . . . . . . . . . . 25
Device select command . . . . . . . . . . . . . . . . . 25
Bank select command . . . . . . . . . . . . . . . . . . 25
Blink command . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4
9
10
11
11.1
11.2
12
13
13.1
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
21
21.1
21.2
21.3
21.4
22
23
Display controller . . . . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Typical supply current characteristics. . . . . . .
Typical LCD output characteristics . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Cascaded operation . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
28
29
30
31
33
33
37
39
41
41
43
43
43
44
44
45
46
47
47
47
47
47
47
48
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 February 2009
Document identifier: PCF8566_7
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