Download Datasheet

STWBC
Digital controller for wireless battery charger (WBC) transmitters Qi
1.1.2 A11 certified, PMA compatible
Datasheet - production data
 Memory
– Flash and E2PROM with read-while-write
(RWW) and error correction code (ECC)
– Program memory: 32 KBytes Flash; data
retention 15 years at 85 °C after 10 kcycles
at 25 °C
– Data memory: 1 KByte true data E2PROM;
data retention:15 years at 85 °C after 100
kcycles at 85 °C
– RAM: 6 KBytes
VFQFPN32
Features
 Digital controller for wireless battery charger
transmitter
 Multiple Qi certified and PMA standard
compatible
 Reference design features
– 2 layers PCBs
– Active object detection
– Graphical user interface for application
monitoring
– Evaluation boards
 Operating temperature: -40 °C up to 105 °C
 Package: VFQFPN32
 Support for up to 5 W applications
– Mobile
– Wearable, sports gear, medical
– Remote controllers
Applications
 Native support to half-bridge and full bridge
topologies
 5 V supply voltage
 Certified Qi A11
– Evaluation board: STEVAL-ISB027V1
– Power rate: 5W
– Input: 5V
 Qi A13(a)
– Power rate: 5 W
– Input: 5 - 16 V, 12 V
 2 firmware options
– Turnkey solution for quick design
– APIs available for application
customization(a)
(a)
 Peripherals available via APIs
– ADC with 10 bit precision and 1 M input
impedance
– UART
– I2C master fast/slow speed rate
– GPIOs
 Wearable(a)
– Power rate: 2 W
– Input: 5 V
 PMA(a)
– power rate: 5 W
– input: 5 V
a. Contact local sale representative for further details:
see www.st.com.
February 2015
This is information on a product in full production.
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www.st.com
Contents
STWBC
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Introduction to wireless battery charging systems . . . . . . . . . . . . . . . . 8
3
Certified Qi A11 solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
Pinout for STWBC in Qi A11 configuration . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4
Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.5
Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.6
Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
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Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1
VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.2
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 18
5.3.3
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.4
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3.5
Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.6
Fast pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.7
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.8
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.9
10-bit SAR ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.1
Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.2
Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Contents
6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
Package design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables
STWBC
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
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Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
HSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLL internal source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Flash program memory/data E2PROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Current DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC accuracy characteristics at VDD/VDDA 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC accuracy characteristics at VDD/VDDA 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VFQFPN32 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Silicon product order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STWBC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
STWBC device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System view of a wireless charging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STWBC pinout view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
External capacitor CVOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VOH standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VOL standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VOH standard pad at 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VOL standard pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VOH fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VOL fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VOH fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VOL fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADC conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Description
1
STWBC
Description
The STWBC is the digital controller for wireless battery charger (WBC) transmitters (TX)
from STMicroelectronics, offering the most flexible and efficient solution for controlling
power transfer to a receiver (RX) in WBC-enabled applications such as phones, wearables,
and other battery powered devices that use electromagnetic induction for recharging.
As a member of the Qi Wireless Power Consortium and the PMA (Power Matters Alliance),
ST ensures full compatibility with these leading wireless charging protocols and holds
certification for the Qi 1.1.2 A11 standard.
The STWBC performs all the functions for transmitter control: thanks to the internal 96 MHz
clock and supporting both half-bridge and full bridge topologies, it is able to precisely control
the amount of transmitted power to match the requirements of the receiving unit in terms of
maximizing the efficiency of the power transfer.
The STWBC comes with firmware options to offer customers the ability to personalize their
end product without the need of external microcontrollers:

A turnkey Qi 1.1.2 A11 certified solution, fully interoperable with Qi enabled mobile
phones.

API (application programming interface) access to customize the underlying firmware,
for example modifying the behavior of the LEDs or GPIOs in response to the receiver
behavior and supporting I²C and UART communication within a network.
The STWBC Qi 1.1.2 A11 certified solution is available in the STMicroelectronics STEVALISB027V1 reference design, intended for all Qi compatible receivers such as in Qi enabled
mobile phones.
In the reference design the STWBC integrates the foreign object detection (FOD): the digital
feedback between TX and RX units allows the detection of metal objects close to the
receiver that could result in potential hazards, enabling the STWBC to stop power
transmission when such objects are detected.
The reference design is offered together with a complete ecosystem to support customers in
building their applications, including the Qi 1.1.2 A11 certified board (STEVAL-ISB027V1),
API libraries and documentation to develop software customizations, as well as
a comprehensive graphical user interface to monitor real-time performance and diagnostics.
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STWBC
Description
Figure 1. STWBC device architecture
Vbus Monitor
5V or 3.3V
V input
2x LED
Digital
controller
Topology
specific
Firmware
(including Qi
certification)
Digital Bridge
Controller
Temperature
Protection
Overcurrent
Protection
Signal & Protocol
Demodulator
ADC
GPIOs
FOD
UART
I2C
Customizable
STWBC
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Active Object
detector
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Introduction to wireless battery charging systems
2
STWBC
Introduction to wireless battery charging systems
Wireless battery charging systems replace the traditional power supply cable by means of
electromagnetic induction between a transmitting pad (TX) and a battery powered unit (RX),
such as a mobile phone or a battery pack.
The power transmitter unit is responsible for controlling the transmitting coil and generating
the correct amount of power requested by the receiver unit. The receiver unit continuously
feedbacks to the transmitter the correct power level requested by modulating the transmitter
carrier by means of a controlled resistive of capacitive insertion. Generating the correct
amount of power guarantees the highest level of end-to-end efficiency due to reduced
energy waste. Also, it helps maintaining a lower operational temperature.
The digital feedback is also used to detect foreign objects, i.e.: metal incorrectly exposed to
the coils. By stopping the application as soon as a foreign object is detected the risk of
damage is reduced.
Digital wireless battery transmitters can adapt the amount of energy transferred by the coil
by modulating the frequency, duty cycles or coil input voltage.
Figure 2. System view of a wireless charging system
Thanks to the internal STWBC 96 MHz clock, support for half-bridge and full bridge
topologies and protocol detection units, the STWBC can drive the power emitted by
a transmitting coil. The STWBC firmware sits on the top of the hardware to monitor and
control the correct wireless charging operations.
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3
Certified Qi A11 solution
Certified Qi A11 solution
The STWBC has been certified for Qi A11, thanks to the STEVAL-ISB027V1 reference
design. The certification is based on the Qi standard version 1.1.2 and supports FOD
(“Foreign Object Detection”).
The STEVAL-ISB027V1 reference design provides a complete kit which includes the
STWBC IC, firmware, layout, graphical interfaces and tools. The layout is based on a costeffective 2-layer PCB.
Firmware
The STWBC firmware is available in two separate software packages:

Turn-key: the firmware is distributed as a binary file.

API customizable: the firmware is designed as a library and external functions as well
as peripherals can be added by means of APIs.
The software APIs allow a great freedom of application customization. The STWBC and the
API library can be accessed by programming the internal controller via standard
programming tools such as the IAR™ Workbench® Studio.
Every STWBC wireless charging architecture is a reference design supported by firmware,
evaluation boards, application notes and PCB layouts notes.
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Pinout and pin description
4
STWBC
Pinout and pin description
The STWBC is a multifunction device that can support several wireless charging
architectures. The pinout is therefore application specific. Section 4.1 shows the pinout
used by the STWBC when the Qi A11 configuration is used.
4.1
Pinout for STWBC in Qi A11 configuration
Figure 3. STWBC pinout view
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4.2
Pinout and pin description
Pin description
Table 1. Pinout description
Pin no.
Pin name
Pin type
API firmware description
Bin firmware description
1
UART_RX(1)
DI
UART RX link
UART RX link
2
PWM_AUX/GPIO_2(1)
DO
PWM output or GPO
Not used, must not be connected
to any potential
3
I2C_SDA/DIGIN [4](1)
I2C_SDA / digital input 4
inactive (internal pull-up)
4
(1)
I2C_SCL / digital input 5
inactive (internal pull-up)
I2C_SCL/DIGIN [5]
5
DRIVEOUT [3]
DO
Output driver for low-side branch
right
Output driver for low-side branch
right
6
GPIO_0(1)
DO
Digital output for the green light
indicator / general purpose I/O
Digital output for the green light
indicator
7
GPIO_1(1)
DO
Digital output for the red light
indicator / general purpose I/O
Digital output for the red light
indicator
8
CPP_INT_3
AI
Symbol detector
Symbol detector
9
CPP_INT_2
AI
Vmain monitor
Vmain monitor
10
CPP_REF
AI
11
CPP_INT_1
AI
Symbol detector
Symbol detector
12
CPP_INT_0
AI
Symbol detector
Symbol detector
13
VDDA
PS
Analog power supply
Analog power supply
14
VSSA
PS
Analog ground
Analog ground
15
TANK_VOLTAGE
AI
LC tank voltage probe
LC tank voltage probe
16
VBRIDGE
Inactive (to be tied to GND)
Inactive (to be tied to GND)
17
SPARE_ADC(1)
Spare analog input (to be tied to
GND if not used)
Spare analog input (to be tied to
GND)
18
NTC_TEMP
AI
NTC temperature measurement.
NTC temperature measurement.
19
ISENSE
AI
LC tank current measurement
LC tank current measurement
20
VMAIN
AI
Vmain monitor
Vmain monitor
21
DRIVEOUT [0]
DO
Output driver for low-side branch
left
Output driver for low-side branch
left
22
DIGIN [0](1)
Digital input 0
Inactive (internal pull-up)
23
(1)
Digital input 1
Inactive (internal pull-up)
DIGIN [1]
External reference for CPP_INT_3 External reference for CPP_INT_3
(if not used, must be tied to GND) (if not used, must be tied to GND)
24
DRIVEOUT [1]
DO
Output driver for high-side branch
left
Output driver for high-side branch
left
25
DRIVEOUT [2]
DO
Output driver for high-side branch
right
Output driver for high-side branch
right
26
DIGIN [2](1)
Digital input 2
Inactive (internal pull-up)
27
SWIM
Debug interface
Debug interface
DIO
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Pinout and pin description
STWBC
Table 1. Pinout description (continued)
Pin no.
Pin name
Pin type
API firmware description
Bin firmware description
28
NRST
DI
Reset
Reset
29
VDD
PS
Digital and I/O power supply
Digital and I/O power supply
30
VSS
PS
Digital and I/O ground
Digital and I/O ground
31
VOUT
Supply
Internal LDO output
Internal LDO output
32
UART_TX(1)
DO
UART TX link
UART TX link
1. API configurable.
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Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS. VDDA and VDD must be
connected to the same voltage value. VSS and VSSA must be connected together with the
shortest wire loop.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA max. (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in Table 2, Table 3 and from Table 5 on page 17 to Table 17 on page 29
footnotes and are not tested in production.
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD and VDDA = 3.3 V.
They are given only as design guidelines and are not tested. Typical ADC accuracy values
are determined by characterization of a batch of samples from a standard diffusion lot over
the full temperature range.
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given as design guidelines only and are
not tested.
5.1.4
Typical current consumption
For typical current consumption measurements, VDD and VDDA are connected together as
shown in Figure 4.
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Electrical characteristics
STWBC
Figure 4. Supply current measurement conditions
5.1.5
Loading capacitors
The loading conditions used for the pin parameter measurement are shown in Figure 5:
Figure 5. Pin loading conditions
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5.1.6
Electrical characteristics
Pin output voltage
The input voltage measurement on a pin is described in Figure 6.
Figure 6. Pin input voltage
5.2
Absolute maximum ratings
Stresses above those listed as 'absolute maximum ratings' may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect the device reliability.
Table 2. Voltage characteristics
Symbol
Ratings
VDDX - VSSX Supply voltage(1)
VIN
Input voltage on any other
pin(2)
Min.
Max.
-0.3
6.5
VSS -0.3
VDD +0.3
VDD - VDDA Variation between different power pins
VSS - VSSA Variation between all the different ground
VESD
Electrostatic discharge voltage
50
pins(3)
50
Unit
V
mV
Refer to absolute maximum ratings
(electrical sensitivity) in
Section 5.4.1 on page 31.
1. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
power supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. VSS and VSSA signals must be interconnected together with a short wire loop.
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36
Electrical characteristics
STWBC
Table 3. Current characteristics
Symbol
IVDDX
IVSSX
IIO
Max.(1)
Ratings
Total current into VDDX power lines(2)
(2)
Total current out of VSSX power lines
Output current sunk by any I/Os and control pin
Unit
100
100
Ref. to Table 11
on page 21
mA
Output current source by any I/Os and control pin
IINJ(PIN)(3), (4)
IINJ(TOT)(3), (4), (5)
Injected current on any pin
±4
Sum of injected currents
±20
1. Data based on characterization results, not tested in production
2. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
power supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
4. Negative injection disturbs the analog performance of the device.
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 4. Thermal characteristics
Symbol
TSTG
TJ
16/36
Ratings
Storage temperature range
Maximum junction temperature
DocID027322 Rev 3
Max.
Unit
-65 to 150
ºC
150
STWBC
5.3
Electrical characteristics
Operating conditions
The device must be used in operating conditions that respect the parameters in Table 5. In
addition, a full account must be taken for all physical capacitor characteristics and
tolerances.
Table 5. General operating conditions
Symbol
Parameter
Conditions
Min.
VDD1, VDDA1 Operating voltages
VDD, VDDA
Nominal operating voltages
ESL of external
Unit
5.5(1)
3.3(1)
5(1)
V
470
3300
nF
0.05
0.2

1.8(2)
CVOUT: capacitance of external
capacitor(3)
ESR of external capacitor(2)
Max.
3(1)
Core digital power supply
VOUT
Typ.
at 1 MHz
capacitor(2)
JA(4)
FR4 multilayer PCB
VFQFPN32
TA
Ambient temperature
Pd = 100 mW
26
-40
°C/W
105
°C
1. The external power supply can be within range from 3 V up to 5.5 V.
2. Internal core power supply voltage.
3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,
DC bias and frequency.
4. To calculate PDmax (TA), use the formula PDmax = (TJmax - TA)/JA.
Table 6. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min.(1)
VDD rising
Typ.
Max.(2)
tTEMP
Reset release delay
3
VIT+
Power-on reset threshold
2.65
2.8
2.98
VIT-
Brownout reset threshold
2.58
2.73
2.88
Unit
ms
V
1. Guaranteed by design, not tested in production.
2. Power supply ramp must be monotone.
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36
Electrical characteristics
5.3.1
STWBC
VOUT external capacitor
The stabilization of the main regulator is achieved by connecting an external capacitor
CVOUT(b) to the VOUT pin. The CVOUT is specified in Section 5.3: Operating conditions.
Care should be taken to limit the series inductance to less than 15 nH.
Figure 7. External capacitor CVOUT
5.3.2
Internal clock sources and timing characteristics
HSI RC oscillator
The HSI RC oscillator parameters are specified under general operating conditions for VDD
and TA.
Table 7. HSI RC oscillator
Symbol
fHSI
ACCHSI
tSU(HSI)
Parameter
Conditions
Min.(1)
Frequency
Max.(1)
16
Accuracy of HSI oscillator
(factory calibrated)(1), (2)
-1%
+1%
VDD = 3.3 V
-40 ºC  TA  105 ºC
-4%
+4%
VDD = 5 V
-40 ºC  TA  105 ºC
-4%
+4%
HSI oscillator wakeup time
including calibration
2. Variation referred to fHSI nominal value.
b. ESR is the equivalent series resistance and ESL is the equivalent inductance.
DocID027322 Rev 3
1
Unit
MHz
VDD = 3.3 V
TA= 25 ºC
1. Data based on characterization results, not tested in production.
18/36
Typ.
%
µs
STWBC
Electrical characteristics
LSI RC oscillator
The LSI RC oscillator parameters are specified under general operating conditions for VDD
and TA.
Table 8. LSI RC oscillator
Symbol
fLSI
Parameter
Conditions
Min.(1)
Frequency
ACCLSI
Accuracy of LSI oscillator
tSU(LSI)
LSI oscillator wakeup time
3.3 V  VDD  5 V
-40 ºC  TA  105 ºC
Typ.
Max.(1) Unit
153.6
kHz
-10%
10%
7
%
µs
1. Guaranteed by design, not tested in production.
PLL internal source clock
Table 9. PLL internal source clock
Symbol
Parameter
fIN
Input frequency(2)
fOUT
Output frequency
tlock
PLL lock time
Conditions
3.3 V  VDD  5 V
-40 ºC  TA  105 ºC
Min
Typ.
Max.(1) Unit
16
MHz
96
200
µs
1. Data based on characterization results, not tested in production.
2. PLL maximum input frequency 16 MHz.
DocID027322 Rev 3
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36
Electrical characteristics
5.3.3
STWBC
Memory characteristics
Flash program and memory/data E2PROM memory
General conditions: TA = -40 °C to 105 °C.
Table 10. Flash program memory/data E2PROM memory
Min.(1) Typ.(1) Max.(1)
Unit
Standard programming time (including erase)
for byte/word/block (1 byte/4 bytes/128 bytes)
6
6.6
ms
Fast programming time for 1 block (128 bytes)
3
3.3
3
3.3
Symbol
tPROG
Parameter
Conditions
tERASE Erase time for 1 block (128 bytes)
Erase/write
NWE
tRET
IDDPRG
cycles((2)(program
memory)
TA = 25 °C
10 K
TA = 85 °C
100 K
TA = 105 °C
35 K
Data retention (program memory) after 10 K
erase/write cycles at TA= 25 °C
TRET = 85 °C
15
Data retention (program memory) after 10 K
erase/write cycles at TA= 25 °C
TRET = 105 °C
11
Data retention (data memory) after 100 K
erase/write cycles at TA= 85 °C
TRET = 85 °C
15
Data retention (data memory) after 35 K
erase/write cycles at TA= 105 °C
TRET = 105 °C
6
Supply current during program and erase
cycles
-40 ºC  TA  105 ºC
Erase/write cycles(2)(data memory)
ms
Cycles
Years
2
mA
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
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DocID027322 Rev 3
STWBC
5.3.4
Electrical characteristics
I/O port pin characteristics
The I/O port pin parameters are specified under general operating conditions for VDD and TA
unless otherwise specified. Unused input pins should not be left floating.
Table 11. Voltage DC characteristics
Symbol
VIL
VIH
Min.(1)
Description
Input low voltage
Input high voltage
(2)
VOL2
Output low voltage at 5 V(3)
VOL3
Output low voltage high sink at 3.3 V / 5 V(2),(5), (6)
VOH2
Output high voltage at 5
0.3 * VDD
0.7 * VDD
VDD
Unit
0.4(4)
Output low voltage at 3.3 V
Output high voltage at 3.3
Max.(1)
-0.3
(3)
VOL1
VOH1
Typ.
0.5
V(3)
0.6(4)
VDD -
V(3)
V
0.4(4)
VDD - 0.5
VOH3
Output high voltage high sink at 3.3 V / 5
HVS
Hysteresis input voltage(7)
RPU
Pull-up resistor
V(2), (5), (6)
VDD - 0.6(4)
0.1 * VDD
30
45
60
k
1. Data based on characterization result, not tested in production.
2. All signals are not 5 V tolerant (input signals can't be exceeded VDDX (VDDX = VDD, VDDA).
3. Parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX.
4. Electrical threshold voltage not yet characterized at -40 ºC.
5. Parameter applicable to signal: SWIM.
6. Parameter applicable to signal: DIGIN [0].
7. Applicable to any digital inputs.
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36
Electrical characteristics
STWBC
Table 12. Current DC characteristics
Symbol
IOL1
IOL2
Description
Min.
Standard output low level current at 3.3 V and VOL1(2)
Standard output low level current at 5 V and VOL 2
IOLhs2
High sink output low level current at 5 V and VOL(3),(4)
,
(2)
IOH1
Standard output high level current at 3.3 V and VOH1
IOH2
Standard output high level current at 5 V and VOLH2(2)
(3), (4)
IOHhs1
High sink output low level current at 3.3 V and VOH3
IOHhs2
High sink output low level current at 5 V and VOH3(3), (4)
I_lnj
Input leakage current digital - analog VSS  VIN  VDD
Injection
(5)
current(6), (7)
5
7.75
1.5
pins)(6)
5
7.75
±1
± 20
1. Data based on characterization result, not tested in production.
2. Parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX.
3. Parameter applicable to signal: SWIM.
4. Parameter applicable to signal: DIGIN [0].
5. Applicable to any digital inputs.
6. Maximum value must never be exceeded.
7. Negative injection current on the ADCIN [7:0] signals (product depending) => SPARE_ADC signals have to avoid since
impact the ADC conversion accuracy.
22/36
DocID027322 Rev 3
mA
3
±4
Total injection current (sum of all I/O and control
Unit
3
(3) (4)
High sink output low level current at 3.3 V and VOL3
I_lnj
Max.(1)
1.5
(2)
IOLhs1
ILKg
Typ.
A
mA
STWBC
5.3.5
Electrical characteristics
Typical output level curves
This section shows the typical output voltage level curves measured on a single output pin
for the two-pad family present in the STWBC device.
Standard pad
This pad is associated to the following signals: DIGIN [0:1], SWIM and GPIO_[0:2] when
available.
Figure 8. VOH standard pad at 3.3 V
Figure 9. VOL standard pad at 3.3 V
DocID027322 Rev 3
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36
Electrical characteristics
STWBC
Figure 10. VOH standard pad at 5 V
Figure 11. VOL standard pad at 5 V
24/36
DocID027322 Rev 3
STWBC
5.3.6
Electrical characteristics
Fast pad
This pad is associated to the DRIVEOUT[0:3], PWM_AUX signals if the external pin is
available.
Figure 12. VOH fast pad at 3.3 V
Figure 13. VOL fast pad at 3.3 V
DocID027322 Rev 3
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36
Electrical characteristics
STWBC
Figure 14. VOH fast pad at 5 V
Figure 15. VOL fast pad at 5 V
26/36
DocID027322 Rev 3
STWBC
5.3.7
Electrical characteristics
Reset pin characteristics
The reset pin parameters are specified under general operating conditions for VDD and TA
unless otherwise specified.
Table 13. NRST pin characteristics
Symbol
Parameter
Conditions
NRST input low level voltage(1)
VIL(NRST)
(1)
VIH(NRST)
NRST input high level voltage
NRST output low level voltage
VOL(NRST)
NRST pull-up resistor
tIFP(NRST)
NRST input filtered pulse(3)
NRST not input filtered
Max.(1)
-0.3
0.3 x VDD
0.7 x VDD
VDD + 0.3
40
60
75
pulse(3)
Unit
V
0.5
30
500
NRST output filtered pulse(3)
tOP(NRST)
Typ.
IOL = 2 mA
(2)
RPU(NRST)
tINFP(NRST)
(1)
Min.(1)
15
k
ns
µs
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
5.3.8
I2C interface characteristics
Table 14. I2C interface characteristics
Standard mode
Symbol
Parameter
Min.(1)
Max.(1)
Fast mode
Min.(1)
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
SDA data hold time
0(2)
0(2)
th(SDA)
Max.(1)
Unit
µs
900(2)
tr(SDA) tr(SCL)
SDA and SCL rise time (VDD = 3.3 to 5 V)(3)
1000
300
tf(SDA) tf(SCL)
SDA and SCL fall time (VDD = 3.3 to 5 V)(3)
300
300
ns
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
µs
STOP to START condition time (bus free)
4.7
1.3
µs
tw(STO:STA)
Cb
Capacitive load for each bus line(4)
50
µs
50
pF
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time
3. I2C multifunction signals require the high sink pad configuration and the interconnection of 1 K pull-up resistances.
4. 50 pF is the maximum load capacitance value to meet the I2C std timing specifications.
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36
Electrical characteristics
5.3.9
STWBC
10-bit SAR ADC characteristics
The 10-bit SAR ADC oscillator parameters are specified under general operating conditions
for VDDA and TA unless otherwise specified.
Table 15. ADC characteristics
Symbol
N
RADCIN
Parameter
Conditions
Min.
Resolution
Typ.
Max.
Unit
10
ADC input impedance
1
VIN1
Conversion voltage range
for gain x1
0
Vref
ADC main reference
voltage(3)
bit
M
1.25(1), (2)
1.250
V
1. Maximum input analog voltage cannot exceed VDDA.
2. Exceeding the maximum voltage on the SPARE_ADC signals for the related conversion scale must be
avoided since the ADC conversion accuracy can be impacted.
3. ADC reference voltage at TA = 25 °C.
ADC accuracy characteristics at VDD/VDDA 3.3 V
Table 16. ADC accuracy characteristics at VDD/VDDA 3.3 V
Min.(2)
Max.(2)
Offset + gain
error(6), (7)
-8.5
9.3
EO+G
Offset + gain
error(6), (8)
-11
11
EO+G
Offset + gain error(6), (9)
-14.3
11.3
Symbol
|ET|
Parameter
Total unadjusted error(3), (4), (5)
error(3), (4), (5)
|EO|
Offset
|EG|
Gain error(3), (4), (5), (6)
EO+G
|ED|
|EL|
Differential linearity error(1), (2), (3)
Integral linearity
error(3), (4), (5)
Typ.(1)
Unit
2.8
0.3
0.4
LSB
0.5
1.4
1. Temperature operating: TA = 25 °C.
2. Data based on characterization results, not tested in production.
3. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins
should be avoided as this reduces the accuracy of the conversion being performed on another analog
input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may
potentially inject the negative current. Any positive injection current within the limits specified for
IINJ(PIN)and INJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC
accuracy parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2.
4. Results in manufacturing test mode.
5. Data aligned with trimming voltage parameters.
6. Gain error evaluation with the two point method.
7. Temperature operating range: 0 ºC  TA  85 ºC.
8. Temperature operating range: -25 ºC  TA  105 ºC.
9. Temperature operating range: -40 ºC  TA  105 ºC.
28/36
DocID027322 Rev 3
STWBC
Electrical characteristics
ADC accuracy characteristics at VDD/VDDA 5 V
Table 17. ADC accuracy characteristics at VDD/VDDA 5 V
Symbol
|ET|
|EO|
|EG|
Parameter
Total unadjusted error(3) (4), (5)
Typ.(1)
0.5
(3) (4) (5) (6)
0.4
Gain error ,
,
,
Max.(2)
,
(6) (7)
EO+G
Offset + gain error ,
-8.3
8.9
EO+G
Offset + gain error(6), (8)
-10.9
10.9
EO+G
Offset + gain error(6), (9)
-13.8
10.9
|ED|
|EL|
Differential linearity
Integral linearity
Unit
TBD
(3) (4) (5)
Offset error ,
Min.(2)
error(1), (2), (3)
error(3), (4), (5)
LSB
0.8
2.0
1. Temperature operating: TA= 25 °C.
2. Data based on characterization results, not tested in production.
3. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins
should be avoided as this reduces the accuracy of the conversion being performed on another analog
input. It is recommended a Schottky diode (pin to ground) to be to added to standard analog pins which
may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN)
and IINJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy
parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2.
4. Results in manufacturing test mode.
5. Data aligned with trimming voltage parameters.
6. Gain error evaluation with two point method.
7. Temperature operating range: 0 ºC  TA  85 ºC.
8. Temperature operating range: -25 ºC  TA  105 ºC.
9. Temperature operating range: -40 ºC  TA  105 ºC. 11.
DocID027322 Rev 3
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36
Electrical characteristics
STWBC
ADC conversion accuracy
Figure 16. ADC conversion accuracy
ADC accuracy parameter definitions:
30/36

ET = total unadjusted error: Maximum deviation between the actual and the ideal
transfer curves.

EO = offset error: deviation between the first actual transition and the first ideal one.

EOG = offset + gain error (1-point gain): deviation between the last ideal transition and
the last actual one.

EG = gain error (2-point gain): defined so that EOG = EO + EG (parameter correlated to
the deviation of the characteristic slope).

ED = differential linearity error: maximum deviation between actual steps and the ideal
one.

EL = integral linearity error: maximum deviation between any actual transition and the
end point correlation line.
DocID027322 Rev 3
STWBC
Electrical characteristics
5.4
EMC characteristics
5.4.1
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts * (n + 1) supply pin).
Table 18. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Maximum
value
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = 25 °C, conforming to
JEDEC/JESD22-A114E
2000
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming to
ANSI/ESD STM 5.3.1 ESDA
500
VESD(MM)
Electrostatic discharge voltage
(machine model)
TA = 25 °C, conforming to
JEDEC/JESD-A115-A
200
Unit
V
Data based on characterization results, not tested in production.
5.4.2
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
A supply overvoltage (applied to each power supply pin) and a current injection (applied to
THE each input, output and configurable I/O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up standard.
Table 19. Electrical sensitivity
Symbol
Parameter
Conditions
Level
LU
Static latch-up class
TA = 105 °C
A
DocID027322 Rev 3
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36
Thermal characteristics
6
STWBC
Thermal characteristics
The STWBC functionality cannot be guaranteed when the device operating exceeds the
maximum chip junction temperature (TJmax).
TJmax, in °C, may be calculated using equation:
TJmax = TAmax + (PDmax x JA)
where:
TAmax is the maximum ambient temperature in °C
JA is the package junction to ambient thermal resistance in °C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip internal
power.
PI/Omax represents the maximum power dissipation on output pins where:
PI/Omax =  (VOL * IOL) + [(VDD - VOH) * IOH],
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at the low and high level.
Table 20. Package thermal characteristics
Symbol
JA
Parameter
VFQFPN32 - thermal resistance junction to
ambient(1)
Value
Unit
26
°C/W
1. Thermal resistance is based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
32/36
DocID027322 Rev 3
STWBC
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1
Package design overview
Figure 17. VFQFPN32 package outline
DocID027322 Rev 3
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36
Package information
7.2
STWBC
Package mechanical data
Table 21. VFQFPN32 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
A3
0.20
b
0.18
0.25
0.30
D
4.85
5.00
5.15
D2
3.40
3.45
3.50
E
4.85
5.00
5.15
E2
3.40
3.45
3.50
0.50
0.55
0.40
0.50
e
L
0.30
ddd
Note:
0.08
1. VFQFPN stands for “Thermally Enhanced Very thin Fine pitch Quad Flat Package No
lead”.
2. Very thin profile: 0.80 < A ≤ 1.00 mm.
3. Details of the terminal 1 are optional but must be located on the top surface of the
package by using either a mold or marked features.
4. Package outline exclusive of any mold flashes dimensions and metal burrs.
34/36
DocID027322 Rev 3
STWBC
8
Order codes
Order codes
Table 22. Silicon product order code
Order code
Package
STWBC
Tube
VFQFPN32
STWBCTR
9
Packaging
Tape and reel
Revision history
Table 23. Document revision history
Date
Revision
18-Dec-2014
1
Initial release.
2
Updated main title on page 1.
Updated Section : Applications on page 1 (added
“certified” to Qi A11).
Added Section 3: Certified Qi A11 solution on page 9.
Updated Figure 3: STWBC pinout view on page 10
(updated title, replaced by new figure).
Updated Table 1: Pinout description on page 11
(replaced by new table).
Added Section 5: Electrical characteristics on page 13
and Section 6: Thermal characteristics on page 32.
Minor modifications throughout document.
3
Updated main title on page 1.
Updated Section : Features on page 1 (minor
modifications).
Updated Section 1: Description on page 6 (replaced by
new Description).
Added Section 2: Introduction to wireless battery
charging systems on page 8 (added title and Description
from rev. 2, updated title of Figure 2).
Removed Section “2 STWBC system architecture” from
page 7 (Figure 2 on page 8 moved to Section 1:
Description).
Updated Section 3: Certified Qi A11 solution on page 9
(renumbered headings).
Minor modifications throughout document.
23-Feb-2015
26-Feb-2015
Changes
DocID027322 Rev 3
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36
STWBC
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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