Data Sheet

CBTV24DD12
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2
applications
Rev. 3.2 — 19 April 2016
Product data sheet
1. General description
CBTV24DD12 is designed for 1.8 V/2.5 V/3.3 V supply voltage operation and it supports
Pseudo Open Drain (POD), SSTL_12, SSTL_15 or SSTL_18 signaling and CMOS select
input levels. This device is designed for operation in DDR4, DDR3 or DDR2 memory bus
systems, with speeds up to 3200 MT/s.
The CBTV24DD12 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 12-bit wide
bus. Each 12-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. Each port is non-directional due to the use of FET switches, allowing a
multitude of applications requiring high-bandwidth switching or multiplexing.
The selection of the port is by a simple CMOS input (SELect). Another CMOS input
(ENable) is available to allow all ports to be disconnected. The SEL0, SEL1 and EN input
signals are designed to operate transparently as CMOS input level signals up to 3.3 V.
CBTV24DD12 uses NXP’s proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss, return loss, and very low propagation delay, allowing
use in many applications requiring switching or multiplexing of high-speed signals. It is
available in a 3.0 mm  8.0 mm TFBGA48 package with 0.65 mm ball pitch, for optimal
size versus board layout density considerations. It is characterized for operation from
10 C to +85 C.
2. Features and benefits
2.1 Topology





12-bit bus width
1 : 2 switch/MUX topology
Bidirectional operation
Simple CMOS select pins (SEL0, SEL1)
Simple CMOS enable pin (EN)
2.2 Performance






3200 MT/s throughput
7.4 GHz bandwidth (for both single-ended and differential signals)
Low ON insertion loss
Low return loss
Low crosstalk
High OFF isolation
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
 POD_12, SSTL_12, SSTL_15 or SSTL_18 signaling
 Low RON (8  typical)
 Low RON (<1 )
2.3 General attributes





1.8 V/2.5 V/3.3 V supply voltage operation
Very low supply current (600 A typical)
Back current protection on all the I/O pins of these switches
ESD robustness exceeds 2.5 kV HBM, 1 kV CDM
Available in TFBGA48 package, 3.0 mm  8.0 mm  1 mm size, 0.65 mm pitch,
Pb-free/Dark Green
3. Applications




DDR4/DDR3/DDR2 memory bus systems
NVDIMM module
Systems requiring high-speed multiplexing
Flash memory array subsystem
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
CBTV24DD12ET
V2412
TFBGA48
plastic low profile fine-pitch ball grid array package; 48
balls; body 3  8  1 mm; 0.65 mm pitch
SOT1365-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum Temperature
order
quantity
CBTV24DD12ET
CBTV24DD12ETY
TFBGA48
Reel 13” Q1/T1
*Standard mark SMD dry pack
4500
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
Tamb = 10 C to +85 C
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
5. Functional diagram
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
SEL1
SEL2
CONTROL LOGIC
EN
aaa-020030
Fig 1.
CBTV24DD12
Product data sheet
Functional diagram
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
6. Pinning information
6.1 Pinning
CBTV24DD12ET
ball A1
index area
1
2
3
4
1
2
3
4
A
A0
SEL0
B0
C0
C
B
A1
GND
B1
C1
D
C
A2
VDD
B2
C2
D
A3
GND
B3
C3
E
A4
GND
B4
C4
F
A5
GND
B5
C5
G
A6
VDD
B6
C6
H
A7
EN
B7
C7
J
J
A8
GND
B8
C8
K
K
A9
VDD
B9
C9
L
L
A10
GND
B10
C10
M
M
A11
SEL1
B11
C11
A
B
E
F
G
H
Transparent top view
002aah572
Transparent top view
Fig 2.
002aah573
Pin configuration for TFBGA48
Fig 3.
Ball mapping for TFBGA48
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
A[0:11]
A1, B1, C1,
D1, E1, F1,
G1, H1, J1,
K1, L1, M1
high-speed I/O
12-bit wide input/output, port A
B[0:11]
A3, B3, C3,
D3, E3, F3,
G3, H3, J3,
K3, L3, M3
high-speed I/O
12-bit wide input/output, port B
C[0:11]
A4, B4, C4,
D4, E4, F4,
G4, H4, J4,
K4, L4, M4
high-speed I/O
12-bit wide input/output, port C
SEL0,
SEL1
A2,
M2
CMOS input
CMOS input signal.
When SEL0 = LOW, port A[0,1,4,5,8,9] and
port B[0,1,4,5,8,9] are mutually connected.
When SEL0 = HIGH, port A[0,1,4,5,8,9] and
port C[0,1,4,5,8,9] are mutually connected.
When SEL1 = LOW, port A[2,3,6,7,10,11] and
port B[2,3,6,7,10,11] are mutually connected.
When SEL1 = HIGH, port A[2,3,6,7,10,11] and
port C[2,3,6,7,10,11] are mutually connected.
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
EN
H2
CMOS input
CMOS input signal.
When HIGH, all ports are mutually isolated.
When LOW, connection is set using the SEL[0:1]
input signals.
CBTV24DD12
Product data sheet
VDD
C2, G2, K2
supply
Must be connected to supply voltage power plane.
GND
B2, D2, E2,
F2, J2, L2
ground
Must be connected to GND plane for both electrical
grounding and thermal relief.
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
7. Functional description
Refer to Figure 1 “Functional diagram”.
CBTV24DD12 supports 1.8 V, 2.5 V or 3.3 V power supply voltages. All signal paths are
implemented using high-bandwidth pass-gate technology and are non-directional. No
clock or reset signal is needed for the multiplexer to function. The switch position for the
channels is selected using the select signals (SEL0, SEL1). The detailed operation is
described in Section 7.1.
7.1 Function selection
The internal multiplexer switch position is controlled by three logic inputs, SEL0, SEL1
and EN, as described in Table 4.
When a channel is not being used, Port B and Port C of this channel should be tied to
ground. For example, if Channel 2 is not used, B2 and C2 should be tied to ground and A2
should be left open.
Table 4.
Function selection
X = don’t care.
Inputs
EN
CBTV24DD12
Product data sheet
Switch position
SELx
AB
AC
HIGH
X
OFF (isolated)
OFF (isolated)
LOW
SEL0 = LOW
A[0,1,4,5,8,9]  B[0,1,4,5,8,9]
OFF (isolated)
LOW
SEL0 = HIGH
OFF (isolated)
A[0,1,4,5,8,9]  C[0,1,4,5,8,9]
LOW
SEL1 = LOW
A[2,3,6,7,10,11]  B[2,3,6,7,10,11]
OFF (isolated)
LOW
SEL1 = HIGH
OFF (isolated)
A[2,3,6,7,10,11]  C[2,3,6,7,10,11]
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
Tstg
storage temperature
VESD
electrostatic discharge voltage
Min
Max
Unit
0.3
+4.4
V
65
+150
C
HBM
[1]
-
2500
V
CDM
[2]
-
1000
V
[1]
Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011), ESDA/JEDEC Joint standard
for ESD sensitivity testing. Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.; JEDEC Solid
State Technology Association, Arlington, VA, USA.
[2]
Charged-Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008), standard for ESD sensitivity
testing, Charged-Device Model - Component level; JEDEC Solid State Technology Association, Arlington, VA, USA.
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Tamb
ambient temperature
Conditions
Min
Typ
Max
Unit
1.62
-
3.63
V
channel inputs/outputs
0.3
-
+1.8
V
control inputs
0.3
-
+3.6
V
operating in free air
10
-
+85
C
Unit
10. Static characteristics
Table 7.
Static characteristics
Typical VDD; Tamb = 10 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
IDD
supply current
EN = LOW
-
0.6
1.3
mA
EN = HIGH
-
-
45
A
High-speed I/O; A, B and C ports;
VI = 1.8 V
-
-
5
A
Control pins; SEL0, SEL1 and EN;
VI = 3.6 V
-
-
10
A
HIGH-level input current
IIH
IIL
LOW-level input current
VI = GND
-
-
5
A
VIH
HIGH-level input voltage
SEL0, SEL1, EN pins
1.4
-
-
V
VIL
LOW-level input voltage
SEL0, SEL1, EN pins
0.5
-
+0.4
V
VIK
input clamping voltage
voltage on high-speed channel pins;
II = 18 mA
-
-
1.2
V
[1]
Typical values are at VDD = 2.5 V; Tamb = 25 C, and maximum loading.
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
11. Dynamic characteristics
Table 8.
Dynamic characteristics for CBTV24DD12
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
supply voltage valid or EN going HIGH to
channel specified operating characteristics
-
90
300
s
trcfg
reconfiguration time
SEL[0:1] state change to channel specified
operating characteristics; measuring from
50 % of SELx to 90 % of channel output
-
-
30
ns
il
insertion loss
channel is on; 0 Hz  f  4 GHz
-
1.5
-
dB
[1]
channel is on; f = 7 GHz
-
3.0
-
dB
channel is off; 0 Hz  f  4 GHz
-
20
-
dB
RLin
input return loss
channel is on; 0 Hz  f  4 GHz
-
16
-
dB
ct
crosstalk attenuation
adjacent channels are on; 0 Hz  f  4 GHz
-
24
-
dB
B
bandwidth
3.0 dB intercept (for both single-ended
and differential signals)
-
7.4
-
GHz
tPD
propagation delay
from A port to B port or C port or vice versa
-
65
-
ps
tsk
skew time
from any output to any output
-
3
6
ps
RON
ON resistance
from any input to any output
5
6.5
9

RON(flat)
ON resistance (flatness)
[2]
-
1.5
-

ON resistance mismatch
between channels
[3][4]
-
0.4
1

RON
[1]
Smooth transition without glitch under DDR termination schemes.
[2]
RON(flat) is the difference of the RON in a given channel across all VI voltage ranges.
[3]
RON is the difference of RON from one port to any other ports when the same VI voltage is applied to all channels.
[4]
Guaranteed by design.
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
12. Package outline
SOT1365-1
TFBGA48: plastic low profile fine-pitch ball grid array package; 48 balls
A
B
D
ball A1
index area
E
A2
A
A1
detail X
e1
C A B
C
Øv
Øw
b
e
C
y
y1 C
1/2 e
M
L
K
J
e
H
G
e2
F
E
1/2 e
D
C
B
A
1 2 3 4
ball A1
index area
X
0
5 mm
scale
Dimensions
Unit
mm
A
A1
A2
b
max 1.05 0.35 0.73 0.45
nom 0.98 0.30 0.68 0.40
min 0.88 0.25 0.63 0.35
D
E
e
3.1
3.0
2.9
8.1
8.0
7.9
e1
e2
v
w
y
0.65 1.95 7.15 0.15 0.05 0.08
y1
0.1
sot1365-1_po
References
Outline
version
IEC
JEDEC
JEITA
SOT1365-1
---
---
---
Fig 4.
European
projection
Issue date
14-01-03
14-08-12
Package outline TFBGA48 (SOT1365-1)
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
13. Packing information
4.00 ± 0.10 (P0)
0.30 ± 0.05
(T)
2.00 ± 0.10 (P2)
Ø 1.50
+ 0.10
(D )
− 0.00 0
1.75 ± 0.10 (E1)
7.50 ± 0.10
(F)
8.30 ± 0.10
(B0)
16.00 ± 0.30
(W)
8.00 ± 0.10
(P1)
3.30 ± 0.10
(A0)
1.20 ± 0.05
(K0)
Fig 5.
Ø 1.60 ± 0.10 (D1)
Notes:
1. Dimensions in mm.
2. 10 sprocket hole pitches cumulative tolerance ±0.20 mm.
3. Camber not to exceed 1 mm in 250 mm.
4. Pocket position relative to sprocket hole measured as true position
of pocket, not pocket hole.
aaa-011237
Carrier tape
pin 1
aaa-006540
Pin 1 (ball A1) is in Quadrant 1.
Fig 6.
CBTV24DD12
Product data sheet
Product orientation in carrier tape
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
2.2
Ø 330 ± 0.5
+ 1.5
17.0 − 0
Ø 318
Ø 97.0 ± 1.0
2.0 ± 0.5
+ 0.5
Ø 13.0 − 0.2
10.6
R1
aaa-012172
Fig 7.
13-inch reel
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
15. Soldering: PCB footprints
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI7)%*$SDFNDJH
627
+[
3
3
+\
VHHGHWDLO;
UHFRPPHQGVWHQFLOWKLFNQHVVPP
VROGHUODQG6/
VROGHUSDVWHGHSRVLW63
VROGHUODQGSOXVVROGHUSDVWH
VROGHUUHVLVWRSHQLQJ65
RFFXSLHGDUHD
6/ 63
65
'LPHQVLRQVLQPP
3
6/
63
65
+[
+\
Fig 9.
GHWDLO;
,VVXHGDWH
VRWBIU
PCB footprint for SOT1365-1 (TFBGA48); reflow soldering
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
16. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DDR2
Double Data Rate 2
DDR3
Double Data Rate 3
DDR4
Double Data Rate 4
DRAM
Dynamic Random Access Memory
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I/O
Input/Output
MT/s
Mega Transfers per second
NVDIMM
Non-Volatile Dual In-line Memory Module
POD
Pseudo Open Drain
SSTL_12
Stub Series Terminated Logic for 1.2 V
SSTL_15
Stub Series Terminated Logic for 1.5 V
SSTL_18
Stub Series Terminated Logic for 1.8 V
17. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTV24DD12 v.3.2
20160419
Product data sheet
-
CBTV24DD12 v.3.1
Modifications:
CBTV24DD12 v.3.1
Modifications:
CBTV24DD12 v.3
Modifications:
•
Section 2.3 “General attributes”: Added “Back current protection...”
20151020
•
Product data sheet
-
CBTV24DD12 v.3
Updated Figure 1 “Functional diagram”
20150820
Product data sheet
-
CBTV24DD12 v.2
•
Table 7 “Static characteristics”: Changed max value for IIH control pins from “5”
to “10”
•
Table 8 “Dynamic characteristics for CBTV24DD12”: Updated conditions for
trcfg; changed min/typ/max values for RON
•
Changed document status from “Company Confidential” to “Company Public”
CBTV24DD12 v.2
20140828
Product data sheet
-
CBTV24DD12 v.1
CBTV24DD12 v.1
20140814
Product data sheet
-
-
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
CBTV24DD12
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTV24DD12
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
18 of 19
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
20. Contents
1
2
2.1
2.2
2.3
3
4
4.1
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General attributes . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
Function selection. . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing information . . . . . . . . . . . . . . . . . . . . 10
Soldering of SMD packages . . . . . . . . . . . . . . 12
Introduction to soldering . . . . . . . . . . . . . . . . . 12
Wave and reflow soldering . . . . . . . . . . . . . . . 12
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13
Soldering: PCB footprints. . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 April 2016
Document identifier: CBTV24DD12