Data Sheet

PCF2120
Quartz oscillator
Rev. 01 — 5 February 2008
Product data sheet
1. General description
The PCF2120 is a CMOS quartz oscillator optimized for low power consumption.
The 32 kHz output signal is gated using an enable signal.
2. Features
n
n
n
n
n
n
Clock operating voltage: 1.5 V to 5.5 V
Low backup current: typical 0.85 µA at VDD = 3.0 V and Tamb = 25 °C
32.768 kHz output for peripheral devices
Two integrated oscillator capacitors
Push-pull output
Internal power-on reset
3. Applications
n Portable instruments
n Industrial products
n Battery powered products
4. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
VDD
supply voltage
IDD
supply current
Conditions
Min
Typ
Max
Unit
1.5
-
5.5
V
VDD = 2.0 V; Tamb = 25 °C
-
210
450
nA
VDD = 3.0 V;
Tamb = −40 °C to +85 °C
-
265
650
nA
VDD = 2.0 V; Tamb = 25 °C
-
615
900
nA
VDD = 3.0 V;
Tamb = −40 °C to +85 °C
-
875
1100
nA
−65
-
+150
°C
[1]
clock output disabled
clock output enabled at 32 kHz
Tstg
[1]
storage temperature
For reliable oscillator start-up at power-up: VDD > VDD(min) + 0.3 V.
PCF2120
NXP Semiconductors
Quartz oscillator
5. Ordering information
Table 2.
Ordering information
Type
number
Package
Name
Description
PCF2120TK
HVSON10
plastic thermal enhanced very thin small outline
SOT650-1
package; no leads; 10 terminals; body 3 × 3 × 0.85 mm
wire bond die; 7 bonding pads; 0.57 × 1.1 × 0.2 mm
PCF2120U[1] [1]
Version
PCF2120U
Packing method: sawn wafer on Film Frame Carrier (FFC).
6. Block diagram
10
PCF2120
8
CLKOE
CLKOUT
3
OSCO
CL(itg)
1, 4, 6
2
OSCI
7
TEST
5
9
VSS
VDD
n.c.
001aaf631
Pin numbers shown for HSVON10 package.
Fig 1. Block diagram
7. Pinning information
7.1 Pinning
PCF2120U
terminal 1
index area
n.c.
1
OSCI
2
OSCO
3
n.c.
4
VSS
10 CLKOE
PCF2120TK
9
VDD
8
CLKOUT
7
TEST
6
5
n.c.
OSCI
1
OSCO
2
VSS
3
7
CLKOE
6
VDD
5
CLKOUT
4
TEST
001aaf628
Transparent top view
Fig 2.
Pin configuration HVSON10
package
PCF2120_1
Product data sheet
001aah559
Fig 3.
Pad configuration wire bond die
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
2 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Pad
Description
HVSON10
Wire bond die
n.c.
1
-
not connected
OSCI
2
1
oscillator input
OSCO
3
2
oscillator output
n.c.
4
-
not connected
VSS
5
3
ground
n.c.
6
-
not connected
TEST
7
4
test pin
CLKOUT
8
5
clock output (push-pull)
VDD
9
6
supply voltage
CLKOE
10
7
clock output enable input
8. Functional description
The 32 kHz quartz oscillator is optimized for directly connecting to a 32 kHz tuning fork
quartz crystal. No additional tuning capacitors are required. Laser tuning of the quartz or
quartz selection for matching is used to tune the oscillator if required.
A digital 32 kHz signal is available on pin CLKOUT. The signal on pin CLKOE is used to
gate and synchronize the 32 kHz CLKOUT signal. Pin CLKOUT is a CMOS push-pull
output. If disabled, it goes to LOW level.
OSCOinternal
32 kHz
(1)
CLKOE
CLKOUT
001aaf633
(1) OSCO-internal 32 kHz signal: internal signal after the Schmitt trigger connected to pin OSCO.
Fig 4. CLKOUT output signal
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
3 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
9. Internal circuitry
PCF2120
OSCI
OSCO
1
7
6
VDD
2
5
VSS
CLKOE
3
4
CLKOUT
TEST
001aaf634
Pin numbers shown for HSVON10 package.
Fig 5.
Device diode protection diagram
10. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
−0.5
+6.5
V
IDD
supply current
−50
+50
mA
VI
input voltage
−0.5
+6.5
V
VO
output voltage
−0.5
+6.5
V
II
input current
at any input
−10
+10
mA
IO
output current
at any output
−10
+10
mA
Ptot
total power dissipation
-
300
mW
Tstg
storage temperature
−65
+150
°C
Vesd
electrostatic discharge voltage
Ilu
Conditions
HBM
[1]
-
±2000
V
MM
[2]
-
±200
V
CDM
[3]
-
±2000
V
[4]
-
100
mA
latch-up current
[1]
Human Body Model (HBM) according to JESD22-A114.
[2]
Machine Model (MM) according to JESD22-A115.
[3]
Charged-Device Model (CDM) according to JESD22-C101.
[4]
Latch-up testing according to JESD78.
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
4 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
11. Static characteristics
Table 5.
Static characteristics
VDD = 1.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 40 kΩ; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.5
-
5.5
V
VDD = 5.0 V
-
300
550
nA
VDD = 3.0 V
-
235
500
nA
VDD = 2.0 V
-
210
450
nA
VDD = 5.0 V
-
345
750
nA
VDD = 3.0 V
-
265
650
nA
-
230
600
nA
VDD = 5.0 V
-
1310
1700
nA
VDD = 3.0 V
-
845
1100
nA
VDD = 2.0 V
-
615
900
nA
VDD = 5.0 V
-
1385
1700
nA
VDD = 3.0 V
-
875
1100
nA
VDD = 2.0 V
-
635
900
nA
−0.5
-
VDD + 0.5 V
Supply
VDD
supply voltage
IDD
supply current
[1]
clock output disabled
Tamb = 25 °C
Tamb = −40 °C to +85 °C
VDD = 2.0 V
clock output enabled at 32 kHz
[2]
Tamb = 25 °C
Tamb = −40 °C to +85 °C
Inputs
Pin OSCI
input voltage
VI
Pin CLKOE
VI
input voltage
−0.5
-
VDD + 0.5 V
VIL
LOW-level input voltage
-
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD -
-
V
ILI
input leakage current
−1
0
+1
µA
−0.5
-
VDD + 0.5 V
VI = VDD or VSS
Outputs
Pin OSCO
VO
Pin CLKOUT
VO
output voltage
−0.5
-
VDD + 0.5 V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 5 V
−1
-
-
mA
IOH
HIGH-level output current
VOH = 4.6 V; VDD = 5 V
-
-
1
mA
ILO
output leakage current
VO = VDD or VSS
−1
0
+1
µA
[1]
For reliable oscillator start-up at power-up: VDD > VDD(min) + 0.3 V.
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
5 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
[2]
Pin CLKOUT is loaded with a 7.5 pF capacitor.
When pin CLKOUT is enabled the current consumption is a function of the load on that pin, the output frequency and the supply voltage.
The additional current consumption for a given load can be calculated from the formula IDD = CCLKOUT × VDD × fCLKOUT
Where:
IDD = supply current
CCLKOUT = capacitance on pin CLKOUT
VDD = supply voltage
fCLKOUT = output frequency on pin CLKOUT
12. Dynamic characteristics
Table 6.
Dynamic characteristics
VDD = 1.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 40 kΩ and CL = 8 pF; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
6
8
10
pF
-
0.2
-
ppm
Oscillator
[1]
CL(itg)
integrated load capacitance
∆fosc/fosc
relative oscillator frequency variation
[1]
∆VDD = 200 mV; Tamb = 25 °C
CL(itg) is the combined equivalent integrated oscillator input and output capacitances.
001aaf635
1.0
IDD
(µA)
001aaf636
2.0
IDD
(µA)
0.8
1.6
0.6
1.2
0.4
0.8
0.2
0.4
0
0
0
2
4
6
0
2
4
VDD (V)
6
VDD (V)
a. CLKOUT disabled
b. CLKOUT enabled at 32 kHz
Tamb = 25 °C.
Tamb = 25 °C.
Fig 6. Supply current as a function of supply voltage
PCF2120_1
Product data sheet
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Rev. 01 — 5 February 2008
6 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
001aaf637
1.00
IDD
(µA)
0.95
0.90
0.85
0.80
0.75
−40
0
40
80
120
Tamb (°C)
VDD = 3 V; CLKOUT enabled at 32 kHz
Fig 7. Supply current as a function of ambient temperature
13. Application information
You can mount the PCF2120 oscillator together with the quartz crystal as an accurate and
pre-tuned quartz oscillator in one package.
CLKOE
PCF2120
CLKOUT
OSCO
CL(itg)
32 kHz
OSCI
TEST(1)
VSS
VDD
10 nF
001aaf632
(1) Do not connect pin TEST; it is chip-internally connected.
Fig 8.
Application diagram
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
7 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
14. Package outline
HVSON10: plastic thermal enhanced very thin small outline package; no leads;
10 terminals; body 3 x 3 x 0.85 mm
SOT650-1
0
1
2 mm
scale
X
A
B
D
A
A1
E
c
detail X
terminal 1
index area
C
e1
terminal 1
index area
e
5
y
y1 C
v M C A B
w M C
b
1
L
Eh
6
10
Dh
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
2.55
2.15
3.1
2.9
1.75
1.45
0.5
2
0.55
0.30
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT650-1
---
MO-229
---
EUROPEAN
PROJECTION
ISSUE DATE
01-01-22
02-02-08
Fig 9. Package outline SOT650-1 (HVSON10)
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
8 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
15. Bare die outline
Wire bond die; 7 bonding pads; 0.57 x 1.1 x 0.2 mm
bonding pad 1
corner
D
3
PCF2120U
2
A
1
P4
x
0
P3
E
0
P2
y
P1
4
5
6
7
detail X
X
DIMENSIONS (mm are the original dimensions)
UNIT
A
D
E
P1
P2
P3
P4
mm
0.212
0.188
1.1
0.57
0.07
0.06
0.07
0.06
OUTLINE
VERSION
P1 and P3: pad size
P2 and P4: passivation opening
0
0.5
1 mm
scale
REFERENCES
IEC
JEDEC
EUROPEAN
PROJECTION
JEITA
ISSUE DATE
07-12-07
08-02-01
PCF2120U
Fig 10. Bare die outline PCF2120U
Table 7.
Bonding pad coordinates
Values x and y in µm.
Pad
x
y
1
+313
+187
2
+93
+187
3
−236
+187
4
−259
−172
5
−137
−172
6
+127
−172
7
+380
−172
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
9 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 11) than a SnPb process, thus
reducing the process window
PCF2120_1
Product data sheet
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Rev. 01 — 5 February 2008
10 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 9.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 11.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 11. Temperature profiles for large and small components
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
11 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF2120_1
20080205
Product data sheet
-
-
PCF2120_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 February 2008
12 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Bare die — All die are tested on compliance with all related technical
specifications as stated in this data sheet up to the point of wafer sawing for a
period of ninety (90) days from the date of delivery by NXP Semiconductors.
If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There are no post-packing tests performed on
individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF2120_1
Product data sheet
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Rev. 01 — 5 February 2008
13 of 14
PCF2120
NXP Semiconductors
Quartz oscillator
20. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Application information. . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Soldering of SMD packages . . . . . . . . . . . . . . . 9
Introduction to soldering . . . . . . . . . . . . . . . . . 10
Wave and reflow soldering . . . . . . . . . . . . . . . 10
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 10
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 February 2008
Document identifier: PCF2120_1