CCD Delay Line Series MN3885S NTSC-Compatible CCD Video Signal Delay Element Overview The MN3885S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3885S samples the input using the supplied clock signal with a frequency 7.15909 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Features Pin Assignment VOC 1 8 VINC VDD 2 7 XI VSS 3 6 VBB VOY 4 5 VINY ( TOP VIEW ) SOP008-P-0225A Single 5.0 V power supply Single chip combining luminance signal delay line and delay line for color signal converted to the low frequency. Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3885S consists of the operational blocks shown in the block diagram. The shift register has the structure shown in the supplementary diagram. Shift register clock driver This block generates two transfer clock signals, ø1 and ø2, synchronized with the 7.15909 MHz input clock signal. It also generates the sampling clock signals øS and øS', resampling clock signal øSH, and reset clock signal øR based on the timing control. Charge Input blocks These blocks alter the analog input signals from the VINC and VINY pins on their way to the shift registers. One adds the bias voltage specified with the bias circuit to the analog signal from the VINC pin. The other applies an "L" level clamp voltage from the clamp circuit to the analog signal from the VINY pin. Analog shift registers These blocks sample the shift register input signals with the sampling clock, and convert the results to charges, and use transfer clocks ø1 and ø2 to transfer the results to the following block. Charge detection blocks These convert the signal charges from the final stage of the analog shift registers into voltage signals. Resampling output amplifiers In the output stage of this blocks, the voltage signal is executed Sample-and-Hold by resampling, and is outputted at signal output pin of VOC (1-pin) and VOY (4-pin). Bias circuit This circuit applies a bias voltage to the analog signal from VINC (pin 8) to optimize it for the shift register. Clamp circuit This circuit applies an "L" level clamp to the analog signal from VINY (pin 5) to optimize it for the shift register. Booster circuits These generate reset drain voltages. 1 MN3885S CCD Delay Line Series 3 V SS 2 V DD Block Diagram Bias circuit VINC 8 Charge input block øS driver CCD 454 stages ø1 driver ø2 driver Charge detection block øR driver Resampling output amplifier 1 VOC øSH driver øSH driver Timing adjustment XI 7 Waveform amplifier adjustment block øS' driver VINY 5 Charge input block CCD 453.5 stages Clamp circuit VBB 6 Substrate bias generator 2 Charge detection block Resampling output amplifier 4 VOY CCD Delay Line Series MN3885S Pin Descriptions Pin No. 1 Symbol VOC Pin Name Remarks Signal output (C) 2 VDD Power supply 3 VSS Ground 4 VOY Signal output (Y) 5 VINY Signal input (Y) 6 VBB 7 XI 8 VINC Substrate connection Negative voltage pin Clock input Signal input (C) Operating Conditions Parameter Power supply Symbol VDD min 4.75 Input clock frequency fck Input clock amplitude (sine wave) vck 0.2 Ambient temperature Ta –20 typ 5.00 max 5.25 Unit V 7.15909 MHz 0.3 1.5 VP–P 60 ˚C Electrical Characteristics VDD=5.0V, Vck=0.3VP-P (sine wave), Vin=0.5VP-P (sine wave), fck=7.15909MHz, Ta=25˚C Parameter Power supply voltage Symbol Conditions min typ 18 IDD max 36 Signal bandwidth (Y signal) BWY –3 dB for 200 kHz value 1.8 2.8 Signal bandwidth (C signal) BWC –3 dB for 200 kHz value 1.8 2.8 Insertion gain (Y signal) IGY fsig=200kHz 0.0 3.0 6.0 Insertion gain (C signal) IGC fsig=200kHz –1.0 2.0 5.0 Total harmonic distortion THD fsig=200kHz 1.0 4.5 Signal-to-noise ratio S/N Signal output (Vp-p)/noise output (rms) Clock leak NC 7.16 MHz components for both Y and C signals fsig=200kHz 48 Unit mA MHz 56 dB % dB –30 –10 dB –50 –35 dB Crosstalk CT Delay (Y signal) τDY 63.38 Delay (C signal) τDC 63.46 VO pin output impedance ZOY 0.5 0.9 ZOC 0.5 0.9 Input bias voltage VBIN Applied to input from C signal input pin 2.86 V Input clamp voltage VCLIN Applied to input from Y signal input pin 2.70 V µs kΩ Output bias voltage VBO Applied to output from C signal output pin 2.70 V Output clamp voltage VCLO Applied to output from Y signal output pin 2.40 V Substrate voltage –VBB –2.80 V 3 MN3885S CCD Delay Line Series VINY Shift Register Configuration Booster circuit Clamp circuit øS' ø1 Voltage generator ø2 2 VDD øR ....... ....... øSH VINY 5 Output amplifier 4 3 4 VOY VSS CCD Delay Line Series MN3885S Application Circuit Example 10µF + 0.1µF 2 VDD 3 VSS – Bias circuit VINC 8 0.01µF 330Ω Charge input block CCD 454 stages Charge detection block Resampling output amplifier 1 VOC 2SA564 øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Timing adjustment XI 7 Waveform amplifier adjustment block 1000pF øS' driver VINY 5 0.47µF 330Ω Charge input block CCD 453.5 stages Charge detection block Resampling output amplifier 4 VOY 2SA564 Clamp circuit VBB 6 Substrate bias generator 0.01µF Note: If the external capacitor attached to pin 6 is a electrolytic capacitor, connect the negative pole to pin 6. 5 MN3885S CCD Delay Line Series Package Dimensions (Unit:mm) 0.4 0.4±0.25 SOP008-P-0225A 5.0±0.3 8 4 5 4.2±0.3 6.5±0.3 6 0.15 0.65 0.3 1.5±0.2 0.1±0.1 1.27 1