Download Datasheet

STM6524
6-pin Smart Reset™
Datasheet − production data
Features
■
Operating voltage 1.65 V to 5.5 V
■
Low supply current 1.5 µA
■
Integrated test mode
■
Dual Smart Reset™ push-button inputs with
fixed extended reset setup delay (tSRC) from
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal pull-up resistor
■
Push-button controlled reset pulse duration
– Option 1: fully push-button controlled, no
fixed or minimum pulse width guaranteed
– Option 2: defined output reset pulse
duration (tREC), factory-programmed
■
No power-on reset
■
Single reset output
– Active low or active high
– Push-pull or open drain with optional pullup resistor
■
Fixed Smart Reset™ input logic voltage levels
■
Operating temperature: –40 °C to +85 °C
■
UDFN6 package: 1.6 mm x 1.3 mm
■
ECOPACK®2 (RoHS compliant, HalogenFree)
August 2012
This is information on a product in full production.
UDFN6 1.6 mm x 1.3 mm
Applications
■
Mobile phones, smartphones, PDAs
■
e-books
■
MP3 players
■
Games
■
Portable navigation devices
■
Any application that requires delayed reset
push-button(s) response for improved system
stability.
Doc ID 022335 Rev 3
1/24
www.st.com
1
Contents
STM6524
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Smart Reset™ input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Smart Reset™ input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
Doc ID 022335 Rev 3
STM6524
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mechanical data for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch . . . . . . . . . . . . . . . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3/24
List of figures
STM6524
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
4/24
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Option without tREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Option with tREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Undervoltage condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply current (ICC) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Smart Reset™ delay (tSRC) vs. temperature (TA), tSRC = 7.5 s (typ.). . . . . . . . . . . . . . . . . 13
Test mode entry voltage (VTEST) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Initial test mode time (tSRC-INI) vs. temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch . . . . . . . . . . . . . . . . . . . . 18
Footprint recommendation for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch. . . . . . . . . . . . 19
Carrier tape for UDFN6 1.6 x 1.3 x 0.55 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Doc ID 022335 Rev 3
STM6524
1
Description
Description
The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset
push-button closures do not cause system resets. This is done by implementing extended
Smart Reset™ input delay time (tSRC) and combined push-button inputs, which together
ensures a safe reset and eliminates the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish between
a software generated interrupt and a hard system reset. When the input push-buttons are
connected to microcontroller interrupt inputs, and are closed for a short time, the processor
can only be interrupted. If the system still does not respond properly, continuing to keep the
push-buttons closed for the extended setup time tSRC causes a hard reset of the processor
through the reset output.
The STM6524 has two combined delayed Smart Reset™ inputs (SR0, SR1) with preset
delayed Smart Reset™ setup time (tSRC). The reset output is asserted after both of the
Smart Reset™ inputs were held active for the selected tSRC delay time. Depending on
selected option the RST output remains asserted either until at least one SR input goes to
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset
pulse duration is fixed for tREC (i.e. factory-programmed). The reset output, RST, is
active low or active high, push-pull or open drain with optional pull-up resistor. The device
fully operates over a broad VCC range 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are
ignored and outputs are deasserted; the deasserted reset output levels are then valid down
to 1.0 V.
Test mode
After pull of SR0 up to VTEST or more (VCC + 1.4 V, max.) we start counting initial
shorten tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for
tREC (if tREC option is used) or stays low as long as overvoltage on SR0 in detected (if tREC
option is not used). This is a feedback and a user knows that the device is locked in the test
mode. Each time both SR inputs are connected to ground in test mode a shorten
tSRC-SHORT (21 ms, typ.) is used instead of long tSRC (0.5 s -10 s). Return from to normal
mode is possible by a new startup of the device (i.e. VCC goes to 0 V and back to its original
state). In this way the device can be quickly tested without repeating test mode triggering.
Advantage of this solution is pretty high glitch immunity, feedback to user about entry to the
test mode and testability within full VCC range.
Doc ID 022335 Rev 3
5/24
Description
STM6524
Figure 1.
Logic diagram
6##
32 34- 234
32
'.$
!-
Figure 2.
Pin connections (top view)
633
32
234
34
6##
32
.#
!-
6/24
Doc ID 022335 Rev 3
STM6524
Table 1.
Pin Name
1
VSS
2
SR1
Description
Signal names
Type
Supply ground Ground
Input
3
RST
Output
4
NC
-
5
SR0
Input
6
VCC
Figure 3.
Description
Secondary push-button Smart Reset™ input. Active low. Optional pull-up resistor.
Reset output
(open drain with optional pull-up resistor, active low)
(push-pull – active low or active high)
Not connected (not bonded; should be connected to VSS)
Primary push-button Smart Reset™ input. Active low. Optional pull-up resistor.
Positive supply voltage for the device. A 0.1 µF decoupling ceramic capacitor is
Supply voltage recommended to be connected between VCC and VSS pins, as close to the STM6524
device as possible.
Block diagram
/VERVOLTAGEDETECT
TESTMODETRIGGER
32 32
!.$
T 32#
GENERATOR
T2%#
GENERATOR
OPTIONAL
234
!-6
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Pin descriptions
STM6524
2
Pin descriptions
2.1
Power supply (VCC)
This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the VCC and VSS pins, as close to the
STM6524 device as possible.
2.2
Ground (VSS)
Ground pin for the device.
2.3
Smart Reset™ input (SR0)
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR
inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST).
By connecting a voltage higher than VCC to the SR0 the device enters a test mode (see
Section 1: Description on page 5 for more information).
2.4
Smart Reset™ input (SR1)
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs
need to be asserted simultaneously for at least tSRC to assert the reset output (RST).
2.5
Reset output (RST)
RST is active low or active high, push-pull or open drain reset output with optional internal
pull-up resistor. Output reset pulse width is optional as follows:
●
Neither fixed nor minimum output reset pulse duration (releasing the push-button while
reset output is active, causes the output to de-assert);
●
Fixed, factory-programmed output reset pulse duration for tREC independent on Smart
Reset™ input state.
If VCC drops below 1.575 V, the RST output is deasserted and its state is guaranteed down
to 1 V (see Figure 8).
8/24
Doc ID 022335 Rev 3
STM6524
3
Typical application diagram
Typical application diagram
Figure 4.
Single-button Smart Reset™ typical hookup
6##
6##
6##
234
2%3%4
34-
-#5
32
).4 .-)
32
633
633
053( "544/.
37)4#( !-6
1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up.
2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
3. When only one Smart Reset™ input push-button is used, tie both the SR inputs together.
Doc ID 022335 Rev 3
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Typical application diagram
Figure 5.
STM6524
Dual-button Smart Reset™ typical hookup
6##
6##
6##
234
2%3%4
34-
-#5
32
32
).4.-)
633
633
053( "544/.
37)4#(
053( "544/.
37)4#(
!-6
1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up.
2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
10/24
Doc ID 022335 Rev 3
STM6524
Timing waveforms
4
Timing waveforms
Figure 6.
Option without tREC
6
6##
6
6
6
3TART
TIMER
%ND
TIMER
0USHBUTTON
CONTROLLEDOUTPUT
T32#
32
'LITCH
IMMUNITY
32
234
!-6
Figure 7.
Option with tREC
6
6
6
6
6##
T2%#
T32#
32
'LITCH
IMMUNITY
32
234
!-6
Doc ID 022335 Rev 3
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Timing waveforms
Figure 8.
STM6524
Undervoltage condition
6
6##
6
6
6
32
6
6
32
6
6
234
6
T32#
4IMES
!-
1. If undervoltage occurs (VCC drops below 1.575 V typ.) while reset output is active, the reset output is released and goes
inactive.
12/24
Doc ID 022335 Rev 3
STM6524
Typical operating characteristics
Figure 9.
Supply current (ICC) vs. temperature (TA)
3UPPLYCURRENT)## —!
6##6
6##6
6##6
4EMPERATURE #
!-6
Figure 10. Smart Reset™ delay (tSRC) vs. temperature (TA), tSRC = 7.5 s (typ.)
3MART2ESET4-DELAYT 32# S
5
Typical operating characteristics
6##6
6##6
6##6
4EMPERATURE #
!-6
Doc ID 022335 Rev 3
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Typical operating characteristics
STM6524
Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA)
4ESTMODEENTRYVOLTAGE64%34 6
6##6
6##6
6##6
4EMPERATURE4! #
!-
Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA)
)NITIALTESTMODETIMET32#?).) MS
6##6
6##6
6##6
4EMPERATURE4! #
14/24
Doc ID 022335 Rev 3
!-
STM6524
6
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 3: Operating and
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 2.
Absolute maximum ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
VIO
Input or output voltage
VCC
Supply voltage
Value
Unit
-55 to +150
°C
260
°C
-0.3 to 5.5(2)
V
-0.3 to 7
V
ESD
VHBM
Electrostatic discharge protection, human body model (JESD22A114-B level 2)
2
kV
VRCDM
Electrostatic discharge protection, charged device model, all pins
1
kV
200
V
EIA/JESD78
-
VMM
Electrostatic discharge protection, machine model, all pins
(JESD22-A115-A level A)
Latch-up (VCC pin, SR0 reset input pin)
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. For push-pull RST output type only from -0.3 V to VCC +0.3 V.
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DC and AC parameters
7
STM6524
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters inTable 4: DC and AC characteristic that
follow, are derived from tests performed under the measurement conditions summarized in
Table 3: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 3.
Operating and measurement conditions
Symbol
VCC
TA
16/24
Parameter
Value
Unit
Supply voltage
1.65 to 5.5
V
Ambient operating temperature
-40 to +85
°C
Doc ID 022335 Rev 3
STM6524
Table 4.
DC and AC parameters
DC and AC characteristic
Symbol
Parameter
VCC
Supply voltage(3)
ICC
Supply current (inputs in
their inactive state, tSRC
counter is not running)
VOL
VOH
tREC
Reset output voltage low
Reset output voltage high
(push-pull output only)
Reset timeout delay,
factory-programmed
Test conditions(1)
Min.
Typ.(2)
1.65
Max.
Unit
5.5
V
VCC = 3.0 V
1.1
2.5
µA
VCC = 5.0 V
1.5
3.0
µA
VCC ≥ 4.5 V, sinking 3.2 mA
0.3
V
VCC ≥ 3.3 V, sinking 2.5 mA
0.3
V
VCC ≥ 1.65 V, sinking 1 mA
0.3
V
VCC ≥ 4.5 V, ISOURCE = 0.8 mA
0.8 VCC
V
VCC ≥ 2.7 V, ISOURCE = 0.5 mA
0.8 VCC
V
VCC ≥ 1.65 V, ISOURCE = 0.25 mA
0.8 VCC
V
(device option)
RPUO
Internal output pull-up
resistor on RST
(device option)
ILO
Output leakage current
VRST = 5.5 V, open drain device
option without output pull-up
resistor
0.85
1.28
1.71
ms
66
100
134
ms
140
210
280
ms
240
360
480
ms
65
-0.1
kΩ
0.1
µA
Smart ResetTM
tSRC
Smart Reset™ delay
TA = -40 to +85 °C
0.8 x tSRC
TA = 25 °C
0.9 x tSRC
tSRC(4)
1.2 x tSRC
1.1 x tSRC
s
VIL
SR0, SR1 input voltage
low
VSS -0.3
0.3
V
VIH
SR0, SR1 input voltage
high
0.85
5.5
V
ILI
SR0, SR1 input leakage
current
-0.1
0.1
µA
Input glitch immunity(5)
SR0 and SR1 asserted
tSRC
s
Test mode
VTEST
Test mode entry voltage
tSRC-INI Initial test mode time
tSRCSHORT
Shorten Smart Reset™
delay
VCC +0.9
VCC +1.1
VCC +1.4
V
28
42
56
ms
16.8
21
25.2
ms
1. Valid for ambient operating temperature TA = -40 to +85 °C, VCC = 1.65 to 5.5 V.
2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted.
3. Reset outputs are deasserted below 1.575 V typ. and remain deasserted down to VCC = 1 V.
4. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps (see Table 7 for available delays).
5.
Input glitch immunity is equal to tSRC, when both inputs (SR0 and SR1) are low. Otherwise infinite.
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Package information
8
STM6524
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. Package outline for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
$
!
"
0).).$%8!2%!
$X%
%
# X
# X
4/06)%7
#
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X
3%!4). '
0,!.%
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#
!
E
BX
0).).$%8!2%!
$X%
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18/24
Doc ID 022335 Rev 3
STM6524
Package information
Table 5.
Mechanical data for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
Dimensions
Symbol
Drawing (millimeters)
Drawing (inches)
Note
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0.00
0.02
0.05
0.0000
0.0008
0.0020
b
0.15
0.20
0.25
0.006
0.008
0.010
D
1.30 BSC
0.051 BSC
E
1.60 BSC
0.063 BSC
e
0.40 BSC
0.016 BSC
L
0.250
N
0.325
0.400
0.0098
6
0.0128
0.0157
6
Figure 14. Footprint recommendation for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
!-
Doc ID 022335 Rev 3
19/24
Package information
STM6524
Figure 15. Carrier tape for UDFN6 1.6 x 1.3 x 0.55 mm
0
›
4
›
0O
›
%
›
9
$
Œ›
#,
&
7
2%&
"O
9
0
!O
+O
3%#4)/.99
!O
"O
+O
&
0
7
›
›
›
›
›
›
!-
1. Measured from centreline of sprocket hole to centreline of pocket.
2. Cumulative tolerance of 10 sprocket holes is ± 0.20.
3. Measured from centreline of sprocket hole to centreline of pocket.
4. Other material available.
5. Typical SR of formed tape max. 109 Ω/ SQ.
6. All dimensions in millimeters unless otherwise stated.
Figure 16. Pin 1 orientation
5SERDIRECTIONOFFEED
!-
20/24
Doc ID 022335 Rev 3
STM6524
9
Part numbering
Part numbering
Table 6.
Ordering information scheme
Example:
STM6524
A
H
A
R
DL
6
F
Device type
STM6524
Reset (VCC monitoring threshold) voltage VRST
A = no VCC monitoring feature
Smart Reset™ set up delay (tSRC)(1)
H = factory programmable tSRC = 4.0 s, no pull-up
L = factory programmable tSRC = 6.0 s, no pull-up
P = factory programmable tSRC = 7.5 s, no pull-up
U = factory programmable tSRC = 10.0 s, no pull-up
Outputs type
A = open drain, no pull-up, active low
C = open drain, 50 kΩ internal pull-up resistor, active low
D = push-pull, active low
H = push-pull, active high
Reset timeout period (tREC)
A = factory programmable tREC = 210 ms (typ.)
B = factory programmable tREC = 360 ms (typ.)
E = factory programmable tREC = 1.28 ms (typ.)
F = factory programmable tREC = 100 ms (typ.)
R = push-button controlled
Package
DL = UDFN6
Temperature range
6 = -40 °C to +85 °C
Shipping method
F = Tape and reel
1. Smart ResetTM delay (tSRC) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities
may apply. Contact local sales office for availability.
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Package marking information
10
STM6524
Package marking information
Table 7.
Package marking
Part number
tSRC (s)
Smart Reset™
inputs(1)
Output
type(2)
tREC option
(ms)(3)
STM6524AHARDL6F
4.0
AL
OD, AL
No tREC
UDFN6
HA
STM6524ALABDL6F
6.0
AL
OD, AL
360
UDFN6
LC
STM6524ALARDL6F
6.0
AL
OD, AL
No tREC
UDFN6
LA
STM6524APARDL6F
7.5
AL
OD, AL
No tREC
UDFN6
PA
STM6524AUABDL6F
10.0
AL
OD, AL
360
UDFN6
UC
STM6524AUARDL6F
10.0
AL
OD, AL
No tREC
UDFN6
UA
Package Topmark
1. AL = active low.
2. OD = open drain, AL = active low.
3. No tREC = push-button controlled reset pulse width.
Figure 17. Package marking (top view)
!
"
!DOTPINREFERENCE
"MARKINGAREATOPMARK
!-
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Revision history
Revision history
Table 8.
Document revision history
Date
Revision
Changes
07-Oct-2011
1
Initial release.
13-Jun-2012
2
Updated Features, Section : Test mode, Table 4, title of Section 8,
minor text corrections throughout document.
31-Aug-2012
3
Updated Table 7 (added “(ms)” to tREC option, added
STM6524ALABDL6F and STM6524AUABDL6F devices).
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STM6524
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