Data Sheet

SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA)
encoder/decoder
Rev. 05 — 10 May 2004
Product data
1. Description
The SC16C554/554D is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.
The SC16C554/554D is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control
registers enables the added features of the SC16C554/554D. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C554/554D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide
the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back
capability allows on-board diagnostics.
The SC16C554/554D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
2. Features
■ 5 V, 3.3 V and 2.5 V operation
■ Industrial temperature range
■ The SC16C554/554D is pin compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554
■ Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
■ 16-byte transmit FIFO
■ 16-byte receive FIFO with error flags
■ Automatic software/hardware flow control
■ Programmable Xon/Xoff characters
■ Software selectable Baud Rate Generator
■ Four selectable Receive FIFO interrupt trigger levels
■ Standard modem interface or infrared IrDA encoder/decoder interface
■ Sleep mode
■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
■ Fully programmable character formatting:
◆ 5, 6, 7, or 8-bit characters
◆ Even, Odd, or No-Parity formats
◆ 1, 11⁄2, or 2-stop bit
◆ Baud generation (DC to 5 Mbit/s)
■ False start-bit detection
■ Complete status reporting capabilities
■ 3-State output TTL drive capabilities for bi-directional data bus and control bus
■ Line Break generation and detection
■ Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
■ Prioritized interrupt system controls
■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
SC16C554DIA68
PLCC68
plastic leaded chip carrier; 68 leads
SOT188-2
SC16C554DIB64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
SC16C554IB64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
SC16C554IB80
LQFP80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
2 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
4. Block diagram
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
D0–D7
IOR
IOW
RESET
TRANSMIT
SHIFT
REGISTER
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
FLOW
CONTROL
LOGIC
A0–A2
CSA-CSD
TXA-TXD
IR
ENCODER
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
FLOW
CONTROL
LOGIC
RXA-RXD
IR
DECODER
16/68
DTRA-DTRD
RTSA-RTSD
MODEM
CONTROL
LOGIC
INTA-INTD
TXRDY
RXRDY
CTSA-CTSD
RIA-RID
CDA-CDD
DSRA-DSRD
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
INTSEL
002aaa168
XTAL1
XTAL2
CLKSEL
Fig 1. SC16C554/554D block diagram (16 mode).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
3 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
D0–D7
R/W
RESET
TRANSMIT
SHIFT
REGISTER
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
FLOW
CONTROL
LOGIC
A0–A4
CS
TXA-TXD
IR
ENCODER
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
FLOW
CONTROL
LOGIC
RXA-RXD
IR
DECODER
16/68
DTRA-DTRD
RTSA-RTSD
MODEM
CONTROL
LOGIC
IRQ
TXRDY
RXRDY
CTSA-CTSD
RIA-RID
CDA-CDD
DSRA-DSRD
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
002aaa343
XTAL1
XTAL2
CLKSEL
Fig 2. SC16C554/554D block diagram (68 mode).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
4 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5. Pinning information
5.1 Pinning
D3
1
61 CDD
D4
2
62 RID
D5
3
63 RXD
D6
4
64 VCC
D7
5
65 INTSEL
GND
6
66 D0
RXA
7
67 D1
RIA
8
68 D2
CDA
PLCC68
9
5.1.1
DSRA 10
60 DSRD
CTSA 11
59 CTSD
DTRA 12
58 DTRD
VCC 13
57 GND
RTSA 14
56 RTSD
INTA 15
55 INTD
CSA 16
54 CSD
TXA 17
53 TXD
SC16C554DIA68
16 MODE
IOW 18
52 IOR
TXB 19
51 TXC
CSB 20
50 CSC
INTB 21
49 INTC
RTSB 22
48 RTSC
47 VCC
GND 23
CDC 43
RIC 42
RXC 41
GND 40
TXRDY 39
RXRDY 38
RESET 37
XTAL2 36
XTAL1 35
A0 34
A1 33
A2 32
44 DSRC
n.c. 31
DSRB 26
VCC 30
45 CTSC
RXB 29
CTSB 25
RIB 28
46 DTRC
CDB 27
DTRB 24
002aaa166
Fig 3. PLCC68 pin configuration (16 mode).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
5 of 55
SC16C554/554D
Philips Semiconductors
D3
1
61 CDD
D4
2
62 RID
D5
3
63 RXD
D6
4
64 VCC
D7
5
65 n.c.
GND
6
66 D0
RXA
7
67 D1
RIA
8
68 D2
CDA
9
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
DSRA 10
60 DSRD
CTSA 11
59 CTSD
DTRA 12
58 DTRD
VCC 13
57 GND
RTSA 14
56 RTSD
IRQ 15
55 n.c.
CS 16
54 n.c.
TXA 17
53 TXD
SC16C554DIA68
68 MODE
R/W 18
52 n.c.
51 TXC
TXB 19
A3 20
50 A4
n.c. 21
49 n.c.
48 RTSC
RTSB 22
47 VCC
GND 23
CDC 43
RIC 42
RXC 41
GND 40
TXRDY 39
RXRDY 38
RESET 37
XTAL2 36
XTAL1 35
A0 34
A1 33
A2 32
44 DSRC
16/68 31
DSRB 26
VCC 30
45 CTSC
RXB 29
CTSB 25
RIB 28
46 DTRC
CDB 27
DTRB 24
002aaa344
Fig 4. PLCC68 pin configuration (68 mode).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
6 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
49 CDD
50 RID
51 RXD
52 VCC
53 D0
54 D1
55 D2
56 D3
57 D4
58 D5
59 D6
60 D7
61 GND
62 RXA
63 RIA
LQFP64
64 CDA
5.1.2
DSRA 1
48 DSRD
CTSA 2
47 CTSD
DTRA 3
46 DTRD
VCC 4
45 GND
RTSA 5
44 RTSD
INTA 6
43 INTD
CSA 7
42 CSD
TXA 8
41 TXD
SC16C554IB64
SC16C554DIB64
IOW 9
40 IOR
TXB 10
39 TXC
CSB 11
38 CSC
INTB 12
37 INTC
RTSB 13
36 RTSC
GND 14
35 VCC
CDC 31
DSRC 32
RIC 30
RXC 29
GND 28
RESET 27
XTAL2 26
A0 24
XTAL1 25
A1 23
A2 22
VCC 21
RXB 20
33 CTSC
RIB 19
CTSB 16
CDB 18
34 DTRC
DSRB 17
DTRB 15
002aaa167
Fig 5. LQFP64 pin configuration.
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9397 750 13132
Product data
Rev. 05 — 10 May 2004
7 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
61 n.c.
62 DSRC
63 CTSC
64 DTRC
65 VCC
66 RTSC
67 INTC
68 CSC
69 TXC
70 IOR
71 n.c.
72 TXD
73 CSD
74 INTD
75 RTSD
76 GND
77 DTRD
LQFP80
78 CTSD
79 DSRD
handbook, full pagewidth
80 n.c.
5.1.3
n.c.
1
60 n.c.
CDD
2
59 CDC
RID
3
58 RIC
RXD
4
57 RXC
VCC
5
56 GND
INTSEL
6
55 TXRDY
D0
7
54 RXRDY
D1
8
53 RESET
D2
9
52 n.c.
n.c. 10
51 XTAL2
SC16C554IB80
D3 11
50 XTAL1
D4 12
49 n.c.
D5 13
48 A0
D6 14
47 A1
D7 15
46 A2
n.c. 40
DSRB 39
CTSB 38
DTRB 37
GND 36
RTSB 35
INTB 34
CSB 33
TXB 32
IOW 31
n.c. 30
41 n.c.
TXA 29
n.c. 20
CSA 28
42 CDB
INTA 27
CDA 19
RTSA 26
43 RIB
VCC 25
RIA 18
DTRA 24
44 RXB
CTSA 23
RXA 17
DSRA 22
45 VCC
n.c. 21
GND 16
002aaa385
Fig 6. LQFP80 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
8 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
PLCC68 LQFP64 LQFP80
Type
Description
16/68
31
-
-
I
16/68 Interface type select (input with internal pull-up). This input
provides the 16 (Intel) or 68 (Motorola) bus interface type select. The
functions of IOR, IOW, INT A-INTD, and CSA-CSD are re-assigned
with the logical state of this pin. When this pin is a logic 1, the 16
mode interface (16C554) is selected. When this pin is a logic 0, the
68 mode interface (68C554) is selected. When this pin is a logic 0,
IOW is re-assigned to R/W, RESET is re-assigned to RESET, IOR is
not used, and INTA-INTD are connected in a wire-OR configuration.
The wire-OR outputs are connected internally to the open drain IRQ
signal output. This pin is not available on 64-pin packages which
operate in the 16 mode only.
A0
34
24
48
I
Address 0 select bit. Internal registers address selection in 16 and
68 modes.
A1
33
23
47
I
Address 1 select bit. Internal registers address selection in 16 and
68 modes.
A2
32
22
46
I
Address 2 select bit. Internal registers address selection in 16 and
68 modes.
A3, A4
20, 50
-
-
I
Address 3-4 select bits. When the 68 mode is selected, these pins
are used to address or select individual UARTs (providing CS is a
logic 0). In the 16 mode, these pins are re-assigned as chip selects,
see CSB and CSC.
CDA, CDB,
CDC, CDD
9, 27,
43, 61
64, 18,
31, 49
19, 42,
59, 2
I
Carrier Detect (Active-LOW). These inputs are associated with
individual UART channels A through D. A logic 0 on this pin indicates
that a carrier has been detected by the modem for that channel.
CS
16
-
-
I
Chip Select (Active-LOW). In the 68 mode, this pin functions as a
multiple channel chip enable. In this case, all four UARTs (A-D) are
enabled when the CS pin is a logic 0. An individual UART channel is
selected by the data contents of address bits A3-A4. when the
16 mode is selected (68-pin devices), this pin functions as CSA (see
definition under CSA, CSB).
CSA, CSB,
CSC, CSD
16, 20,
50, 54
7, 11,
38, 42
28, 33,
68, 73
I
Chip Select A, B, C, D (Active-LOW). This function is associated
with the 16 mode only, and for individual channels ‘A’ through ‘D’.
When in 16 mode, these pins enable data transfers between the user
CPU and the SC16C554/554D for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a
logic 0 on the respective CSA-CSD pin. When the 68 mode is
selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
CTSA, CTSB, 11, 25,
CTSC, CTSD 45, 59
2, 16,
33, 47
23, 38,
63, 78
I
Clear to Send (Active-LOW). These inputs are associated with
individual UART channels A through D. A logic 0 on the CTS pin
indicates the modem or data set is ready to accept transmit data from
the SC16C554/554D. Status can be tested by reading MSR[4]. This
pin only affects the transmit or receive operations when Auto CTS
function is enabled via the Enhanced Feature Register EFR[7] for
hardware flow control operation.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
9 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2:
Pin description…continued
Symbol
D0-D2,
D3-D7
Pin
PLCC68 LQFP64 LQFP80
Type
Description
66-68,
1-5
53-55,
56-60
7-9,
11-15
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus
for transferring information to or from the controlling CPU. D0 is the
least significant bit and the first data bit in a transmit or receive serial
data stream.
10, 26,
DSRA,
44, 60
DSRB,
DSRC, DSRD
1, 17,
32, 48
22, 39,
62, 79
I
Data Set Ready (Active-LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data exchange
with the UART. This pin has no effect on the UART’s transmit or
receive operation.
12, 24,
DTRA,
46, 58
DTRB,
DTRC, DTRD
3, 15,
34, 46
24, 37,
64, 77
O
Data Terminal Ready (Active-LOW). These outputs are associated
with individual UART channels, A through D. A logic 0 on this pin
indicates that the SC16C554/554D is powered-on and ready. This pin
can be controlled via the modem control register. Writing a logic 1 to
MCR[0] will set the DTR output to logic 0, enabling the modem. This
pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
This pin has no effect on the UART’s transmit or receive operation.
GND
6, 23,
40, 57
14, 28,
45, 61
16, 36,
56, 76
I
Signal and power ground.
INTA, INTB,
INTC, INTD
15, 21,
49, 55
6, 12,
37, 43
27, 34,
67, 74
O
Interrupt A, B, C, D (Active-HIGH). This function is associated with
the 16 mode only. These pins provide individual channel interrupts
INTA-INTD. INTA-INTD are enabled when MCR[3] is set to a logic 1,
interrupts are enabled in the interrupt enable register (IER), and
when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty,
or when a modem status flag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
INTSEL
65
-
6
I
Interrupt Select (Active-HIGH, with internal pull-down). This
function is associated with the 16 mode only. When the 16 mode is
selected, this pin can be used in conjunction with MCR[3] to enable
or disable the 3-State interrupts, INTA-INTD, or override MCR[3] and
force continuous interrupts. Interrupt outputs are enabled
continuously by making this pin a logic 1. Making this pin a logic 0
allows MCR[3] to control the 3-State interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-State outputs. This pin is
disabled in the 68 mode. Due to pin limitations on the 64-pin
packages, this pin is not available. To cover this limitation, the
SC16C654DIB64 version operates in the continuous interrupt enable
mode by bonding this pin to VCC internally. The SC16C654IB64
operates with MCR[3] control by bonding this pin to GND.
IOR
52
40
70
I
Input/Output Read strobe (Active-LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
load the contents of an internal register defined by address bits
A0-A2 onto the SC16C554/554D data bus (D0-D7) for access by
external CPU. This pin is disabled in the 68 mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
10 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2:
Pin description…continued
Symbol
Pin
PLCC68 LQFP64 LQFP80
Type
Description
IOW
18
9
31
I
Input/Output Write strobe (Active-LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
transfer the contents of the data bus (D0-D7) from the external CPU
to an internal register that is defined by address bits A0-A2. When
the 68 mode is selected, this pin functions as R/W (see definition
under R/W).
IRQ
15
-
-
O
Interrupt Request or Interrupt ‘A’. This function is associated with
the 68 mode only. In the 68 mode, interrupts from UART channels
A-D are wire-ORed internally to function as a single IRQ interrupt.
This pin transitions to a logic 0 (if enabled by the interrupt enable
register) whenever a UART channel(s) requires service. Individual
channel interrupt status can be determined by addressing each
channel through its associated internal register, using CS and A3-A4.
In the 68 mode, and external pull-up resistor must be connected
between this pin and VCC. The function of this pin changes to INTA
when operating in the 16 mode (see definition under INTA).
n.c.
21, 49,
52, 54,
55, 65
-
1, 10,
20, 21,
30, 40,
41, 49,
52, 60,
61, 71,
80
-
Not connected.
RESET
(RESET)
37
27
53
I
Reset. In the 16 mode, a logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output and the
receiver input will be disabled during reset time. (See Section 7.11
“SC16C554/554D external reset conditions” for initialization details.)
When 16/68 is a logic 0 (68 mode), this pin functions similarly, but as
an inverted reset interface signal, RESET.
RIA, RIB,
RIC, RID
8, 28,
42, 62
63, 19,
30, 50
18, 43,
58, 3
I
Ring Indicator (Active-LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on this pin indicates
the modem has received a ringing signal from the telephone line. A
logic 1 transition on this input pin will generate an interrupt.
RTSA, RTSB, 14, 22,
RTSC, RTSD 48, 56
5, 13,
36, 44
26, 35,
66, 75
O
Request to Send (Active-LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin will be set to
a logic 1. This pin only affects the transmit and receive operations
when Auto RTS function is enabled via the Enhanced Feature
Register (EFR[6]) for hardware flow control operation.
-
-
I
Read/Write strobe. This function is associated with the 68 mode
only. This pin provides the combined functions for Read or Write
strobes.
R/W
18
Logic 1 = Read from UART register selected by CS and A0-A4.
Logic 0 = Write to UART register selected by CS and A0-A4.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
11 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2:
Pin description…continued
Symbol
Pin
PLCC68 LQFP64 LQFP80
Type
Description
RXA, RXB,
RXC, RXD
7, 29,
41, 63
62, 20,
29, 51
17, 44,
57, 4
I
Receive data input RXA-RXD. These inputs are associated with
individual serial channel data to the SC16C554/554D. The RX signal
will be a logic 1 during reset, idle (no data), or when the transmitter is
disabled. During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input internally.
RXRDY
38
-
54
O
Receive Ready (Active-LOW). RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDYA-RXRDYD. A
logic 0 indicates receive data ready status, i.e., the RHR is full, or the
FIFO has one or more RX characters available for unloading. This
pin goes to a logic 1 when the FIFO/RHR is empty, or when there are
no more characters available in either the FIFO or RHR. Individual
channel RX status is read by examining individual internal registers
via CS and A0-A4 pin functions.
TXA, TXB,
TXC, TXD
17, 19,
51, 53
8, 10,
39, 41
29, 32,
69, 72
O
Transmit data A, B, C, D. These outputs are associated with
individual serial transmit channel data from the SC16C554/554D.
The TX signal will be a logic 1 during reset, idle (no data), or when
the transmitter is disabled. During the local loop-back mode, the TX
output pin is disabled and TX data is internally connected to the
UART RX input.
TXRDY
39
-
55
O
Transmit Ready (Active-LOW). TXRDY contains the wire-ORed
status of all four transmit channel FIFOs, TXRDYA-TXRDYD. A
logic 0 indicates a buffer ready status, i.e., at least one location is
empty and available in one of the TX channels (A-D). This pin goes to
a logic 1 when all four channels have no more empty locations in the
TX FIFO or THR. Individual channel TX status can be read by
examining individual internal registers via CS and A0-A4 pin
functions.
VCC
13, 30,
47, 64
4, 21,
35, 52
5, 25,
45, 65
I
Power supply inputs.
XTAL1
35
25
50
I
Crystal or external clock input. Functions as a crystal input or as
an external clock input. A crystal can be connected between this pin
and XTAL2 to form an internal oscillator circuit (see Figure 7).
Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See Section 6.10 “Programmable baud
rate generator”.)
XTAL2
36
26
51
O
Output of the crystal oscillator or buffered clock. (See also
XTAL1.) Crystal oscillator output or buffered clock output.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
12 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6. Functional description
The SC16C554/554D provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character. Data integrity is insured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex,
especially when manufactured on a single integrated silicon chip. The
SC16C554/554D represents such an integration with greatly enhanced features. The
SC16C554/554D is fabricated with an advanced CMOS process to achieve low drain
power and high speed requirements.
The SC16C554/554D is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554/554D is
designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C554/554D by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software flow
control is uniquely provided for maximum data throughput performance, especially
when operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554/554DAI68 combines the package interface modes of the 16C454/554
and 68C454/554 series on a single integrated chip. The 16 mode interface is
designed to operate with the Intel-type of microprocessor bus, while the 68 mode is
intended to operate with Motorola and other popular microprocessors. Following a
reset, the SC16C554/554DAI68 is downward compatible with the 16C454/554 or the
68C454/554, dependent on the state of the interface mode selection pin, 16/68.
The SC16C554/554D is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum
speed is 3 Mbit/s).
The rich feature set of the SC16C554/554D is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO
trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,
modem interface controls, and a sleep mode are all standard features. In the
16 mode, INTSEL and MCR[3] can be configured to provide a software controlled or
continuous interrupt capability. Due to pin limitations of the 64-pin package, this
feature is offered by two different LQFP64 packages. The SC16C554D operates in
the continuous interrupt enable mode by bonding INTSEL to VCC internally. The
SC16C554 operates in conjunction with MCR[3] by bonding INTSEL to GND
internally.
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.1 Interface options
Two user interface modes are selectable for the PLCC68 package. These interface
modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature
corresponds to the early 16C454/554 and 68C454/554 package interfaces
respectively.
6.2 The 16 mode interface
The 16 mode configures the package interface pins for connection as a standard
16 series (Intel) device and operates similar to the standard CPU interface available
on the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with
individual chip select (CSx) pins, as shown in Table 3.
Table 3:
Serial port channel selection, 16 mode interface
CSA
CSB
CSC
CSD
1
1
1
1
none
0
1
1
1
A
1
0
1
1
B
1
1
0
1
C
1
1
1
0
D
UART channel
6.3 The 68 mode interface
The 68 mode configures the package interface pins for connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C554/554D decodes two additional addresses,
A3-A4, to select one of the four UART ports. The A3-A4 address decode function is
used only when in the 68 mode (16/68 = logic 0), and is shown in Table 4.
Table 4:
Serial port channel selection, 68 mode interface
CS
A4
A3
UART channel
1
n/a
n/a
none
0
0
0
A
0
0
1
B
0
1
0
C
0
1
1
D
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Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.4 Internal registers
The SC16C554/554D provides 17 internal registers for monitoring and control. These
registers are shown in Table 5. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C554
features and capabilities, the SC16C554/554D offers an enhanced feature register
set (EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control.
Register functions are more fully described in the following paragraphs.
Table 5:
A2
Internal registers decoding
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
Interrupt Enable Register
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
1
Line Control Register
Line Control Register
1
0
0
Modem Control Register
Modem Control Register
1
0
1
Line Status Register
n/a
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Baud rate register set
(DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
0
Enhanced Feature Register
Enhanced Feature Register
1
0
0
Xon1 word
Xon1 word
1
0
1
Xon2 word
Xon2 word
1
1
0
Xoff1 word
Xoff1 word
1
1
1
Xoff2 word
Xoff2 word
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF’ (HEX).
6.5 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 6:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
1
1
4
1
4
4
8
4
8
8
12
8
14
14
14
10
6.6 Hardware flow control
When automatic hardware flow control is enabled, the SC16C554/554D monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local
buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS)
and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating
a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C554/554D will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is resumed after the CTS input
returns to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C554/554D will continue to accept data until the receive FIFO is full.
6.7 Software flow control
When software flow control is enabled, the SC16C554/554D compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C554/554D will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C554/554D will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C554/554D will resume operation
and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C554/554D compares two consecutive receive characters with two software
flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C554/554D automatically sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The SC16C554/554D sends the Xoff1,2
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
characters as soon as received data passes the programmed trigger level. To clear
this condition, the SC16C554/554D will transmit the programmed Xon1,2 characters
as soon as receive data drops below the programmed trigger level.
6.8 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C554/554D compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 8) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.9 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, if the transmitter interrupt is enabled, the
SC16C554/554D will issue an interrupt to indicate that the Transmit Holding Register
is empty. This interrupt must be serviced prior to continuing operations. The LSR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C554/554D FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-State interrupt operation. This is accomplished by
INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0,
MCR[3] controls the 3-State interrupt outputs, INTA-INTD. When INTSEL is a logic 1,
MCR[3] has no effect on the INTA-INTD outputs, and the package operates with
interrupt outputs enabled continuously.
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.10 Programmable baud rate generator
The SC16C554/554D supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
X1
1.8432 MHz
C1
47 pF
XTAL2
XTAL1
XTAL2
XTAL1
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as
required for supporting a 5 Mbit/s data rate. The SC16C554/554D can be configured
for internal or external clock operation. For internal clock oscillator operation, an
industry standard microprocessor crystal (parallel resonant/22-33 pF load) is
connected externally between the XTAL1 and XTAL2 pins (see Figure 7).
Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table 7).
X1
1.8432 MHz
C2
100 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa169
Fig 7. Crystal oscillator connection.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate.
Table 7:
Baud rate generator programming table using a 7.3728 MHz clock
Output baud rate
User
16× clock divisor
Decimal
HEX
DLM
program value
(HEX)
200
2304
900
09
1200
384
180
01
80
2400
192
C0
00
C0
4800
96
60
00
60
9600
48
30
00
30
19.2 k
24
18
00
18
38.4 k
12
0C
00
0C
76.8 k
6
06
00
06
153.6 k
3
03
00
03
230.4 k
2
02
00
02
460.8 k
1
01
00
01
00
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DLL
program value
(HEX)
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.11 DMA operation
The SC16C554/554D FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5,6] provide an indication when the transmitter is empty
or has an empty location(s). The user can optionally operate the transmit and receive
FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled
and the DMA mode is de-activated (DMA Mode 0), the SC16C554/554D activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is
activated (DMA Mode 1), the user takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the preset trigger
level. In this mode, the SC16C554/554D sets the interrupt output pin when characters
in the transmit FIFOs are below the transmit trigger level, or the characters in the
receive FIFOs are above the receive trigger level.
6.12 Sleep mode
The SC16C554/554D is designed to operate with low power consumption. A special
sleep mode is included to further reduce power consumption when the chip is not
being used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C554/554D
enters the sleep mode, but resumes normal operation when a start bit is detected, a
change of state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit
data is provided by the user. If the sleep mode is enabled and the SC16C554/554D is
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case,
the seep mode will not be entered while an interrupt(s) is pending. The
SC16C554/554D will stay in the sleep mode of operation until it is disabled by setting
IER[4] to a logic 0.
6.13 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OP1 and OP2 in the MCR register (bits 2-3) control the
modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem DSR and CTS inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 8). The CTS, DSR,
CD, and RI are disconnected from their normal modem control input pins, and instead
are connected internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered
into the transmit holding register via the user data bus interface, D0-D7. The transmit
UART serializes the data and passes the serial data to the receive UART via the
internal loop-back connection. The receive UART converts the serial data back into
parallel data that is then made available at the user data interface D0-D7. The user
optionally compares the received data to the initial transmitted data for verifying
error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
RECEIVE
FIFO
REGISTERS
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
A0–A2
CSA-CSD
TXA-TXD
FLOW
CONTROL
LOGIC
IR
ENCODER
MCR[4] = 1
D0–D7
IOR
IOW
RESET
TRANSMIT
SHIFT
REGISTER
RECEIVE
SHIFT
REGISTER
RXA-RXD
IR
DECODER
RTSA-RTSD
CTSA-CTSD
DTRA-DTRD
MODEM
CONTROL
LOGIC
DSRA-DSRD
OP1A-OP1D
INTA-INTD
TXRDY
RXRDY
RIA-RID
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
OP2A-OP2D
CDA-CDD
002aaa170
XTAL1
XTAL2
Fig 8. Internal loop-back mode diagram (16 mode).
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
RECEIVE
FIFO
REGISTERS
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
A0–A4
CS
TXA-TXD
FLOW
CONTROL
LOGIC
IR
ENCODER
MCR[4] = 1
D0–D7
R/W
RESET
TRANSMIT
SHIFT
REGISTER
RECEIVE
SHIFT
REGISTER
RXA-RXD
IR
DECODER
RTSA-RTSD
16/68
CTSA-CTSD
DTRA-DTRD
MODEM
CONTROL
LOGIC
DSRA-DSRD
OP1A-OP1D
IRQ
TXRDY
RXRDY
RIA-RID
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
OP2A-OP2D
CDA-CDD
002aaa700
XTAL1
XTAL2
Fig 9. Internal loop-back mode diagram (68 mode).
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7. Register descriptions
Table 8 details the assigned bit functions for the SC16C554/554D internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 8:
SC16C554/554D internal registers
Shaded bits are only accessible when EFR[4] is set.
A2 A1 A0 Register Default[1] Bit 7
General Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set[2]
0
0
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
IER
00
CTS
RTS
Xoff
interrupt interrupt interrupt
Sleep
mode
modem
status
interrupt
receive
transmit
line status holding
interrupt
register
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
reserved reserved
DMA
mode
select
XMIT
RCVR
FIFO reset FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
1
LCR
00
divisor
latch
enable
set
break
set parity even
parity
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
0
MCR
00
0
IR
enable
0
loop back OP2,
INTx
enable
OP1
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR
X0
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
∆CTS
1
1
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Special Register
INT
priority
bit 3
Set[3]
0
0
0
DLL
0
0
1
DLM
Enhanced Register
Set[4]
0
1
0
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4:7],
ISR[4:5],
MCR[6]
Cont-3
Tx, Rx
Control
Cont-2 Tx, Cont-1
Rx Control Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
0
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
1
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
[1]
[2]
[3]
[4]
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
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SC16C554/554D
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C554/554D and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On
the falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16× clock rate. After 7-1⁄2 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA-INTD output pins in the 16 mode, or on wire-OR IRQ
output pin in the 68 mode.
Table 9:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C554/554D issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C554/554D issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See
Section 6.7 “Software flow control” for details.
4
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.12 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 9:
Interrupt Enable Register bits description…continued
Bit
Symbol
Description
2
IER[2]
Receive Line Status interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default
condition).
Logic 1 = Enable the transmitter empty interrupt.
0
IER[0]
Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
7.2.1
IER versus Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
• FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
• The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C554/554D in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
•
•
•
•
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
• LSR[7] will indicate any FIFO data errors.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive
FIFO trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when there are one or more FIFO locations empty. The
receive interrupt is set when the receive FIFO fills to the programmed trigger level.
However, the FIFO continues to fill regardless of the programmed level until the FIFO
is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
7.3.2
FIFO mode
Table 10:
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7:6]
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5:4
FCR[5:4]
Not used; initialized to logic 0.
3
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C554/554D is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C554/554D is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive FIFO,
the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a
logic 1 when there are no more characters in the receiver.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 10:
Bit
FIFO Control Register bits description…continued
Symbol
Description
Transmit operation in mode ‘1’: When the SC16C554/554D is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one
or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C554/554D is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 11:
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0
0
1
0
1
4
1
0
8
1
1
14
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.4 Interrupt Status Register (ISR)
The SC16C554/554D provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
2
0
0
0
1
0
0
RXRDY (Received Data
Ready)
2
0
0
1
1
0
0
RXRDY (Receive Data
time-out)
3
0
0
0
0
1
0
TXRDY (Transmitter
Holding Register Empty)
4
0
0
0
0
0
0
MSR (Modem Status
Register)
5
0
1
0
0
0
0
RXRDY (Received Xoff
signal) / Special character
6
1
0
0
0
0
0
CTS, RTS change of state
Table 13:
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5:4
ISR[5:4]
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3:1
ISR[3:1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
0
ISR[0]
INT status.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5
LCR[5]
Set parity. If the parity bit is enabled, LCR[5] selects the forced
parity format. Programs the parity conditions (see Table 15).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data.
4
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be
programmed to check the same format (normal default
condition).
Logic 1 = EVEN Parity is generated by forcing an even number
of logic 1s in the transmitted data. The receiver must be
programmed to check the same format.
3
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission,
receiver checks the data and parity for transmission errors.
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 16).
Logic 0 or cleared = default condition.
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
Logic 0 or cleared = default condition.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 15:
LCR[5] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
0
0
1
ODD parity
0
1
1
EVEN parity
1
0
1
force parity ‘1’
1
1
1
forced parity ‘0’
Table 16:
LCR[2] stop bit length
LCR[2]
Word length
0
5, 6, 7, 8
1
1
5
1-1⁄2
1
6, 7, 8
2
Table 17:
Stop bit length (bit times)
LCR[1-0] word length
LCR[1]
LCR[0]
Word length
0
0
5
0
1
6
1
0
7
1
1
8
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 18:
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
Reserved; set to 0.
6
MCR[6]
IR enable.
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
5
MCR[5]
Reserved; set to 0.
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, CD, and RI are disconnected from the SC16C554/554D I/O
pins. Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 8). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OP2, INTx enable. Used to control the modem CD signal in the
loop-back mode.
Logic 0 = Forces INTA-INTD outputs to the 3-State mode during
the 16 mode (normal default condition). In the loop-back mode,
sets OP2 (CD) internally to a logic 1.
Logic 1 = Forces the INTA-INTD outputs to the active mode during
the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a
logic 0.
2
MCR[2]
OP1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal via OP1.
1
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
Automatic RTS may be used for hardware flow control by enabling
EFR[6]. See Table 21.
0
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C554/554D and
the CPU.
Table 19:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the transmit FIFO and transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 19:
Line Status Register bits description…continued
Bit
Symbol
Description
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C554/554D is connected.
Four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a control input from the modem changes state. These bits
are set to a logic 0 whenever the CPU reads this register.
Table 20:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (Active-HIGH, logical 1). Normally this bit is the complement of the
CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the
MCR register.
6
MSR[6]
RI (Active-HIGH, logical 1). Normally this bit is the complement of the RI
input. In the loop-back mode this bit is equivalent to the OP1 bit in the
MCR register.
5
MSR[5]
DSR (Active-HIGH, logical 1). Normally this bit is the complement of the
DSR input. In loop-back mode this bit is equivalent to the DTR bit in the
MCR register.
4
MSR[4]
CTS. CTS functions as hardware flow control signal input if it is enabled
via EFR[7]. The transmit holding register flow control is enabled/disabled
by MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the
CTS pin will stop SC16C554/554D transmissions as soon as current
character has finished transmission. Normally MSR[4] is the complement
of the CTS input. However, in the loop-back mode, this bit is equivalent to
the RTS bit in the MCR register.
3
MSR[3]
∆CD [1]
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
2
MSR[2]
∆RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C554/554D has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
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Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 20:
Modem Status Register bits description…continued
Bit
Symbol
Description
1
MSR[1]
∆DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C554/554D provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 21:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Auto CTS. Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Auto RTS. Automatic RTS may be used for hardware flow control by
enabling EFR[6]. When Auto RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return
to a logic 0 when data is unloaded below the next lower trigger level.
The state of this register bit changes with the status of the hardware flow
control. RTS functions normally when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic RTS flow control.
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Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 21:
Enhanced Feature Register bits description…continued
Bit
Symbol
Description
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C554/554D
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be
set to indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this
feature is enabled, the normal software flow control must be disabled
(EFR[3-0] must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7:4], ISR[5:4], and
MCR[6] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new
values. This feature prevents existing software from altering or
overwriting the SC16C554/554D enhanced functions.
Logic 0 = Disable (normal default condition).
Logic 1 = Enable.
3:0
EFR[3:0]
Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See Table 22.
Software flow control functions[1]
Table 22:
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
1
1
Transmit Xon2/Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
[1]
When using software flow control the Xon/Xoff characters cannot be used for data transfer.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
34 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.11 SC16C554/554D external reset conditions
Table 23:
Reset state for registers
Register
Reset state
IER
IER[7:0] = 0
ISR
ISR[7:1] = 0; ISR[0] = 1
LCR
LCR[7:0] = 0
MCR
MCR[7:0] = 0
LSR
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR
MSR[7:4] = input signals; MSR[3:0] = 0
FCR
FCR[7:0] = 0
EFR
EFR[7:0] = 0
Table 24:
Reset state for outputs
Output
Reset state
TXA, TXB, TXC, TXD
HIGH
RTSA, RTSB, RTSC, RTSD
HIGH
DTRA, DTRB, DTRC, DTRD
HIGH
RXRDY
HIGH
TXRDY
LOW
8. Limiting values
Table 25: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Max
Unit
VCC
supply voltage
-
7
V
Vn
voltage at any pin
GND − 0.3
VCC + 0.3
V
Tamb
operating temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ptot(pack)
total power dissipation per
package
-
500
mW
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Min
Rev. 05 — 10 May 2004
35 of 55
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Nom
Max
Min
Nom
Max
Min
Nom
Max
LOW-level clock input voltage
−0.3
-
0.45
−0.3
-
0.6
−0.5
-
0.6
V
VIH(CK)
HIGH-level clock input voltage
1.8
-
VCC
2.4
-
VCC
3.0
-
VCC
V
VIL
LOW-level input voltage
(except X1 clock)
−0.3
-
0.65
−0.3
-
0.8
−0.5
-
0.8
V
VIH
HIGH-level input voltage
(except X1 clock)
1.6
-
-
2.0
-
-
2.2
-
-
V
VOL
LOW-level output voltage
on all outputs[1]
IOL = 5 mA
(databus)
-
-
-
-
-
-
-
-
0.4
V
IOL = 4 mA
(other outputs)
-
-
-
-
-
0.4
-
-
-
V
IOL = 2 mA
(databus)
-
-
0.4
-
-
-
-
-
-
V
IOL = 1.6 mA
(other outputs)
-
-
0.4
-
-
-
-
-
-
V
IOH = −5 mA
(databus)
-
-
-
-
-
-
2.4
-
-
V
IOH = −1 mA
(other outputs)
-
-
-
2.0
-
-
-
-
-
V
IOH = −800 µA
(data bus)
1.85
-
-
-
-
-
-
-
-
V
IOH = −400 µA
(other outputs)
1.85
-
-
-
-
-
-
-
-
V
-
-
±10
-
-
±10
-
-
±10
µA
-
-
±30
-
-
±30
-
-
±30
µA
-
-
4.5
-
-
6
-
-
6
mA
-
1
-
-
1
-
-
1
-
mA
-
-
5
-
-
5
-
-
5
pF
500
-
-
500
-
-
500
-
-
kΩ
HIGH-level output voltage
36 of 55
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ILIL
LOW-level input leakage
current
ICL
clock leakage
ICC
supply current
f = 5 MHz
current[2]
ICCsleep
sleep
Ci
input capacitance
Rpu(int)
[1]
[2]
[3]
internal pull-up
resistance[3]
2.5 V
3.3 V
Except x2, VOL = 1 V typical.
When using crystal oscillator. The use of an external clock will increase the sleep current.
Refer to Table 2 “Pin description” on page 9 for a listing of pins having internal pull-up resistors.
5.0 V
Unit
SC16C554/554D
Min
VIL(CK)
VOH
Conditions
Philips Semiconductors
Parameter
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 05 — 10 May 2004
Symbol
9. Static characteristics
9397 750 13132
Product data
Table 26: DC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
10. Dynamic characteristics
Table 27: AC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ± 10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
10
-
6
-
6
-
ns
-
48
-
80
80
MHz
t1w, t2w
clock pulse duration
t3w
oscillator/clock frequency
t6s
address set-up time
0
-
0
-
0
-
ns
t6h
address hold time
0
-
0
-
0
-
ns
t7d
IOR delay from chip select
10
-
10
-
10
-
ns
t7w
IOR strobe width
77
-
26
-
23
-
ns
t7h
chip select hold time from IOR
0
-
0
-
0
-
ns
t9d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
[1]
25 pF load
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
20
-
20
-
15
-
ns
0
-
0
-
0
-
ns
25
-
25
-
20
-
ns
[2]
t13w
IOW strobe width
t13h
chip select hold time from IOW
t15d
write cycle delay
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from Modem
input
25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from IOR
25 pF load
-
100
-
24
-
23
ns
-
1
-
1
-
1
Rclk
25 pF load
-
100
-
29
-
28
ns
[3]
t20d
delay from stop to set interrupt
t21d
delay from IOR to reset interrupt
t22d
delay from start to set interrupt
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit start
8
24
8
24
8
24
Rclk
t24d
delay from IOW to reset interrupt
-
100
-
45
-
40
ns
t25d
delay from stop to set RXRDY
-
1
-
1
-
1
Rclk
t26d
delay from IOR to reset RXRDY
-
100
-
45
-
40
ns
t27d
delay from IOW to set TXRDY
-
100
-
45
-
40
ns
t28d
delay from start to reset TXRDY
-
8
-
8
-
8
Rclk
t30s
address set-up time
10
-
10
-
10
-
ns
t30w
chip select strobe width
90
-
26
-
23
-
ns
t30h
address hold time
15
-
15
-
15
-
ns
t30d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t31d
delay from CS to data
25 pF load
-
90
-
26
-
23
ns
t31h
data disable time
25 pF load
-
15
-
15
-
15
ns
t32s
write strobe set-up time
10
-
10
-
10
-
ns
t32h
write strobe hold time
10
-
10
-
10
-
ns
25 pF load
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
37 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 27: AC electrical characteristics…continued
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ± 10%, unless otherwise specified.
Symbol
Parameter
Conditions
t32d
write cycle delay
2.5 V
[3]
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
25
-
25
-
20
-
ns
t33s
data set-up time
20
-
15
-
15
-
ns
t33h
data hold time
15
-
5
-
5
-
ns
tRESET
Reset pulse width
200
-
40
-
40
-
ns
1
216
1
216
1
216
N
baud rate divisor
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
1
IOWstrobe max = -------------------------------------2 ( Baudrate max )
−1
−1
−1
Rclk
= 333 ns (for Baudratemax = 1.5 Mbit/s)
= 1 µs (for Baudratemax = 460.8 kbit/s)
= 4 µs (for Baudratemax = 115.2 kbit/s)
[3]
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1, clock cycle.
10.1 Timing diagrams
A0–A4
t30s
t30w
t30h
t30d
CS
t32s
t31h
R/W
t31d
D0–D7
002aaa210
Fig 10. General read timing in 68 mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
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SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
A0–A4
t30s
t30w
t30h
CS
t32s
t32h
t32d
R/W
t33h
t33s
D0–D7
002aaa211
Fig 11. General write timing in 68 mode.
t6h
VALID
ADDRESS
A0–A2
t6s
t13h
ACTIVE
CS
t13d
t15d
t13w
IOW
ACTIVE
t16h
t16s
D0–D7
DATA
002aaa171
Fig 12. General write timing in 16 mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
39 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
t6h
VALID
ADDRESS
A0–A2
t6s
t7h
ACTIVE
CS
t7d
t9d
t7w
IOR
ACTIVE
t12h
t12d
D0–D7
DATA
002aaa172
Fig 13. General read timing in 16 mode.
IOW
ACTIVE
t17d
RTS
DTR
CHANGE OF STATE
CHANGE OF STATE
CD
CHANGE OF STATE
CTS
CHANGE OF STATE
DSR
t18d
INT
t18d
ACTIVE
ACTIVE
ACTIVE
t19d
IOR
ACTIVE
ACTIVE
ACTIVE
t18d
RI
CHANGE OF STATE
002aaa352
Fig 14. Modem input/output timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
40 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
t 2w
t 1w
EXTERNAL
CLOCK
002aaa112
t 3w
Fig 15. External clock timing.
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
t20d
7 DATA BITS
ACTIVE
INT
t21d
ACTIVE
IOR
16 BAUD RATE CLOCK
002aaa113
Fig 16. Receive timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
41 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa114
Fig 17. Receive ready timing in non-FIFO mode.
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa115
Fig 18. Receive ready timing in FIFO mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
42 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
ACTIVE TX READY
INT
t22d
t24d
t23d
IOW
ACTIVE
ACTIVE
16 BAUD RATE CLOCK
002aaa116
Fig 19. Transmit timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
43 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
START
BIT
TX
DATA BITS (5–8)
D0
IOW
ACTIVE
D0–D7
BYTE #1
PARITY
BIT
D1
D2
D3
D4
D5
D6
STOP
BIT
NEXT
DATA
START
BIT
D7
TRANSMITTER READY
t28d
t27d
ACTIVE
TXRDY
TRANSMITTER
NOT READY
002aaa345
Fig 20. Transmit ready timing in non-FIFO mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
44 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
IOW
ACTIVE
t28d
D0–D7
BYTE #16
t27d
TXRDY
FIFO FULL
002aaa346
Fig 21. Transmit ready timing in FIFO mode (DMA mode ‘1’).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
45 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
TX DATA
0
STOP
START
UART FRAME
DATA BITS
1
0
1
0
0
1
1
0
1
IRTXA–IRTXD
TX
BIT
TIME
1/2 BIT TIME
3/16 BIT TIME
002aaa212
Fig 22. Infrared transmit timing.
IRRXA–IRRXD
RX
BIT
TIME
1
0
1
0
0
DATA BITS
1
1
0
1
STOP
0
START
RX DATA
0-1 16X CLOCK DELAY
UART FRAME
002aaa213
Fig 23. Infrared receive timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
46 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
11. Package outline
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD
eE
y
X
60
A
44
43 Z E
61
bp
b1
w M
68
1
E
HE
pin 1 index
A
e
A4 A1
(A 3)
β
9
Lp
27
k
detail X
10
26
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
UNIT A
D(1) E(1)
e
HD
A3
eD
eE
bp b1
max.
min.
4.57
4.19
mm
inches
0.51
0.180
0.02
0.165
0.53
0.33
0.81
0.66
HE
k
23.62 23.62 25.27 25.27 1.22
24.33 24.33
1.27
22.61 22.61 25.02 25.02 1.07
24.13 24.13
0.25
3.3
0.01
0.021 0.032 0.958 0.958
0.05
0.13
0.013 0.026 0.950 0.950
0.93
0.89
0.93
0.89
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.995 0.995 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.985 0.985 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT188-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 24. PLCC68 package outline (SOT188-2).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
47 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 25. LQFP64 package outline (SOT314-2).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
48 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y
X
A
60
41
40 Z E
61
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
80
21
1
detail X
20
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.16
0.04
1.5
1.3
0.25
0.27
0.13
0.18
0.12
12.1
11.9
12.1
11.9
0.5
HD
HE
L
Lp
v
w
y
1
0.75
0.30
0.2
0.15
0.1
14.15 14.15
13.85 13.85
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT315-1
136E15
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 26. LQFP80 package outline (SOT315-1).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
49 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
50 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
12.5 Package related soldering information
Table 28:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
Reflow[2]
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
suitable
recommended[7]
SSOP, TSSOP, VSO, VSSOP
not
CWQCCN..L[8],
not suitable
[1]
[2]
PMFP[9],
WQCCN..L[8]
suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Wave
Rev. 05 — 10 May 2004
51 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
[3]
[4]
[5]
[6]
[7]
[8]
[9]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
Hot bar soldering or manual soldering is suitable for PMFP packages.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
52 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
13. Revision history
Table 29:
Revision history
Rev Date
05
20040510
CPCN
Description
-
Product data (9397 750 13132). Supersedes data of 19 June 2003 (9397 750 11616).
Modifications:
•
Figure 6 “LQFP80 pin configuration.”: change pin 49 from “CSC” to “n.c.”; change pin 74
from “D6” to “INTD”.
•
Table 2 “Pin description”
– INTSEL description, last sentence: change from “The ST16C654IB64 ...” to “The
SC16C654IB64 ...”
– RESET (RESET) description, last sentence: change from “... this pin functions similarly,
bus as an inverted reset interface signal ...” to “... this pin functions similarly, but as an
inverted reset interface signal ...”
•
Section 6.4 “Internal registers”, first sentence: change from “... provides 15 internal
registers...” to “... provides 17 internal registers...”
•
Section 6.13 “Loop-back mode”
– First paragraph:
– change from “MCR signals DTR and RTS (bits 0-1) are used to control the modem
CTS and DSR inputs, respectively.” to “MCR signals DTR and RTS (bits 0-1) are used
to control the modem DSR and CTS inputs, respectively.”
– Change from “...are connected internally to DTR, RTS, OP1 and OP2.” to “...are
connected internally to RTS, DTR, OP2 and OP1.”
– Figure 8 and Figure 9 modified: signals to/from Modem Control Logic block corrected.
•
•
Table 9 “Interrupt Enable Register bits description”: description of bit 2, IER[2], modified.
Table 21 “Enhanced Feature Register bits description”: description of bit 6, EFR[6], and of
bit 4, EFR[4], modified.
04
20030619
-
Product data (9397 750 11616); ECN 853-2376 30028 of 16 June 2003.
03
20030415
-
Product data (9397 750 11375); ECN 853-2376 29797 of 11 April 2003.
02
20030313
-
Product data (9397 750 11002); ECN 853-2376 29627 of 10 March 2003.
01
20020910
-
Product data; (9397 750 09213); ECN 853-2376 28891 of 10 September 2002.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
53 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
14. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13132
Rev. 05 — 10 May 2004
54 of 55
SC16C554/554D
Philips Semiconductors
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Contents
1
2
3
4
5
5.1
5.1.1
5.1.2
5.1.3
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
9
10
10.1
11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PLCC68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . 13
Interface options . . . . . . . . . . . . . . . . . . . . . . . 14
The 16 mode interface . . . . . . . . . . . . . . . . . . 14
The 68 mode interface . . . . . . . . . . . . . . . . . . 14
Internal registers. . . . . . . . . . . . . . . . . . . . . . . 15
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 15
Hardware flow control . . . . . . . . . . . . . . . . . . . 16
Software flow control . . . . . . . . . . . . . . . . . . . 16
Special feature software flow control . . . . . . . 17
Hardware/software and time-out interrupts. . . 17
Programmable baud rate generator . . . . . . . . 18
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 19
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 19
Register descriptions . . . . . . . . . . . . . . . . . . . 22
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 23
Interrupt Enable Register (IER) . . . . . . . . . . . 23
IER versus Receive FIFO interrupt
mode operation . . . . . . . . . . . . . . . . . . . . . . . 24
IER versus Receive/Transmit FIFO polled
mode operation . . . . . . . . . . . . . . . . . . . . . . . 24
FIFO Control Register (FCR) . . . . . . . . . . . . . 25
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupt Status Register (ISR) . . . . . . . . . . . . 27
Line Control Register (LCR) . . . . . . . . . . . . . . 28
Modem Control Register (MCR) . . . . . . . . . . . 30
Line Status Register (LSR) . . . . . . . . . . . . . . . 31
Modem Status Register (MSR). . . . . . . . . . . . 32
Scratchpad Register (SPR) . . . . . . . . . . . . . . 33
Enhanced Feature Register (EFR) . . . . . . . . . 33
SC16C554/554D external reset conditions. . . 35
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 35
Static characteristics. . . . . . . . . . . . . . . . . . . . 36
Dynamic characteristics . . . . . . . . . . . . . . . . . 37
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 38
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 47
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 10 May 2004
Document order number: 9397 750 13132
12
12.1
12.2
12.3
12.4
12.5
13
14
15
16
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
50
50
51
51
53
54
54
54
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