For Information Equipment MN89201 VGA-NTSC Scan Converter Overview The MN89201 converts PC/AT VGA (640 × 480) display data into an NTSC video signal without requiring an external frame memory. It uses filtering to eliminate flicker and produce a high-quality television image. Note: PC/AT and VGA are registered trademarks of International Business Machines Corporation. Features Conversion of PC/AT VGA (640 × 480) display data into NTSC video signal • 8-bit inputs for VGA R, G, and B signals Horizontal frequency: 31.5 kHz Vertical frequency: 59.94 Hz • Conversion of non-interlaced display to interlaced display Choice of readout clocks for NTSC output Choice 1: Choice of clock that has arbitrary frequency and synchronizes with VGA clock External voltage-controlled oscillator in addition to built-in phase-locked loop • Conversion from RGB to YCrCb (4:2:2) format Choice 2: Choice of clock that has arbitrary frequency and does not synchronize with VGA clock External oscillator • Data output in NTSC display format (YCrCb24 or YCrCb16-bit) Choice 3: Clock with half frequency of the VGA-dot-clock Flicker prevention Choose the clock matching the NTSC encoder. • Built-in phase-locked loop for synchronizing VGA and NTSC data clocks • Choice of line filters with 3 taps for preventing flicker Processing with only line memory • No need for external VRAM • All processing completes within built-in line memory Applications Point-of-sale terminals, Factory automation terminals, word processors, and other terminals The MN89201 offers high-quality NTSC-compatible output from a compact configuration. MN89201 For Information Equipment 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS VDD YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 VSS VDD YOUT1 YOUT0 CROUT7 CROUT6 CROUT5 CROUT4 VSS VDD CROUT3 CROUT2 CROUT1 CROUT0 CBOUT7 CBOUT6 VSS VDD CBOUT5 CBOUT4 CBOUT3 CBOUT2 CBOUT1 CBOUT0 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSS VDD AEN XRD XWE REGLIN RA3 RA2 RA1 RA0 DB7 DB6 DB5 DB4 VSS VDD DB3 DB2 DB1 DB0 VSS VDD RESET MODSET1 MODSET0 MOD422F MODVFIL MODHFIL MODPIN MINTEST MON1 MON0 TEST0 TEST1 TEST2 TEST3 TEST4 BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 GIN0 GIN1 GIN2 GIN3 GIN4 GIN5 GIN6 GIN7 RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 XVSYNCIN XHSYNCIN DOTCLK (TOP VIEW) QFH128-P-1818 Note: Never leave VDD and VSS pins open. VDD VSS RDCLK XENCRST XBLANK XVSYNC XHSYNC RD2CLK VDD VSS OEON OEOP VDD VSS XOO OSXIN VDD VSS MEMOUT0 MEMOUT1 MEMOUT2 MEMOUT3 MEMOUT4 MEMOUT5 VDD VSS MEMOUT6 MEMOUT7 MODST MODCHAV MODCRCB SXRST For Information Equipment MN89201 Block Diagram • RDCLK from an external VCO clock synchronized with VGA clock 8 8 8 Latch RGB-YCrCb converter DOTCLK Control block counters, pulse generator, etc. XVSYNCIN XHSYNCIN DB[7:0] RA[3:0] CS (AEN) WR RD 8 8 8 Conversion from non-interlaced to interlaced display Flicker elimination block 8 4 Registers PLL XVSYNC XHSYNC BLANK RD2CLK RDCLK 1/N OSC I/F OEON OEOP OSXIN Y Cr Cb Coding interface R G B XOO lead VCO lag • RDCLK from VGA clock 8 8 8 Latch RGB-YCrCb converter DOTCLK Control block counters, pulse generator, etc. XVSYNCIN XHSYNCIN DB[7:0] RA[3:0] CS (AEN) WR RD 8 4 Registers PLL 8 8 8 Conversion from non-interlaced to interlaced display Flicker elimination block 1/N OSC I/F Y Cr Cb Coding interface R G B XVSYNC XHSYNC BLANK RD2CLK RDCLK MN89201 For Information Equipment Pin Descriptions Pin No. Symbol I/O 3 AEN I Function Description Chip select signal "L" level: Register access enabled "H" level: Register access disabled 4 XRD I Read control signal "L" level: Read enabled 5 XWE I Write control signal "L" level: Write enabled 6 REGLIN I Register address mode specification "H" level: Obtain register address from RA[3:0] "L" level: Obtain register address from address register In the latter case, the address of the parameter/mode register are specified by the address register . Address register: 0H (4-bit decode) Data register: 1H (4-bit decode) 7 to 10 RA[3:0] I Register address specification 11 to 14 DB[7:0] I Host data bus RESET I MN89201 reset signal 17 to 20 23 Active "H" This signal initializes internal registers to their default values and resets internal synchronization counters. 24 ,25 MODSET[1:0] I Synchronization mode specification pins These specify the RDCLK synchronization mode for output signals to the NTSC encoder (1:0) 0 0: Use an external VCO clock signal synchronized with the VGA clock signal for RDCLK. The XH, XVSYNC, XBLANK, and XENRST signals are generated inside the MN89201 and are outputted. (synchronous) 0 1: Use an external oscillator clock signal not synchronized with the VGA clock signal for RDCLK. The XH and XVSYNC signals are retimed versions of the VGA H and VSYNC signals. (asynchronous) The other outputs use the VGA DOTCLK signal. 1 0: Use the VGA DOTCLK signal for RDCLK. The YCrCb data, XVSYNC, XBLANK, and XENRST signals all are dealt in the VGA clock. An external oscillator is not necessary. (synchronous) For Information Equipment MN89201 Pin Descriptions (continued) Pin No. 26 Symbol MOD422F I/O I Function Description Cr and Cb output mode specification "L" level: Cr and Cb are both 8 bits (24-bit mode) "H" level: Cr and Cb are multiplexed into 8 bits (16-bit mode) The combined output is sent to CROUT[7:0]. The MODCRCB pin specifies the multiplex order. 27 MODVFIL I This pin switches the vertical filter ON and OFF. "L" level: OFF; "H" level: ON 28 MODHFIL I This pin switches the horizontal filter ON and OFF. "L" level: OFF; "H" level: ON 29 MODPIN I This pin selects the setting of the filter mode. "H" level: Ignore mode register setting and take filter settings from pins. "L" level: Ignore pins and take filter settings from mode register. 30 MINTEST I Test pin Keep this pin at "L" level. 31 ,32 MON[1:0] I Test pin Keep this pin at "L" level. SXRST I 33 This signal resets the synchronization counter only. Active "H" 34 MODCRCB I This pin specifies the bit order for multiplexed Cr and Cb output data in the 16-bit mode. "H" level: Cr before Cb "L" level: Cb before Cr 35 MODCHAV I This pin selects the default values for the parameter registers determining the vertical position of the television image. "H" level: Use the default setting that centers the PC image in the television display. Setting value is 45 for back porch and 530 for active end. These settings cause one or two PC lines to be lost at both the top and bottom. "L" level: Use the default settings that align the center of the PC image at two or three lines below the center of the television display. Setting value is 35 for back porch and 514 for active end. These settings doesn’t lose the tops of the images but cause three or four lines to be lost at the bottom. MN89201 For Information Equipment Pin Descriptions (continued) Pin No. 36 Symbol MODST I/O I Function Description This pin selects the output signal to the monitor pin, MEMOUT7 (pin 37). "H" level: Pin 37 (normally "H" level) indicates the phase information of VSYNC signal in VGA when the MN89201 is in synchronization. Note: At the time when RESET (pin 23) or SXRST (pin 33) is driven (turned-ON or -OFF), the inner counter of the MN89201 begins to operate in phase with H and VSYNC of VGA. So, the phase shift in VGA after synchronization can cause wrong display. In this case you should survey the phase information in synchronization that is outputted from this pin, and detect the phase variation of the synchronous signal in VGA, then give RESET or SXRST to the MN89201. "L" level: Test signal output. 37 MEMOUT7/ O SYNCINF If the MODST pin (pin 36) is "H" level, this pin indicates phase information in synchronization of internal counters and VGA synchronizing signals. If pin 36 is "L" level, this pin is output for a test. Should be left open usually. 38 MEMOUT 41 to 46 [6:0] 49 OSXIN O Test pin Normally leave this pin open. I External oscillator input pin If an external oscillator is not used, drive this pin at "L" level. 50 XOO O External oscillator output pin 53 OEOP O Internal PLL comparator result signal 54 OEON O Internal PLL comparator result signal 57 RD2CLK O This data clock is half the frequency of RDCLK, has the same frequency as the clock for Y, Cr, and Cb outputs. The XHSYNC, XVSYNC, and XBLANK signals have a retiming at the rising edge of this clock signal. 58 XHSYNC O Horizontal synchronizing output signal (Active "L") 59 XVSYNC O Vertical synchronizing output signal (Active "L") 60 XBLANK O Composite blanking output signal (Active "L") 61 XENRST O Encoder reset signal (Active "L") This signal has four fields interval (when both H and V are at "L" level.) Use it as necessary to control the NTSC encoder. 62 RDCLK O Encoder clock Y, Cr, and Cb outputs to the NTSC encoder are synchronized with the rising edge of this clock signal. For Information Equipment MN89201 Pin Descriptions (continued) Pin No. Symbol I/O 65 to 70 CB OUT[7:0] O Function Description CR OUT[7:0] O In the 24-bit mode, color difference output (CR: R-Y). And in the Y OUT[7:0] O Luminance signal output (Y) 97 to 101 TEST[4:0] I Test pins 102 to 109 BIN[7:0] I Blue input signals 110 to 117 GIN[7:0] I Green input signals 118 to 125 RIN[7:0] I Red input signals 126 XVSYNCIN I VVGA horizontal synchronizing input signal (Active "L") 127 XHSYNCIN I VGA vertical synchronizing input signal (Active "L") 128 DOTCLK I VGA dot clock In the 24-bit mode, color difference output (CB: B-Y). And in the 73 to 74 75 to 78 16-bit mode, CBOUT0 gives the Cr flag: "H" level for Cr output. 81 to 84 85 to 86 16-bit mode, these pins yield multiplexed Cr/Cb output. 89 to 94 Keep these pins at "L" level. The chip latches input data from VGA at the rising edge of this clock signal. Absolute Maximum Ratings Parameter Power supply voltage Symbol VDD Ratings – 0.3 to +7.0 Unit V Input pin voltage VI – 0.3 to VDD+0.3 V Output pin voltage VO – 0.3 to VDD+0.3 V Output current IOL +12 mA Output current IOH – 12 mA Power dissipation PD 1000 mW Operating ambient temperature Topr – 40 to +70 ˚C Storage temperature Tstg – 55 to +150 ˚C Recommended Operating Conditions Parameter Symbol Conditions min typ max 5.0 Unit Power supply voltage VDD 4.75 5.25 V Ambient temperature Ta 0 70 ˚C Rise time for input tr 0 150 ns Fall time for input tf 0 150 ns Oscillation frequency fosc Crystal oscillator 24 MHz 24 MHz Recommended value CXI VDD=5.0V 12 pF for external capacitance CXO Built-in feedback resistor 12 pF MN89201 For Information Equipment Electrical Characteristics VDD =4.75 to 5.25V, VSS =0.00V, f=25MHz, Ta=0 to 70˚C Parameter Symbol Power supply current I DD during operation Conditions min typ VI =VDD or VSS max Unit 126 mA 1430 kΩ VDD V f=25MHz VDD =5.0V Output open Oscillator circuit XOO Built-in feedback resistance Rfb VI =VDD or VSS, VDD =5.0V 228 570 CMOS level input with pull-down resistor: MINTEST "H" level input voltage VDD × 0.7 VIH2 "L" level input voltage VIL2 Pull-down resistance RPD1 VI =VDD, VDD=5.0V 0 Input leakage current I LIPD VI =VSS 12 30 V DD × 0.3 V 75 kΩ ±20 µA TTL level inputs: RA0 to 3, AEN, BIN0 to 7, GIN0 to 7, MOD422F, RIN0 to 7, XRD, XWE, TEST0 to 4, MODST, DOTCLK, MODPIN, MODSET0 to 1, REGLIN, MODCHAV, MODCRCB, MODHFIL, MODVFIL, XHSYNCIN, XVSYNCIN "H" level input voltage VIH1 2.0 VDD V "L" level input voltage VIL1 0 0.8 V ±10 µA 2.4 V ±10 µA Input leakage current ILI VI =VDD or VSS TTL level inputs with Schmidt input: SRST, RESET Input threshold voltage VtHL VDD =4.75 to 5.25V VtLH ∆Vtt Hysteresis width Input leakage current ILI VDD =5.0V 1.8 0.4 1.0 0.4 0.8 VI =VDD or VSS V Push-pull outputs: RD2CLK, OEON, OEOP, YOUT0 to 7, CBOUT0 to 7, CROUT0 to 7, RDCLK, MEMOUT0 to 7, XBLANK, XHSYNC, XVSYNC, XENRST "H" level output voltage VOH IO=–4 .0mA VDD– 0.6 V VI =VDD or VSS "L" level output voltage VOL IO=4.0mA 0.4 V – 12 12 mA VDD × 0.7 VDD V 0 V DD × 0.3 VI =VDD or VSS Peak output current IO (Peak) Absolute maximum rating (not guaranteed operating value) CMOS level I/O: DB0 to DB7 "H" level input voltage VIH2 "L" level input voltage VIL2 "H" level output voltage VOH "L" level output voltage VOL Output leakage current ILO IO=–4.0mA VDD –0.6 V V VI =VDD or VSS IO=4.0mA 0.4 V ±10 µA 12 mA VI =VDD or VSS VO=High-impedance state VI =VDD or VSS VO=V DD or VSS Peak output current IO (Peak) Absolute maximum rating (not guaranteed operating value) –12 For Information Equipment MN89201 Timing Chart 780 clock cycles 640 clock cycles Back porch Front porch 60 clock cycles 22 clock cycles Active interval (horizontal) Horizontal synchronization Horizontal synchronizing signal Horizontal synchronizing signal 58 clock cycles 118 clock cycles 480 lines Active interval (vertical) Vertical synchronization Vertical synchronizing signal Vertical synchronizing signal Horizontal synchronizing signal 2 lines 35 lines 515 lines 525 lines (for a readout frequency of 12.27 MHz) MN89201 For Information Equipment Application Circuit Example 16 Address decoder SA AEN RA0 YOUT RA1 MN89201 RA2 CROUT 8 8 Y 8 C RA3 XRD CBOUT XWE XHSYNC 8 DB XVSYNC Counters 8 8 8 VGA XENRST RIN NTSC encoder GIN 1/2nd frequency divider BIN RD2CLK XVSYNCIN RDCLK XHSYNCIN SEL DOTCLK 25.175MHz (VGACLK) PLL RESET VCO1 OSC Notes: Choose the clock frequencies to match the synchronization system for the NTSC encoder. The PLL uses the VGA XHSYNCIN (31.5 MHz) clock signal for comparison. The XHSYNC, XVSYNC, and XENRST signals to the NTSC encoder are synchronized with the VGA outputs. For Information Equipment MN89201 Package Dimensions (Unit: mm) QFH128-P-1818 20.0±0.2 18.0±0.2 96 65 64 18.0±0.2 20.0±0.2 (1.25) 97 0.1 SEATING PLANE 0 to 10° 1.0±0.2 +0.10 32 0.2±0.1 0.15–0.05 0.5 3.4±0.3 1 3.3±0.2 (1.25) 33 0.1±0.1 128 0.5±0.2