Data Sheet

SC16C852V
1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs,
infrared (IrDA) and XScale VLIO bus interface
Rev. 5 — 21 January 2011
Product data sheet
1. General description
The SC16C852V is a 1.8 V, low power dual channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. SC16C852V can be programmed to operate in extended mode where
additional advanced UART features are available (see Section 6.2). The SC16C852V
family UART provides enhanced UART functions with 128-byte FIFOs, modem control
interface, DMA mode data transfer, and IrDA encoder/decoder. On-board status registers
provide the user with error indications and operational status. System interrupts and
modem control features may be tailored by software to meet specific user requirements.
An internal loopback capability allows on-board diagnostics. Independent programmable
baud rate generators are provided to select transmit and receive baud rates.
The SC16C852V with Intel XScale processor VLIO interface operates at 1.8 V and is
available in HVQFN48 and TFBGA36 packages.
2. Features and benefits
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Dual channel high performance UART
1.8 V operation
Advanced packages: HVQFN48 and TFBGA36
Up to 5 Mbit/s data rate at 1.8 V
128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
128 programmable Receive and Transmit FIFO interrupt trigger levels
128 Receive and Transmit FIFO reporting levels (level counters)
Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
Programmable Xon/Xoff characters
128 programmable hardware and software trigger levels
Automatic 9-bit mode (RS-485) address detection
Automatic RS-485 driver turn-around with programmable delay
Dual channel concurrent write
UART software reset
High resolution clock prescaler, from 0 to 15 with granularity of 1⁄16 to allow
non-standard UART clock to be used
Industrial temperature range (−40 °C to +85 °C)
Software compatible with industry standard SC16C652B
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
„
„
„
„
„
„
„
Software selectable baud rate generator
Supports IrDA version 1.0 (up to 115.2 kbit/s)
Standard modem interface or infrared IrDA encoder/decoder interface
Enhanced Sleep mode and low power feature
Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
Independent transmitter and receiver enable/disable
Pb-free, RoHS compliant package offered
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
SC16C852V
Product data sheet
Description
Version
SC16C852VIBS HVQFN48 plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; body 6 × 6 × 0.85 mm
SOT778-3
SC16C852VIET TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls;
body 3.5 × 3.5 × 0.8 mm
SOT912-1
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
2 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
4. Block diagram
SC16C852VIBS
FLOW
CONTROL
LOGIC
CS
REGISTER
SELECT
LOGIC
LOWPWR
POWER
DOWN
CONTROL
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
AD0 to AD7
IOR
IOW
RESET
LLA
TRANSMIT
FIFO
REGISTER
RECEIVE
FIFO
REGISTER
FLOW
CONTROL
LOGIC
IR
ENCODER
RECEIVE
SHIFT
REGISTER
RXA, RXB
IR
DECODER
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
MODEM
CONTROL
LOGIC
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
002aac349
XTAL1
Fig 1.
XTAL2
Block diagram of SC16C852V (HVQFN48 package)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
3 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
SC16C852VIET
FLOW
CONTROL
LOGIC
CS
REGISTER
SELECT
LOGIC
LOWPWR
POWER
DOWN
CONTROL
INTA, INTB
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL
LOGIC
INTERRUPT
CONTROL
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
AD0 to AD7
IOR
IOW
RESET
LLA
TRANSMIT
FIFO
REGISTER
RECEIVE
FIFO
REGISTER
FLOW
CONTROL
LOGIC
IR
ENCODER
RECEIVE
SHIFT
REGISTER
RXA, RXB
IR
DECODER
DTRA, DTRB
RTSA, RTSB
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
002aac348
XTAL1
Fig 2.
XTAL2
Block diagram of SC16C852V (TFBGA36 package)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
4 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
5. Pinning information
37 n.c.
38 CTSA
39 DSRA
40 CDA
41 RIA
42 VDD
43 TXRDYA
44 AD0
45 AD1
46 AD2
terminal 1
index area
47 AD3
48 AD4
5.1 Pinning
AD5
1
36 RESET
AD6
2
35 DTRB
AD7
3
34 DTRA
RXB
4
33 RTSA
RXA
5
32 OP2A
TXRDYB
6
TXA
7
TXB
8
29 INTB
OP2B
9
28 LLA
CS 10
27 n.c.
n.c. 11
26 n.c.
LOWPWR 12
25 n.c.
31 RXRDYA
n.c. 24
CTSB 23
RTSB 22
30 INTA
RIB 21
DSRB 20
IOR 19
RXRDYB 18
VSS 17
CDB 16
IOW 15
XTAL2 14
XTAL1 13
SC16C852VIBS
002aac351
Transparent top view
Fig 3.
Pin configuration for HVQFN48
SC16C852VIET
ball A1
index area
1
2
3
4
5
6
A
B
C
D
E
F
002aac350
Transparent top view
Fig 4.
SC16C852V
Product data sheet
Pin configuration for TFBGA36
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
5 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
1
2
3
4
5
6
A
AD4
AD2
AD0
RIA
DSRA
CTSA
B
AD5
AD3
AD1
CDA
RESET
DTRB
C
AD7
RXB
AD6
VDD
DTRA
RTSA
D
RXA
TXA
XTAL1
VSS
INTA
INTB
E
TXB
CS
IOW
DSRB
RTSB
LLA
F
LOWPWR
XTAL2
CDB
IOR
RIB
CTSB
002aac352
Fig 5.
TFBGA36 ball mapping (transparent top view)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
TFBGA36
HVQFN48
AD0
A3
44
I/O
AD1
B3
45
I/O
AD2
A2
46
I/O
AD3
B2
47
I/O
AD4
A1
48
I/O
AD5
B1
1
I/O
AD6
C3
2
I/O
AD7
C1
3
I/O
CDA
B4
40
I
CDB
F3
16
I
CS
E2
10
I
Chip Select (active LOW). This pin enables the data transfers between the
host and the SC16C852V for the addressed channel. Individual channel
selection is done with address A6. When A6 is 0 channel A is selected, and
when A6 is 1 channel B is selected.
Clear to Send (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on the CTS pin indicates the modem or
data set is ready to accept transmit data from the SC16C852V. Status can be
tested by reading MSR[4].
Type Description
CTSA
A6
38
I
CTSB
F6
23
I
DSRA
A5
39
I
DSRB
E4
20
I
DTRA
C5
34
O
DTRB
B6
35
O
SC16C852V
Product data sheet
Address and Data bus (bidirectional). These pins are the 8-bit multiplexed
data bus and address bus for transferring information to or from the controlling
CPU. AD0 is the least significant bit and is address A0 during the address
cycle, and AD7 is the most significant bit and is address A7 during the address
cycle.
Carrier Detect (active LOW). These inputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that a carrier has
been detected by the modem for that channel.
Data Set Ready (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem or data
set is powered-on and is ready for data exchange with the UART. Status can be
tested by reading MSR[5].
Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates that the
SC16C852V is powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
6 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TFBGA36
HVQFN48
INTA
D5
30
O
Channel A interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is
set to a logic 1. INTA is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21.
INTB
D6
29
O
Channel B interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode when MCR[3] is
set to a logic 1. INTB is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21.
IOR
F4
19
I
Read strobe (active LOW). A HIGH to LOW transition on this signal starts the
read cycle. The SC16C852V reads a byte from the internal register and puts
the byte on the data bus for the host to retrieve.
IOW
E3
15
I
Write strobe (active LOW). A HIGH to LOW transition on this signal starts the
write cycle, and a LOW to HIGH transition transfers the data on the data bus to
the internal register.
LLA
E6
28
I
Latch Lower Address (active LOW). A logic LOW on this pin puts the VLIO
interface in the address phase of the transaction, where the lower 8 bits of the
VLIO (specifying the UART register and the channel address) are loaded into
the address latch of the device through the AD7 to AD0 bus. A logic HIGH puts
the VLIO interface in the data phase where data can are transferred between
the host and the UART.
LOWPWR F1
12
I
Low Power. When asserted (active HIGH), the device immediately goes into
low power mode. The oscillator is shut-off and some host interface pins are
isolated from the host’s bus to reduce power consumption. The device only
returns to normal mode when the LOWPWR pin is de-asserted. On the
negative edge of a de-asserting LOWPWR signal, the device is automatically
reset and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
n.c.
-
11, 24, 25, 26, 27, 37
not connected
OP2A
-
32
O
OP2B
-
9
O
Output 2 (user-defined). This function is associated with individual channels,
A through B. The state at these pin(s) are defined by the user and through
MCR register bit 3. INTA, INTB are set to the active mode and OP2A/OP2B to
logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode
and OP2A/OP2B to a logic 1 when MCR[3] is set to a logic 0 (see Table 20
“Modem Control Register bits description”, bit 3). Since these bits control both
the INTA, INTB operation and OP2A/OP2B outputs, only one function should
be used at one time, interrupt or OP function.
RESET
B5
36
I
Master reset (active LOW). A reset pulse will reset the internal registers and
all the outputs. The SC16C852V transmitter outputs and receiver inputs will be
disabled during reset time. (See Section 7.23 “SC16C852V external reset
condition and software reset” for initialization details.)
RIA
A4
41
I
RIB
F5
21
I
Ring Indicator (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
RTSA
C6
33
O
RTSB
E5
22
O
SC16C852V
Product data sheet
Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control
register MCR[1] will set this pin to a logic 0, indicating data is available. After a
reset this pin will be set to a logic 1.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
7 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TFBGA36
HVQFN48
RXA
D1
5
I
RXB
C2
4
I
RXRDYA
-
31
O
RXRDYB
-
18
O
TXA
D2
7
O
TXB
E1
8
O
Receive data A, B. These inputs are associated with individual serial channel
data to the SC16C852V receive input circuits, A through B. The RX signal will
be a logic 1 during reset, idle (no data), or when not receiving data. During the
local Loopback mode, the RX input pin is disabled and TX data is connected to
the UART RX input, internally.
Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B). RXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive ready status
with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not
been reached. This signal can also be used for single mode transfers (DMA
mode 0).
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C852V. The TX signal will be a logic 1
during reset, idle (no data), or when the transmitter is disabled. During the local
Loopback mode, the TX output pin is disabled and TX data is internally
connected to the UART RX input.
TXRDYA
-
43
O
TXRDYB
-
6
O
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B). TXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,
at lease one location is empty and available in the FIFO or THR. This pin goes
to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers (DMA mode 0).
VDD
C4
42
I
Power supply input.
VSS
D4
17[1]
I
Signal and power ground.
XTAL1
D3
13
I
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see Section 6.9 “Programmable baud
rate generator”). See Figure 7.
XTAL2
F2
14
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external
clock is connected to XTAL1.
[1]
HVQFN48 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
8 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6. Functional description
The SC16C852V provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C852V represents such
an integration with greatly enhanced features. The SC16C852V is fabricated with an
advanced CMOS process.
The SC16C852V is an upward solution to the SC16C652B with a VLIO interface that
provides a dual UART capability with 128 bytes of transmit and receive FIFO memory,
instead of 32 bytes for the SC16C652B. The SC16C852V is designed to work with high
speed modems and shared network environments that require fast data processing time.
Increased performance is realized in the SC16C852V by the transmit and receive FIFOs.
This allows the external processor to handle more networking tasks within a given time. In
addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided
in normal mode, or 128 programmable levels are provided in extended mode for
maximum data throughput performance especially when operating in a multi-channel
environment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO memory
greatly reduces the bandwidth requirement of the external controlling CPU, and increases
performance.
A low power pin (LOWPWR) is provided to further reduce power consumption by isolating
the host interface bus.
The SC16C852V is capable of operation up to 5 Mbit/s with an external 80 MHz clock.
With a crystal is capable of operation up to 1.5 Mbit/s.
The rich feature set of the SC16C852V is available through internal registers. These
features are: selectable and programmable receive and transmit FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls (all standard features).
Following a power-on reset an external reset or a software reset, the SC16C852V is
software compatible with the previous generation SC16C652B.
6.1 UART A-B functions
The UART provides the user with the capability to bidirectionally transfer information
between a CPU and an external serial device. The CS pin together with addresses A6 and
A7 determine which channel of the UART is being accessed; see Table 3.
Table 3.
Serial port selection
H = HIGH-level; L = LOW-level; X = Don’t care.
SC16C852V
Product data sheet
Chip Select
Function
CS = H, A7 = X, A6 = X
none
CS = L, A7 = L, A6 = L
UART channel A
CS = L, A7 = L, A6 = H
UART channel B
CS = L, A7 = L, A6 = X
device not selected
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
9 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.2 Extended mode (128-byte FIFO)
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
6.3 Internal registers
The SC16C852V provides two sets of internal registers (A and B) consisting of
25 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4.
Table 4.
Internal registers decoding
A3
A1
A2
Read mode
Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR, LSR, EFCR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
Interrupt Enable Register
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
1
Line Control Register
Line Control Register
1
0
0
Modem Control Register
Modem Control Register
1
0
1
Line Status Register
Extra Feature Control Register (EFCR)
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
Second special register set
(TXLVLCNT/RXLVLCNT)[3]
0
1
1
Transmit FIFO Level Count
n/a
1
0
0
Receive FIFO Level Count
n/a
Enhanced register set (EFR, Xon1/Xon2,
Xoff1/Xoff2)[4]
0
1
0
Enhanced Feature Register
Enhanced Feature Register
1
0
0
Xon1 word
Xon1 word
1
0
1
Xon2 word
Xon2 word
1
1
0
Xoff1 word
Xoff1 word
1
1
1
Xoff2 word
Xoff2 word
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)[5]
0
1
0
Transmit FIFO Interrupt Level
Transmit FIFO Interrupt Level
1
0
0
Receive FIFO Interrupt Level
Receive FIFO Interrupt Level
1
1
0
Flow Control Count High
Flow Control Count High
1
1
1
Flow Control Count Low
Flow Control Count Low
Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)[6]
0
1
0
Clock Prescaler
1
0
0
RS-485 turn-around Timer
RS-485 turn-around Timer
1
1
0
Additional Feature Control Register 2
Additional Feature Control Register 2
1
1
1
Additional Feature Control Register 1
Additional Feature Control Register 1
[1]
SC16C852V
Product data sheet
Clock Prescaler
These registers are accessible only when LCR[7] is a logic 0.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
10 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Second special registers are accessible only when EFCR[0] = 1.
[4]
Enhanced feature registers are only accessible when LCR = 0xBF.
[5]
First extra feature registers are only accessible when EFCR[2:1] = 01b.
[6]
Second extra feature registers are only accessible when EFCR[2:1] = 10b.
6.4 FIFO operation
6.4.1 32-byte FIFO mode
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by
FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to
the SC16C652B (see Table 5), and the FIFO sizes are 32 entries. The transmit and
receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be
noted that the user can set the transmit trigger levels by writing to the FCR, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a
time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please
refer to Table 12 and Table 13 for the setting of FCR[7:4].
Table 5.
Interrupt trigger level and flow control mechanism
(FCR[7:6, 5:4])
INTA/INTB pin activation
RX
TX
Negate RTSA/RTSB
or send Xoff
Assert RTSA/RTSB
or send Xon
[00, 00]
8
16
8
0
[01, 01]
16
8
16
7
[10, 10]
24
24
24
15
[11, 11]
28
30
28
23
6.4.2 128-byte FIFO mode
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the transmit and receive trigger levels are set by
TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit
FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with
granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger
levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C852V monitors the CTSx pin
for a remote buffer overflow indication and controls the RTSx pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTSx transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852V will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTSx input returns to a logic 0, indicating more data
may be sent.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
11 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
When AFCR1[2] is set to 1, then the function of CTSx pin is mapped to the DSRx pin, and
the function of RTS is mapped to DTRx pin. DSRx and DTRx pins will behave as
described above for CTSx and RTSx.
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not
be forced to a logic 1 (RTS off) until the receive FIFO reaches the next trigger level.
However, the RTSx (or DTRx) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16C852V will continue to accept data until the receive FIFO
is full.
When TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the First Extra Register Set
are all zeroes, the hardware and software flow control trigger levels are set by FCR[7:4];
see Table 5.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the hardware and software flow control trigger
levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how
many bytes are in the receive FIFO before RTSx (or DTRx) is de-asserted or XOFF is
sent. The content of FLWCNTL determines how many bytes are in the receive FIFO
before RTSx (or DTRx) is asserted, or XON is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met spurious operation of the device might occur. When using
FLWCNTH and FWLCNTL, these registers must be initialized to the proper values before
hardware or software flow control is enabled via the EFR register.
6.6 Software flow control
When software flow control is enabled, the SC16C852V compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C852V will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C852V will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C852V will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions (see Table 26). When double 8-bit Xon/Xoff characters are selected, the
SC16C852V compares two consecutive receive characters with two software flow control
8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under
the above described flow control mechanisms, flow control characters are not placed
(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters
cannot be used for data transfer.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
12 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
In the event that the receive buffer is overfilling, the SC16C852V automatically sends an
Xoff character (when enabled) via the serial TX output to the remote UART. The
SC16C852V sends the Xoff1/Xoff2 characters as soon as the number of received data in
the receive FIFO passes the programmed trigger level. To clear this condition, the
SC16C852V will transmit the programmed Xon1/Xon2 characters as soon as the number
of characters in the receive FIFO drops below the programmed trigger level.
6.7 Special character detect
A special character detect feature is provided to detect an 8-bit character when EFR[5] is
set. When an 8-bit character is detected, it will be placed on the user-accessible data
stack along with normal incoming RXA/RXB data. This condition is selected in conjunction
with EFR[3:0] (see Table 26). Note that software flow control should be turned off when
using this special mode by setting EFR[3:0] to all zeroes.
The SC16C852V compares each incoming receive character with Xoff2 data. If a match
occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 9 “SC16C852V internal registers” shows
Xon-1, Xon-2, Xoff-1, Xoff-2 with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register bits LCR[1:0]
define the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word
length selected by LCR[1:0] also determine the number of bits that will be used for the
special character comparison. Bit 0 in the Xon-1, Xon-2, Xoff-1, Xoff-2 registers
corresponds with the LSB bit for the received character.
6.8 Interrupt priority and time-out interrupts
The interrupts are enabled by IER[7:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C852V
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR indicates the current singular highest priority interrupt
only. A condition can exist where a higher priority interrupt masks the lower priority
interrupt(s) (see Table 14). Only after servicing the higher pending interrupt will the lower
priority interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
Receive Data Ready and Receive Time Out have the same interrupt priority (when
enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver
issues an interrupt after the number of characters have reached the programmed trigger
level. In this case, the SC16C852V FIFO may hold more characters than the programmed
trigger level. Following the removal of a data byte, the user should re-check LSR[0] to see
if there are any additional characters. A Receive Time Out will not occur if the receive
FIFO is empty. The time-out counter is reset at the center of each stop bit received or
each time the Receive Holding Register (RHR) is read. The actual time-out value is
4 character time, including data information length, start bit, parity bit, and the size of stop
bit, that is, 1×, 1.5×, or 2× bit times.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
13 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.9 Programmable baud rate generator
The SC16C852V UART contains a programmable rational baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (216 − 1). The
SC16C852V offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the First Extra
Register Set.
f XTAL1
baud rate = -----------------------------------------------------------------M
MCR [ 7 ] × 16 × ⎛ N + ------⎞
⎝
16⎠
(1)
where:
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
fXTAL1 is the clock frequency at XTAL1 pin.
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
CLKPRES
[3:0]
DIVIDE-BY-1
MCR[7] = 0
XTAL1
XTAL2
BAUD RATE
GENERATOR
(DLL, DLM)
OSCILLATOR
DIVIDE-BY-4
transmitter and
receiver clock
MCR[7] = 1
002aac645
Fig 6.
Prescalers and baud rate generator block diagram
A single baud rate generator is provided for the transmitter and receiver. The
programmable Baud Rate Generator (BRG) is capable of operating with a frequency of up
to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C852V can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected
to the XTAL1 pin (see Figure 8) to clock the internal baud rate generator for standard or
custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The
SC16C852V divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in Table 6
shows the selectable baud rate available when using a 1.8432 MHz external clock input
with MCR[7] is 0, and CLKPRES = 0x00.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
14 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
XTAL1
XTAL2
XTAL1
X1
1.8432 MHz
C1
22 pF
XTAL2
X1
1.8432 MHz
C2
33 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa870
Fig 7.
Crystal oscillator connection
XTAL1
fXTAL1
XTAL2
100 pF
002aac630
If fXTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required.
XTAL2 pin should be left unconnected when an external clock is used.
Fig 8.
External clock connection
Table 6.
SC16C852V
Product data sheet
Baud rate generator programming table using a 1.8432 MHz clock with MCR[7] = 0
and CLKPRE[3:0] = 0
Output
baud rate
(bit/s)
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(hexadecimal)
DLM
program value
(hexadecimal)
DLL
program value
(hexadecimal)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
15 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.10 DMA operation
The SC16C852V FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYx and TXRDYx
output pins. Table 7 and Table 8 show this.
Remark: DMA pins are not available on the TFBGA36 package.
Table 7.
Effect of DMA mode on state of RXRDYx pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, or time-out occurs[1]
[1]
Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the receive FIFO becomes full at
128 bytes.
Table 8.
Effect of DMA mode on state of TXRDYx pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full [1]
0 = FIFO empty
[1]
1-to-0 transition when FIFO has at least one empty location
Transmit FIFO becomes full at 32 byte when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the transmit FIFO becomes full at
128 byte.
6.11 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see Figure 9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
In the Loopback mode, the transmitter output (TXA/TXB) and the receiver input
(RXA/RXB) are disconnected from their associated interface pins, and instead are
connected together internally. The CTSx, DSRx, CDx, and RIx are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2A/OP2B) and MCR[2] (OP1A/OP1B). Loopback test data is entered
into the transmit holding register via the user data bus interface, D[7:0]. The transmit
UART serializes the data and passes the serial data to the receive UART via the internal
loopback connection. The receive UART converts the serial data back into parallel data
that is then made available at the user data interface D[7:0]. The user optionally compares
the received data to the initial transmitted data for verifying error-free operation of the
UART TX/RX circuits.
In this mode the interrupt pins are 3-stated, therefore the software must use polling
method (see Section 7.2.2) to send and receive data.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
16 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
SC16C852V
AD0 to AD7
IOR
IOW
RESET
LLA
TRANSMIT
FIFO
REGISTER
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL
LOGIC
IR
ENCODER
FLOW
CONTROL
LOGIC
CS
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MCR[4] = 1
REGISTER
SELECT
LOGIC
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
IR
DECODER
FLOW
CONTROL
LOGIC
RTSA, RTSB
LOWPWR
POWER
DOWN
CONTROL
CTSA, CTSB
MODEM
CONTROL
LOGIC
DTRA, DTRB
DSRA, DSRB
OP1A/OP1B
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
RIA, RIB
(OP2A/OP2B)
CDA, CDB
002aac353
XTAL1
Fig 9.
XTAL2
Internal Loopback mode diagram
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
17 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.12 Sleep mode
Sleep mode is an enhanced feature of the SC16C852V UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] of both channels are set.
6.12.1 Conditions to enter Sleep mode
Sleep mode is entered when:
• Modem input pins are not toggling.
• The serial data input line, RXA/RXB, is idle for 4 character time (logic HIGH) and
AFCR1[4] is 0. When AFCR1[4] is 1, the device will go to sleep regardless of the state
of the RXA/RXB pin (see Section 7.21 for the description of AFCR1 bit 4).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending.
• The RX FIFO is empty.
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
6.12.2 Conditions to resume normal operation
SC16C852V resumes normal operation by any of the following:
• Receives a start bit on RXA or RXB pin.
• Data is loaded into transmit FIFO.
• A change of state on any of the modem input pins.
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after all the conditions described in Section 6.12.1 are met. The
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic 0.
When the SC16C852V is in Sleep mode and the host interface bus (AD7 to AD0, IOW,
IOR, CS) remains in steady state, either HIGH or LOW, the sleep current will be in the
microampere range as specified in Table 38 “Static characteristics”. If any of these signals
is toggling or floating then the sleep current will be higher.
6.13 Low power feature
A Low Power feature is provided by the SC16C852V to prevent the switching of the host
data bus from influencing the sleep current. When the pin LOWPWR is activated (logic
HIGH), the device immediately and unconditionally goes into Low Power mode. All clocks
are stopped and most host interface pins are isolated to reduce power consumption. The
device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can
be left unconnected because it has an internal pull-down resistor.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
18 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.14 RS-485 features
6.14.1 Auto RS-485 RTS control
Normally the RTSx pin is controlled by MCR bit 1, or if hardware flow control is enabled,
the logic state of the RTSx pin is controlled by the hardware flow control circuitry. EFCR2
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTSx pin. The transmitter automatically asserts the
RTSx pin (logic 0) once the host writes data to the transmit FIFO, and de-asserts the
RTSx pin (logic 1) once the last bit of the data has been transmitted.
To use the auto RS-485 RTS mode, the software would have to disable the hardware flow
control function.
6.14.2 RS-485 RTS inversion
EFCR2 bit 5 reverses the polarity of the RTSx pin if the UART is in auto RS-485 RTS
mode.
When the transmitter has data to be sent, it will de-assert the RTSx pin (logic 1), and
when the last bit of the data has been sent out, the transmitter asserts the RTS pin
(logic 0).
6.14.3 Auto 9-bit mode (RS-485)
EFCR2 bit 0 is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode
of operation, a ‘master’ station transmits an address character followed by data characters
for the addressed ‘slave’ stations. The slave stations examine the received data and
interrupt the controller if the received character is an address character (parity bit = 1).
To use the auto 9-bit mode the software would have to disable the hardware and software
flow control functions.
6.14.3.1
Normal Multi-drop mode
The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).
The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an
address byte is received (parity bit = 1). This address byte will cause the UART to set the
parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at
this time), and at the same time puts this address byte in the RX FIFO. After the controller
examines the byte it must make a decision whether or not to enable the receiver; it should
enable the receiver if the address byte addresses its ID address, and must not enable the
receiver if the address byte does not address its ID address.
If the controller enables the receiver, the receiver will receive the subsequent data until
being disabled by the controller after the controller has received a complete message
from the ‘master’ station. If the controller does not disable the receiver after receiving a
message from the ‘master’ station, the receiver will generate a parity error upon receiving
another address byte. The controller then determines if the address byte addresses its ID
address, if it is not, the controller then can disable the receiver. If the address byte
addresses the ‘slave’ ID address, the controller take no further action, the receiver will
receive the subsequent data.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
19 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.14.3.2
Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte), the receiver will try to detect an address byte that matches the
programmed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the
receiver will discard these data. Upon receiving an address byte that matches the Xoff2
character, the receiver will be automatically enabled if not already enabled, and the
address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to
logic 1 at this time). The receiver will then receive the subsequent data from the ‘master’
station until being disabled by the controller after having received a message from the
‘master’ station.
If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
7. Register descriptions
Table 9 details the assigned bit functions for the SC16C852V internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.23.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
20 of 55
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
A3 A2
NXP Semiconductors
SC16C852V
Product data sheet
Table 9.
SC16C852V internal registers
A1
Register
General register
Default[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
set[2]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
0
0
1
IER
00
CTS
interrupt[3]
RTS
interrupt[3]
Xoff
interrupt[3]
Sleep
mode[3]
modem status receive line
interrupt
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
R/W
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX trigger
(MSB)[3]
TX trigger
(LSB)[3]
DMA mode
select
XMIT FIFO
reset
RCVR FIFO
reset
FIFOs
enable
W
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT priority INT priority INT priority
bit 4
bit 3
bit 2
INT priority
bit 1
INT priority
bit 0
INT status
R
0
1
1
LCR
00
divisor
latch
enable
set break
set parity
even parity parity enable
stop bits
word length
bit 1
word length
bit 0
R/W
1
0
0
MCR
00
clock
select[3]
IRDA
enable
reserved
loopback
OP2A, INT
enable
(OP1A)
RTS
DTR
R/W
1
0
1
LSR
60
FIFO data
error
THR and
THR empty break
TSR empty
interrupt
framing error
parity error
overrun error receive data R
ready
1
0
1
EFCR
00
reserved
reserved
reserved
reserved
reserved
Enable extra
feature bit-1
Enable extra Enable
feature bit-0 TXLVLCNT/
RXLVLCNT
W
1
1
0
MSR
X0
CD
RI
DSR
CTS
ΔCD
ΔRI
ΔDSR
ΔCTS
R
1
1
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Special register
set[4]
0
0
0
DLL
0
0
1
DLM
Second special register
set[5]
21 of 55
© NXP B.V. 2011. All rights reserved.
0
1
1
TXLVLCNT
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
1
0
0
RXLVLCNT
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
SC16C852V
0
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 5 — 21 January 2011
All information provided in this document is subject to legal disclaimers.
0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
A3 A2
SC16C852V internal registers …continued
A1
Register
Enhanced register
Default[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
00
Auto CTS
Auto RTS
special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3 Tx,
Rx Control
Cont-2 Tx,
Rx Control
Cont-1 Tx,
Rx Control
Cont-0 Tx,
Rx Control
R/W
set[6]
0
1
0
EFR
1
0
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
1
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
1
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
set[7]
0
1
0
TXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
0
RXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
1
0
FLWCNTH
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
1
1
FLWCNTL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
reserved
reserved
reserved
reserved
bit 3
bit 2
bit 1
bit 0
R/W
Second extra register set[8]
0
1
0
CLKPRES
1
0
0
RS485TIME
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
1
0
AFCR2
0x00
reserved
reserved
RS485
RTS invert
Auto
RS485
RTS
RS485
RTS/DTR
transmitter
disable
receiver
disable
9-bit enable
R/W
1
1
1
AFCR1
0x00
concurrent
write
reserved
reserved
sleep RX
LOW
reserved
RTS/CTS
mapped to
DTR/DSR
software
reset
TSR
interrupt
R/W
The value shown in represents the register’s initialized hexadecimal value; X = not applicable.
[2]
Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
[3]
This bit is only accessible when EFR[4] is set.
[4]
Baud rate registers accessible only when LCR[7] is logic 1.
[5]
Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[6]
Enhanced Feature Register, Xon-1/Xon-2 and Xoff-1/Xoff-2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
[7]
First extra register set is only accessible when EFCR[2:1] = 01b.
[8]
Second extra register set is only accessible when EFCR[2:1] = 10b.
SC16C852V
22 of 55
© NXP B.V. 2011. All rights reserved.
[1]
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 5 — 21 January 2011
All information provided in this document is subject to legal disclaimers.
First extra register
NXP Semiconductors
SC16C852V
Product data sheet
Table 9.
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to
the transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the
transmit FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852V
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time should be
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 10.
Interrupt Enable Register bits description
Bit
Symbol Description
7
IER[7]
CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C852V issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C852V issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal default
condition)
logic 1 = enable the receive Xoff interrupt
4
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
23 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 10.
Interrupt Enable Register bits description …continued
Bit
Symbol Description
1
IER[1]
Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be
issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO
modes, this interrupt will be issued whenever the FIFO is empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
0
IER[0]
Receive Holding Register interrupt. In the non-FIFO mode, this interrupt will be
issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the programmed
trigger level or is cleared when the FIFO drops below the trigger level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
7.2.1 IER versus transmit/receive FIFO interrupt mode operation
When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts
(IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the
following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR, or by loading the THR with new data characters.
7.2.2 IER versus receive/transmit FIFO polled mode operation
When FCR[0] = logic 1, setting IER[3:0] = zeroes puts the SC16C852V in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
•
•
•
•
•
SC16C852V
Product data sheet
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
24 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if
FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
In this mode, the transmit ready (TXRDY) is set when the transmit FIFO is below the
programmed trigger level. The receive ready (RXRDY) is set when the receive FIFO fills
to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
7.3.2 FIFO mode
Table 11.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7:6]
Receive trigger level in 32-byte FIFO mode.[1]
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C852V will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to Table 12.
5:4
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode.[2]
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852V will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 13.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C852V is in the non-FIFO
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO, the TXRDY signal will be a logic 0. Once
active, the TXRDY signal will go to a logic 1 after the first character is loaded
into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C852V is in non-FIFO
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is
at least one character in the receive FIFO, the RXRDY signal will be a
logic 0. Once active, the RXRDY signal will go to a logic 1 when there are no
more characters in the receiver.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
25 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 11.
Bit
FIFO Control Register bits description …continued
Symbol
3
(cont.)
Description
Transmit operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY signal will be a logic 1 when
the transmit FIFO is completely full, see Section 6.10 “DMA operation”. It will
be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY signal will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in the
FIFO.
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
[1]
For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.
[2]
For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.
Table 12.
FCR[6]
RX FIFO trigger level in 32-byte FIFO mode[1]
0
0
8 bytes
0
1
16 bytes
1
0
24 bytes
1
1
28 bytes
[1]
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.
Table 13.
Product data sheet
TX FIFO trigger levels
FCR[5]
FCR[4]
TX FIFO trigger level in 32-byte FIFO mode[1]
0
0
16 bytes
0
1
8 bytes
1
0
24 bytes
1
1
30 bytes
[1]
SC16C852V
RCVR trigger levels
FCR[7]
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
26 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.4 Interrupt Status Register (ISR)
The SC16C852V provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14.
Interrupt source
Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
level
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
0
1
0
0
RXRDY (Received Data Ready)
2
0
0
1
1
0
0
RXRDY (Receive Data time-out)
3
0
0
0
0
1
0
TXRDY (Transmitter Holding
Register Empty)
4
0
0
0
0
0
0
MSR (Modem Status Register)
5
0
1
0
0
0
0
RXRDY (Received Xoff signal)/
Special character
6
1
0
0
0
0
0
CTS, RTS change of state
Table 15.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852V mode.
logic 0 or cleared = default condition
5:4
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 14).
logic 0 or cleared = default condition
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
27 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 16.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3
LCR[5:3]
Programs the parity conditions (see Table 17).
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see Table 18).
logic 0 or cleared = default condition
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 19).
logic 0 or cleared = default condition
Table 17.
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
X
0
1
odd parity
0
1
1
even parity
0
0
1
forced parity ‘1’
1
1
1
forced parity ‘0’
Table 18.
Product data sheet
LCR[2] stop bit length
LCR[2]
Word length (bits)
0
5, 6, 7, 8
1
1
5
11⁄2
1
6, 7, 8
2
Table 19.
SC16C852V
LCR[5:3] parity selection
Stop bit length (bit times)
LCR[1:0] word length
LCR[1]
LCR[0]
Word length (bits)
0
0
5
0
1
6
1
0
7
1
1
8
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
28 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20.
Modem Control Register bits description
Bit
Symbol Description
7
MCR[7] Clock select
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6
MCR[6] IR enable (see Figure 21).
logic 0 = enable the standard modem receive and transmit input/output interface
(normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a logic 0
during idle data conditions.
5
MCR[5] Reserved; set to ‘0’.
4
MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C852V I/O pins. Internally the modem data and
control pins are connected into a loopback data configuration (see Figure 9). In
this mode, the receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts continue to be
controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3
MCR[3] OP2A/OP2B, INT enable
logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2A/OP2B to
a logic 1 (normal default condition)
logic 1 = forces the INT (A, B) outputs to the active mode and sets OP2A/OP2B
to a logic 0
Remark: OP2A/OP2B pins do not exist on the TFBGA36 package.
OP1A/OP1B are not available as an external signal in the SC16C852V. This bit is
instead used in the Loopback mode only. In the Loopback mode, this bit is used to
write the state of the modem RI interface signal.
2
MCR[2]
1
MCR[1] RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0] DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
Table 21.
SC16C852V
Product data sheet
Interrupt output control
MCR[3]
INT (A, B) output
0
3-state
1
active
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
29 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C852V and the CPU.
Table 22.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error flags
associated with the remaining data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the transmit holding register and the transmit shift register are
both empty. It is reset to logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode, this bit is set to logic 1 whenever the transmit
FIFO and transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.
3
LSR[3]
Framing error.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop bit(s).
In the FIFO mode, this error is associated with the character at the top of the
FIFO.
2
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the Receive Shift Register is not transferred
into the FIFO, therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding
Register or FIFO
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
30 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C852V is connected. Four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
When write, the data will be written to EFCR register.
Table 23.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loopback mode produces the state of MCR[3]
(OP2A/OP2B).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI input. Reading
this bit in the loopback mode produces the state of MCR[2] (OP1A/OP1B).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the loopback mode, this bit is equivalent to MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the loopback mode, this bit is equivalent to MCR[1] (RTS).
3
MSR[3]
ΔCD [1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C852V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
2
MSR[2]
ΔRI [1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C852V has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1
MSR[1]
ΔDSR [1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C852V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
ΔCTS [1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C852V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
[1]
SC16C852V
Product data sheet
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
31 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers:
First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 24.
Bit
Extra Feature Control Register bits description
Symbol
Description
7:3
EFCR[7:3]
reserved
2:1
EFCR[2:1]
Enable Extra Feature Control bits
00 = General Register Set is accessible
01 = First Extra Register Set is accessible
10 = Second Extra Register Set is accessible
11 = reserved
0
EFCR[0]
Enable TXLVLCNT and RXLVLCNT access
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
7.10 Scratchpad Register (SPR)
The SC16C852V provides a temporary data register to store 8 bits of user information.
7.11 Division Latch (DLL and DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
7.12 Transmit FIFO Level Count (TXLVLCNT)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
7.13 Receive FIFO Level Count (RXLVLCNT)
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RXFIFO).
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
32 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bit 0 through bit 4 provide single or dual character software flow control selection. When
the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 25.
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS flow control.
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS signal
returns to a logical 0.
6
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow
control. RTS functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
5
EFR[5]
Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C852V compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C852V
enhanced functions.
logic 0 = disable/latch enhanced features[1]
logic 1 = enables the enhanced functions[1]. When this bit is set to a logic 1,
all enhanced features of the SC16C852V are enabled and user settings
stored during a reset will be restored.
3:0
[1]
EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See Table 26.
Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].
Software flow control functions[1]
Table 26.
SC16C852V
Product data sheet
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
33 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Software flow control functions[1] …continued
Table 26.
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.15 Transmit Interrupt Level register (TXINTLVL)
This 8-bit register is used store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1. Table 27 shows trigger level register bit settings.
Table 27.
TXINTLVL register bits description
Bit
Symbol
Description
7:0
TXINTLVL[7:0]
This register stores the programmable transmit interrupt trigger levels for
128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.16 Receive Interrupt Level register (RXINTLVL)
This 8-bit register is used store the receive FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 28 shows trigger level register bit settings.
Table 28.
RXINTLVL register bits description
Bit
Symbol
Description
7:0
RXINTLVL[7:0]
This register stores the programmable receive interrupt trigger levels for
128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1]
SC16C852V
Product data sheet
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
34 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 29 shows transmission control
register bit settings; see Section 6.5.
Table 29.
FLWCNTH register bits description
Bit
Symbol
Description
7:0
FLWCNTH[7:0]
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 30 shows transmission control
register bit settings; see Section 6.5.
Table 30.
FLWCNTL register bits description
Bit
Symbol
Description
7:0
FLWCNTL[7:0]
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.19 Clock prescaler (CLKPRES)
This register hold values for the clock prescaler.
SC16C852V
Product data sheet
Table 31.
Clock prescaler register description
Bit
Symbol
Description
7:4
CLKPRES[7:4]
reserved
3:0
CLKPRES[3:0]
clock prescaler value; reset to 0
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
35 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.20 RS-485 turn-around time delay (RS485TIME)
The value in this register controls the turn-around time of the external line transceiver in
bit time. In automatic 9-bit mode, the RTSA/RTSB or DTRA/DTRB pin is used to control
the direction of the line driver, after the last bit of data has been shifted out of the transmit
shift register the UART will count down the value in this register. When the count value
reaches zero, the UART will assert the RTSA/RTSB or DTRA/DTRB pin (logic 0) to turn
the external RS-485 transceiver around for receiving.
Table 32.
RS-485 programmable turn-around time register
Bit
Symbol
Description
7:0
RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value
represents the bit time at the programmed baud rate.
7.21 Advanced Feature Control Register 1 (AFCR1)
Table 33.
Advanced Feature Control Register 1 bits description
Bit
Symbol
Description
7
AFCR1[7]
Concurrent write. When this bit is set the host can write concurrently to the
same register of all channels.
0 = normal operation
1 = concurrent write operation
6:5
AFCR1[6:5]
reserved
4
AFCR1[4]
Sleep RXlow. Program RX input to be edge-sensitive or level-sensitive.
0 = RX input is level sensitive. If RXA/RXB pin is LOW, the UART will not
go to sleep. Once the UART is in Sleep mode, it will wake up if RXA/RXB
pin goes LOW.
1 = RX input is edge sensitive. UART will go to sleep even if RXA/RXB
pin is LOW, and will wake up when RXA/RXB pin toggles.
3
AFCR1[3]
reserved
2
AFCR1[2]
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
0 = RTS and CTS signals are used for hardware flow control
1 = DTR and DSR signals are used for hardware flow control. RTS and
CTS retain their functionality.
1
AFCR1[1]
SReset. Software reset. A write to this bit will reset the UART. Once the
UART is reset this bit is automatically set to 0.[1]
0
AFCR1[0]
TSR interrupt. Select TSR interrupt mode.
0 = transmit empty interrupt occurs when transmit FIFO falls below the
trigger level or becomes empty.
1 = transmit empty interrupt occurs when transmit FIFO fall below the
trigger level, or becomes empty and the last stop bit has been shift out
the transmit shift register.
[1]
SC16C852V
Product data sheet
It takes 4 XTAL1 clocks to reset the device.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
36 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.22 Advanced Feature Control Register 2 (AFCR2)
Table 34.
Advanced Feature Control Register 2 bits description
Bit
Symbol
Description
7:6
AFCR2[7:6]
reserved
5
AFCR2[5]
RTSInvert. Invert RTS or DTR signal in auto 9-bit mode.
0 = RTS or DTR is set to 0 by the UART during transmission, and to 1
during reception
1 = RTS or DTR is set to 1 by the UART during transmission, and to 0
during reception
4
AFCR2[4]
RTSCon. Enable the transmitter to control RTS or DTR signal in auto 9-bit
mode.
0 = transmitter does not control RTS or DTR signal
1 = transmitter controls RTS or DTR signal
3
AFCR2[3]
RS485 RTS/DTR. Select RTSA/RTSB or DTRA/DTRB pin to control the
external transceiver.
0 = RTSA/RTSB pin is used to control the external transceiver
1 = DTRA/DTRB pin is used to control the external transceiver
2
AFCR2[2]
TXDisable. Disable transmitter.
0 = transmitter is enabled
1 = transmitter is disabled
1
AFCR2[1]
RXDisable. Disable receiver.
0 = receiver is enabled
1 = receiver is disabled
0
AFCR2[0]
9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode.
0 = normal RS-232 mode
1 = enable 9-bit mode
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
37 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.23 SC16C852V external reset condition and software reset
These two reset methods are identical and will reset the internal registers as indicated in
Table 35.
Table 35.
Reset state for registers
Register
Reset state
IER
IER[7:0] = 0
FCR
FCR[7:0] = 0
ISR
ISR[7:1] = 0; ISR[0] = 1
LCR
LCR[7:0] = 0
MCR
MCR[7:0] = 0
LSR
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR
MSR[7:4] = input signals; MSR[3:0] = 0
EFCR
EFCR[7:0] = 0
SPR
SPR[7:0] = 1
DLL
undefined
DLM
undefined
TXLVLCNT
TXLVLCNT[7:0] = 0
RXLVLCNT
RXLVLCNT[7:0] = 0
EFR
EFR[7:0] = 0
Xon-1
Undefined
Xon-2
Undefined
Xoff-1
Undefined
Xoff-2
Undefined
TXINTLVL
TXINTLVL[7:0] = 0
RXINTLVL
RXINTLVL[7:0] = 0
FLWCNTH
FLWCNTH[7:0] = 0
FLWCNTL
FLWCNTL[7:0] = 0
CLKPRES
CLKPRES[7:0] = 0
RS485TIME
RS485TIME[7:0] = 0
AFCR2
AFCR2[7:0] = 0
AFCR1
AFCR1[7:0] = 0
Table 36.
Reset state for outputs
Output
SC16C852V
Product data sheet
Reset state
TXA, TXB
logic 1
OP2A, OP2B
logic 1
RTSA, RTSB
logic 1
DTRA, DTRB
logic 1
INTA, INTB
3-state condition
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
38 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
8. Limiting values
Table 37. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
[1]
Min
Max
Unit
-
2.5
V
VSS − 0.3
VDD + 0.3
V
−40
+85
°C
Vn
voltage on any other pin
Tamb
ambient temperature
Tstg
storage temperature
−65
+150
°C
Ptot/pack
total power dissipation per
package
-
500
mW
[1]
operating in free air
Vn should not exceed 2.5 V.
9. Static characteristics
Table 38. Static characteristics
Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified.
Symbol
Parameter
Conditions
Max
Unit
VIL(clk)
clock LOW-level input voltage XTAL1 pin
-
-
0.25
V
clock HIGH-level input voltage XTAL1 pin
1.35
-
-
V
VIL
LOW-level input voltage
-
-
0.45
V
HIGH-level input voltage
VIH
except X1 clock,
LOWPWR pin
[1]
except X1 clock,
LOWPWR pin
LOWPWR pin
[1]
[2]
VOL
LOW-level output voltage
IOL = 2 mA
VOH
HIGH-level output voltage
IOH = −800 μA
ILIL
-
-
0.45
V
1.35
-
-
V
1.35
-
-
V
-
-
0.35
V
1.45
-
-
V
LOW-level input leakage
current
-
-
1
μA
ILIH
HIGH-level input leakage
current
-
-
1
μA
IL(clk)
clock leakage current
LOW-level
-
-
30
μA
HIGH-level
-
-
30
μA
IDD
supply current
-
-
2
mA
IDD(sleep)
sleep mode supply current
[3]
-
-
5
μA
IDD(lp)
low-power mode supply
current
[4]
-
-
5
μA
Ci
input capacitance
-
-
5
pF
[1]
Product data sheet
Typ
VIH(clk)
LOWPWR pin
SC16C852V
Min
f = 5 MHz
Hysteresis input.
[2]
Except XTAL2, VOL = 1 V typical.
[3]
Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
[4]
Activate by LOWPWR pin.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
39 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
10. Dynamic characteristics
Table 39. Dynamic characteristics
Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified.
Symbol
Parameter
fXTAL1
frequency on pin XTAL1
Conditions
[1]
Min
Typ
Max
Unit
-
-
80
MHz
td(CS-LLAH)
delay time from CS to LLA HIGH
10
-
-
ns
tsu(A-LLAH)
set-up time from address to LLA HIGH
5
-
-
ns
tw(LLA)
LLA pulse width time
10
-
-
ns
th(LLAH-A)
address hold time after LLA HIGH
10
-
-
ns
10
-
-
ns
-
-
40
ns
td(IOW)
IOW delay time
td(IOR-DV)
delay time from IOR to data valid
tw(IOR)
IOR pulse width time
20
-
-
ns
td(LLAH-IORL)
delay time from LLA HIGH to IOR LOW
10
-
-
ns
25 pF load
tw(IOW)
IOW pulse width time
10
-
-
ns
th(IOWH-D)
data input hold time after IOW HIGH
5
-
-
ns
td(LLAH-IOWL)
delay time from LLA HIGH to IOW LOW
10
-
-
ns
tsu(D-IOWH)
set-up time from data input to IOW HIGH
5
-
-
ns
td(IOR)
IOR delay time
10
-
-
ns
tdis(IOR-QZ)
disable time from IOR to high-impedance data
output[2]
25 pF load
-
-
20
ns
td(IOW-Q)
delay time from IOW to data output
25 pF load
-
-
50
ns
td(modem-INT)
delay time from modem to INT
25 pF load
-
-
50
ns
td(IOR-INTL)
delay time from IOR to INT LOW
25 pF load
-
-
50
ns
tWH
pulse width HIGH
6
-
-
ns
tWL
pulse width LOW
6
-
-
ns
tw(clk)
clock pulse width
td(stop-INT)
delay time from stop to INT
12.5
-
-
ns
25 pF load
[3]
-
-
1TRCLK
s
[3]
-
-
1TRCLK
s
-
-
50
ns
td(stop-RXRDY)
delay time from stop to RXRDY
25 pF load
td(IOR-RXRDYH)
delay time from IOR to RXRDY HIGH
25 pF load
25 pF load
td(start-INT)
delay time from start to INT
td(IOW-TX)
delay time from IOW to TX
td(IOW-INTL)
delay time from IOW to INT LOW
25 pF load
td(IOW-TXRDYH)
delay time from IOW to TXRDY HIGH
25 pF load
td(start-TXRDY)
delay time from start to TXRDY
tw(RESET_N)
pulse width on pin RESET
[1]
[3]
25 pF load
[3]
-
-
1TRCLK
s
8TRCLK
-
24TRCLK
s
-
-
50
ns
-
-
50
ns
-
-
8TRCLK
s
10
-
-
ns
External clock only; maximum crystal frequency is 24 MHz.
[2]
10 % of the data bus fall or rise time.
[3]
RCLK is an internal frequency and it is equal to 16 times the baud rate.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
40 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
10.1 Timing diagrams
AD7 to AD0
upper address
lower address
tsu(A-LLAH)
data
th(LLAH-A)
CS
td(CS-LLAH)
th(IOWH-D)
tw(LLA)
LLA
tsu(D-IOWH)
td(LLAH-IOWL)
tw(IOW)
td(IOW)
IOW
002aac354
Fig 10. General write timing
AD7 to AD0
upper address
lower address
tsu(A-LLAH)
data
th(LLAH-A)
tdis(IOR-QZ)
CS
td(CS-LLAH)
tw(LLA)
LLA
td(IOR-DV)
td(IOR)
td(LLAH-IORL)
tw(IOR)
IOR
002aac355
Fig 11. General read timing
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
41 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
active
IOW
td(IOW-Q)
RTSA, RTSB
DTRA, DTRB
change of state
change of state
CDA, CDB
CTSA, CTSB
DSRA, DSRB
change of state
change of state
td(modem-INT)
INTA, INTB
td(modem-INT)
active
active
active
td(IOR-INTL)
active
IOR
active
active
td(modem-INT)
change of state
RIA, RIB
002aac356
Fig 12. Modem input/output timing
tWL
tWH
external clock
tw(clk)
002aac357
1
f XTAL1 = -------------t w ( clk )
Fig 13. External clock timing
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
42 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
start
bit
RXA, RXB
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
td(stop-INT)
7 data bits
active
INTA, INTB
td(IOR-INTL)
active
IOR
16 baud rate clock
002aac358
Fig 14. Receive timing
start
bit
RXA, RXB
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
td(stop-RXRDY)
active data
ready
RXRDYA
RXRDYB
td(IOR-RXRDYH)
active
IOR
002aac359
Fig 15. Receive ready timing in non-FIFO mode
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
43 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
start
bit
D0
RXA, RXB
parity
bit
data bits (0 to 7)
D1
D2
D3
D4
D5
D6
stop
bit
D7
first byte that
reaches the
trigger level
td(stop-RXRDY)
active data
ready
RXRDYA
RXRDYB
td(IOR-RXRDYH)
active
IOR
002aac360
Fig 16. Receive ready timing in FIFO mode
start
bit
TXA, TXB
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
7 data bits
active
transmitter ready
INTA, INTB
td(start-INT)
td(IOW-TX)
IOW
td(IOW-INTL)
active
active
16 baud rate clock
002aac361
Fig 17. Transmit timing
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
44 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
start
bit
D0
TXA, TXB
IOW
parity
bit
data bits (0 to 7)
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
active
td(start-TXRDY)
AD0 to AD7
byte #1
td(IOW-TXRDYH)
TXRDYA
TXRDYB
active transmitter
ready
transmitter
not ready
002aac362
Fig 18. Transmit ready timing in non-FIFO mode
start
bit
data bits (0 to 7)
D0
TXA, TXB
parity
bit
D1
D2
D3
D4
D5
D6
stop
bit
D7
5 data bits
6 data bits
7 data bits
IOW
active
td(start-TXRDY)
AD0 to AD7
byte #32 or
byte #128
td(IOW-TXRDYH)
TXRDYA
TXRDYB
FIFO full
002aac363
Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
45 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
UART frame
start
data bits
0
TX data
1
0
1
0
stop
0
1
1
0
1
IrDA TX data
1/ bit time
2
bit
time
3/ bit time
16
002aaa212
Fig 20. Infrared transmit timing
IrDA RX data
bit
time
RX data
0 to 1 16× clock delay
0
1
0
1
start
0
0
data bits
1
1
0
1
stop
UART frame
002aaa213
Fig 21. Infrared receive timing
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
46 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
11. Package outline
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 x 6 x 0.85 mm
D
SOT778-3
A
B
terminal 1
index area
E
A
A1
c
detail X
C
e1
e
v
w
b
1/2 e
13
M
M
y
y1 C
C A B
C
24
L
25
12
e
e2
Eh
1/2 e
1
terminal 1
index area
36
48
37
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.25
0.15
0.2
6.1
5.9
3.95
3.65
6.1
5.9
3.95
3.65
0.4
4.4
4.4
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT778-3
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
04-06-16
04-06-23
Fig 22. Package outline SOT778-3 (HVQFN48)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
47 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm
B
D
SOT912-1
A
ball A1
index area
E
A
A2
A1
detail X
e1
1/2 e
e
v
w
b
F
M
M
C
C A B
C
y1 C
y
e
E
D
e2
C
B
1/2 e
A
ball A1
index area
1
2
3
4
5
6
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.15
0.25
0.15
0.90
0.75
0.35
0.25
3.6
3.4
3.6
3.4
0.5
2.5
2.5
0.15
0.05
0.08
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT912-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
05-08-09
05-09-01
Fig 23. Package outline SOT912-1 (TFBGA36)
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
48 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
49 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 40 and 41
Table 40.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 41.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
50 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 42.
SC16C852V
Product data sheet
Abbreviations
Acronym
Description
CPU
Central Processing Unit
DLL
Divisor Latch LSB
DLM
Divisor Latch MSB
DMA
Direct Memory Access
FIFO
First In, First Out
IrDA
Infrared Data Association
ISDN
Integrated Service Digital Network
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
RoHS
Restriction of Hazardous Substances directive
UART
Universal Asynchronous Receiver/Transmitter
VLIO
Variable Latency Input/Output
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
51 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
14. Revision history
Table 43.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SC16C852V v.5
20110121
Product data sheet
-
SC16C852V v.4
Modifications:
•
Table 38 “Static characteristics”:
– VIL(clk) specification: added condition “XTAL1 pin”
– VIH(clk) specification: added condition “XTAL1 pin”
– VIL specification split for condition “LOWPWR pin”.
– VIH specification split for condition “LOWPWR pin”.
– Added (new) Table note [1].
SC16C852V v.4
20080114
Product data sheet
-
SC16C852V v.3
SC16C852V v.3
20071015
Product data sheet
-
SC16C852V v.2
SC16C852V v.2
20070105
Product data sheet
-
SC16C852V v.1
SC16C852V v.1
20061031
Objective data sheet
-
-
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
52 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
53 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
SC16C852V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
© NXP B.V. 2011. All rights reserved.
54 of 55
SC16C852V
NXP Semiconductors
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
17. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
5.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Functional description . . . . . . . . . . . . . . . . . . . 9
6.1
UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9
6.2
Extended mode (128-byte FIFO) . . . . . . . . . . 10
6.3
Internal registers . . . . . . . . . . . . . . . . . . . . . . . 10
6.4
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4.1
32-byte FIFO mode . . . . . . . . . . . . . . . . . . . . 11
6.4.2
128-byte FIFO mode . . . . . . . . . . . . . . . . . . . 11
6.5
Hardware flow control . . . . . . . . . . . . . . . . . . . 11
6.6
Software flow control . . . . . . . . . . . . . . . . . . . 12
6.7
Special character detect . . . . . . . . . . . . . . . . . 13
6.8
Interrupt priority and time-out interrupts . . . . . 13
6.9
Programmable baud rate generator . . . . . . . . 14
6.10
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 16
6.11
Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16
6.12
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.12.1
Conditions to enter Sleep mode . . . . . . . . . . . 18
6.12.2
Conditions to resume normal operation . . . . . 18
6.13
Low power feature . . . . . . . . . . . . . . . . . . . . . 18
6.14
RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 19
6.14.1
Auto RS-485 RTS control . . . . . . . . . . . . . . . . 19
6.14.2
RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 19
6.14.3
Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 19
6.14.3.1 Normal Multi-drop mode . . . . . . . . . . . . . . . . . 19
6.14.3.2 Auto address detection . . . . . . . . . . . . . . . . . . 20
7
Register descriptions . . . . . . . . . . . . . . . . . . . 20
7.1
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . . 23
7.2
Interrupt Enable Register (IER) . . . . . . . . . . . 23
7.2.1
IER versus transmit/receive FIFO
interrupt mode operation . . . . . . . . . . . . . . . . 24
7.2.2
IER versus receive/transmit FIFO
polled mode operation . . . . . . . . . . . . . . . . . . 24
7.3
FIFO Control Register (FCR) . . . . . . . . . . . . . 25
7.3.1
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.1.1
Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 25
7.3.1.2
Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 25
7.3.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4
Interrupt Status Register (ISR) . . . . . . . . . . . . 27
7.5
Line Control Register (LCR) . . . . . . . . . . . . . . 28
7.6
Modem Control Register (MCR) . . . . . . . . . . . 29
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
8
9
10
10.1
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
16
17
Line Status Register (LSR) . . . . . . . . . . . . . .
Modem Status Register (MSR) . . . . . . . . . . .
Extra Feature Control Register (EFCR) . . . . .
Scratchpad Register (SPR) . . . . . . . . . . . . . .
Division Latch (DLL and DLM) . . . . . . . . . . . .
Transmit FIFO Level Count (TXLVLCNT) . . .
Receive FIFO Level Count (RXLVLCNT). . . .
Enhanced Feature Register (EFR) . . . . . . . .
Transmit Interrupt Level register (TXINTLVL)
Receive Interrupt Level register (RXINTLVL).
Flow Control Trigger Level High (FLWCNTH)
Flow Control Trigger Level Low (FLWCNTL) .
Clock prescaler (CLKPRES) . . . . . . . . . . . . .
RS-485 turn-around time delay (RS485TIME)
Advanced Feature Control Register 1
(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Feature Control Register 2
(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC16C852V external reset condition and
software reset . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
32
32
32
32
32
33
34
34
35
35
35
36
36
37
38
39
39
40
41
47
49
49
49
49
50
51
52
53
53
53
53
54
54
55
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 January 2011
Document identifier: SC16C852V
Similar pages