Data Sheet

SC28L92
3.3 V/5.0 V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Rev. 07 — 19 December 2007
Product data sheet
1. General description
The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating
at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on
power-up is that of the SC26C92. Its differences from the SCC2692 and SC26C92 are:
16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver,
mode register 0 is added, extended baud rate and overall faster speeds, programmable
receiver and transmitter interrupts. (Neither the SC26C92 nor the SCC2692 is being
discontinued.)
Pin programming will allow the device to operate with either the Motorola or Intel bus
interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO
mode if strict compliance with the SC26C92 FIFO structure is required.
The NXP Semiconductors SC28L92 Dual Universal Asynchronous Receiver/Transmitter
(DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex
asynchronous receiver/transmitter channels in a single package. It interfaces directly with
microprocessors and may be used in a polled or interrupt driven system with modem and
DMA interface.
The operating mode and data format of each channel can be programmed independently.
Additionally, each receiver and transmitter can select its operating speed as one of 28
fixed baud rates; a 16× clock derived from a programmable counter/timer, or an external
1× or 16× clock. The baud rate generator and counter/timer can operate directly from a
crystal or from external clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly attractive for
dual-speed channel applications such as clustered terminal systems.
Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the
potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in
interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS
signaling to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit
output port. These can be used as general purpose I/O ports or can be assigned specific
functions (such as clock inputs or status/interrupt outputs) under program control.
The SC28L92 is available in three package versions: PLCC44, QFP44, and HVQFN48.
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
2. Features
n Member of IMPACT family: 3.3 V to 5.0 V, −40 °C to +85 °C and 68xxx or 80xxx bus
interface for all devices
n Dual full-duplex independent asynchronous receiver/transmitters
n 16 character FIFOs for each receiver and transmitter
n Pin programming selects 68xxx or 80xxx bus interface
n Programmable data format
u 5 data to 8 data bits plus parity
u Odd, even, no parity or force parity
u 1 stop, 1.5 stop or 2 stop bits programmable in 1⁄16-bit increments
n 16-bit programmable counter/timer
n Programmable baud rate for each receiver and transmitter selectable from:
u 28 fixed rates: 50 kBd to 230.4 kBd
u Other baud rates to 1 MHz at 16×
u Programmable user-defined rates derived from a programmable counter/timer
u External 1× or 16× clock
n Parity, framing, and overrun error detection
n False start bit detection
n Line break detection and generation
n Programmable channel mode
u Normal (full-duplex)
u Automatic echo
u Local loopback
u Remote loopback
u Multi-drop mode (also called wake-up or 9-bit)
n Multi-function 7-bit input port (includes IACKN)
u Can serve as clock or control inputs
u Change of state detection on four inputs
u Inputs have typically > 100 kΩ pull-up resistors
u Change of state detectors for modem control
n Multi-function 8-bit output port
u Individual bit set/reset capability
u Outputs can be programmed to be status/interrupt signals
u FIFO status for DMA interface
n Versatile interrupt system
u Single interrupt output with eight maskable interrupting conditions
u Output port can be configured to provide a total of up to six separate interrupt
outputs that may be wire ORed
u Each FIFO can be programmed for four different interrupt levels
u Watchdog timer for each receiver
n Maximum data transfer rates: 1× - 1 Mbit/s, 16× - 1 Mbit/s
n Automatic wake-up mode for multi-drop applications
n Start-end break interrupt/status
n Detects break which originates in the middle of a character
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
2 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
n
n
n
n
n
On-chip crystal oscillator
Power-down mode
Receiver time-out mode
Single 3.3 V or 5 V power supply
Powers up to emulate SC26C92
3. Ordering information
Table 1.
Ordering information
VCC = 3.3 V ± 10 % or VCC = 5.0 V ± 10 %; Tamb = −40 °C to +85 °C
Type number
Package
Name
Description
Version
SC28L92A1A
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
SC28L92A1B
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2
SC28L92A1BS
HVQFN48
plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 × 6 × 0.85 mm
SOT778-4
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
3 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
4. Block diagram
SC28L92 (80xxx mode)
8
D0 to D7
CHANNEL A
BUS BUFFER
16-BYTE
TRANSMIT FIFO
RDN
OPERATION
CONTROL
TRANSMIT
SHIFT REGISTER
ADDRESS
DECODE
16-BYTE
RECEIVE FIFO
R/W CONTROL
WATCHDOG
TIMER
WRN
CEN
RESET
I/M
open or connect
to VCC for 80xxx
4
RxDA
RECEIVE
SHIFT REGISTER
INTERRUPT
CONTROL
MRA0, 1, 2, 3
IMR
CRA
ISR
SRA
INTRN
timing
control
GP
INTERNAL DATA BUS
A0 to A3
TxDA
TxDB
CHANNEL B
(AS ABOVE)
RxDB
INPUT PORT
TIMING
CHANGE-OFSTATE
DETECTORS (4)
BAUD RATE
GENERATOR
IPCR
7
IP0 to IP6
ACR
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
XTAL
OSCILLATOR
FUNCTION
SELECT LOGIC
CSRA
OPCR
CSRB
OPR
X1/CLK
X2
8
OP0 to OP7
ACR
CTL
CTU
002aad459
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0
(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually
means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed
from those above: Mark is low voltage, and Space is high voltage.
Fig 1. Block diagram (80xxx mode)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
4 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SC28L92 (68xxx mode)
8
D0 to D7
CHANNEL A
BUS BUFFER
16-BYTE
TRANSMIT FIFO
R/WN
IACKN
CEN
RESETN
I/M
ground for
68xxx mode
OPERATION
CONTROL
TRANSMIT
SHIFT REGISTER
ADDRESS
DECODE
16-BYTE
RECEIVE FIFO
R/W CONTROL
WATCHDOG
TIMER
4
RxDA
RECEIVE
SHIFT REGISTER
INTERRUPT
CONTROL
MRA0, 1, 2, 3
IMR
CRA
ISR
SRA
INTRN
DACKN
control
timing
GP
INTERNAL DATA BUS
A0 to A3
TxDA
TxDB
CHANNEL B
(AS ABOVE)
RxDB
INPUT PORT
TIMING
CHANGE-OFSTATE
DETECTORS (4)
BAUD RATE
GENERATOR
IPCR
6
IP0 to IP5
ACR
CLOCK
SELECTORS
X1/CLK
X2
COUNTER/
TIMER
OUTPUT PORT
XTAL
OSCILLATOR
FUNCTION
SELECT LOGIC
CSRA
OPCR
CSRB
OPR
8
OP0 to OP7
ACR
CTL
CTU
002aad460
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0
(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually
means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed
from those above: Mark is low voltage, and Space is high voltage.
Fig 2. Block diagram (68xxx mode)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
5 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5. Pinning information
n.c.
1
40 IP2
A0
2
41 IP6
IP3
3
42 IP5
A1
4
43 IP4
IP1
5
44 VCC
A2
6
5.1 Pinning
A3
7
39 CEN
IP0
8
38 RESET
WRN
9
37 X2
RDN 10
36 X1/CLK
RxDB 11
35 RxDA
SC28L92A1A
I/M 12
34 n.c.
(80xxx mode)
TxDB 13
33 TxDA
D4 26
D2 27
D0 28
42 IP5
41 IACKN
40 IP2
D6 25
INTRN 24
n.c. 23
GND 22
29 OP6
D7 21
30 OP4
OP7 17
D5 20
31 OP2
OP5 16
D3 19
32 OP0
OP3 15
D1 18
OP1 14
002aad412
A1
IP3
A0
n.c.
4
3
2
1
43 IP4
IP1
5
44 VCC
A2
6
Fig 3. Pin configuration for PLCC44; 80xxx mode
A3
7
39 CEN
IP0
8
38 RESETN
R/WN
9
37 X2
DACKN 10
36 X1/CLK
RxDB 11
35 RxDA
SC28L92A1A
I/M 12
34 n.c.
(68xxx mode)
TxDB 13
33 TxDA
D0 28
D2 27
D4 26
D6 25
INTRN 24
n.c. 23
GND 22
29 OP6
D7 21
30 OP4
OP7 17
D5 20
31 OP2
OP5 16
D3 19
32 OP0
OP3 15
D1 18
OP1 14
002aad413
Fig 4. Pin configuration for PLCC44; 68xxx mode
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
6 of 73
SC28L92
NXP Semiconductors
34 IP2
35 IP6
36 IP5
37 IP4
38 VCC
39 VCC
40 A0
41 IP3
42 A1
43 IP1
44 A2
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
A3
1
33 CEN
IP0
2
32 RESET
WRN
3
31 X2
RDN
4
30 X1/CLK
RxDB
5
29 RxDA
TxDB
6
SC28L92A1B
28 TxDA
OP1
7
(80xxx mode)
27 OP0
OP3
8
26 OP2
OP5
9
25 OP4
OP7 10
24 OP6
I/M 11
D6 19
D4 20
D2 21
D0 22
37 IP4
36 IP5
35 IACKN
34 IP2
INTRN 18
GND 17
GND 16
D7 15
D5 14
D3 13
D1 12
23 n.c.
002aad414
38 VCC
39 VCC
40 A0
41 IP3
42 A1
43 IP1
44 A2
Fig 5. Pin configuration for QFP44; 80xxx mode
A3
1
33 CEN
IP0
2
32 RESETN
R/WN
3
31 X2
DACKN
4
30 X1/CLK
RxDB
5
29 RxDA
TxDB
6
SC28L92A1B
28 TxDA
OP1
7
(68xxx mode)
27 OP0
OP3
8
26 OP2
OP5
9
25 OP4
OP7 10
24 OP6
I/M 11
D0 22
D2 21
D4 20
D6 19
INTRN 18
GND 17
GND 16
D7 15
D5 14
D3 13
D1 12
23 n.c.
002aad415
Fig 6. Pin configuration for QFP44; 68xxx mode
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
7 of 73
SC28L92
NXP Semiconductors
37 n.c.
38 IP2
39 IP6
40 IP5
41 IP4
42 VCC
43 n.c.
44 A0
45 IP3
46 A1
48 A2
terminal 1
index area
47 IP1
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
A3
1
36 n.c.
IP0
2
35 CEN
WRN
3
34 RESET
RDN
4
33 X2
RxDB
5
32 X1/CLK
n.c.
6
I/M
7
TxDB
8
29 OP0
OP1
9
28 OP2
OP3 10
27 OP4
OP5 11
26 OP6
OP7 12
25 n.c.
31 RxDA
SC28L92A1BS
30 TxDA
D2 22
D0 23
n.c. 24
39 IACKN
38 IP2
37 n.c.
D4 21
D6 20
INTRN 19
GND 18
D7 17
D5 16
D3 15
D1 14
n.c. 13
(80xxx mode)
002aad362
Transparent top view
40 IP5
42 VCC
41 IP4
43 n.c.
44 A0
45 IP3
46 A1
48 A2
terminal 1
index area
47 IP1
Fig 7. Pin configuration for HVQFN48; 80xxx mode
A3
1
36 n.c.
IP0
2
35 CEN
R/WN
3
34 RESETN
DACKN
4
33 X2
RxDB
5
32 X1/CLK
n.c.
6
I/M
7
TxDB
8
29 OP0
OP1
9
28 OP2
OP3 10
27 OP4
OP5 11
26 OP6
OP7 12
25 n.c.
31 RxDA
SC28L92A1BS
30 TxDA
n.c. 24
D0 23
D2 22
D4 21
D6 20
INTRN 19
GND 18
D7 17
D5 16
D3 15
D1 14
n.c. 13
(68xxx mode)
002aad363
Transparent top view
Fig 8. Pin configuration for HVQFN48; 68xxx mode
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
8 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5.2 Pin description
Table 2.
Symbol
Pin description for 80xxx bus interface (Intel)
Pin
Type
Description
PLCC44 QFP44 HVQFN48
I/M
12
11
7
I
Bus configuration: When HIGH or not connected configures the bus
interface to the conditions shown in this table.
D0
28
22
23
I/O
D1
18
12
14
I/O
D2
27
21
22
I/O
Data bus: Bidirectional 3-state data bus used to transfer commands,
data and status between the DUART and the CPU. D0 is the least
significant bit.
D3
19
13
15
I/O
D4
26
20
21
I/O
D5
20
14
16
I/O
D6
25
19
20
I/O
D7
21
15
17
I/O
CEN
39
33
35
I
Chip enable: Active LOW input signal. When LOW, data transfers
between the CPU and the DUART are enabled on D0 to D7 as
controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places
the D0 to D7 lines in the 3-state condition.
WRN
9
3
3
I
Write strobe: When LOW and CEN is also LOW, the contents of the
data bus is loaded into the addressed register. The transfer occurs on
the rising edge of the signal.
RDN
10
4
4
I
Read strobe: When LOW and CEN is also LOW, causes the contents
of the addressed register to be presented on the data bus. The read
cycle begins on the falling edge of RDN.
A0
2
40
44
I
A1
4
42
46
I
Address inputs: Select the DUART internal registers and ports for
read/write operations.
A2
6
44
48
I
A3
7
1
1
I
RESET
38
32
34
I
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR,
OPR and OPCR), puts OP0 to OP7 in the HIGH state, stops the
counter/timer, and puts channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to
MR1. See Figure 10.
INTRN
24
18
19
O
Interrupt request: Active LOW, open-drain, output which signals the
CPU that one or more of the eight maskable interrupting conditions are
true. This pin requires a pull-up device.
X1/CLK
36
30
32
I
Crystal 1: Crystal or external clock input. A crystal or clock of the
specified limits must be supplied at all times. When a crystal is used, a
capacitor must be connected from this pin to ground (see Figure 17).
X2
37
31
33
O
Crystal 2: Connection for other side of the crystal. When a crystal is
used, a capacitor must be connected from this pin to ground (see
Figure 17). If X1/CLK is driven from an external source, this pin must
be left open.
RxDA
35
29
31
I
Channel A receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (Figure 1).
RxDB
11
5
5
I
Channel B receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (Figure 1).
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
9 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 2.
Symbol
Pin description for 80xxx bus interface (Intel) …continued
Pin
Type
Description
PLCC44 QFP44 HVQFN48
TxDA
33
28
30
O
Channel A transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, Idle or when operating in local loopback mode.
See note on drive levels at block diagram (Figure 1).
TxDB
13
6
8
O
Channel B transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, Idle, or when operating in local loopback mode.
See note on drive levels at block diagram (Figure 1).
OP0
32
27
29
O
Output 0: General purpose output or channel A request to send
(RTSAN, active LOW). Can be deactivated automatically on receive or
transmit.
OP1
14
7
9
O
Output 1: General-purpose output or channel B request to send
(RTSBN, active LOW). Can be deactivated automatically on receive or
transmit.
OP2
31
26
28
O
Output 2: General purpose output, or channel A transmitter 1× or 16×
clock output, or channel A receiver 1× clock output.
OP3
15
8
10
O
Output 3: General purpose output or open-drain, active LOW
counter/timer output or channel B transmitter 1× clock output, or
channel B receiver 1× clock output.
OP4
30
25
27
O
Output 4: General purpose output or channel A open-drain, active
LOW, RxA interrupt ISR[1] output.
OP5
16
9
11
O
Output 5: General-purpose output or channel B open-drain, active
LOW, RxB interrupt ISR[5] output.
OP6
29
24
26
O
Output 6: General purpose output or channel A open-drain, active
LOW, TxA interrupt ISR[0] output.
OP7
17
10
12
O
Output 7: General-purpose output, or channel B open-drain, active
LOW, TxB interrupt ISR[4] output.
IP0
8
2
2
I
Input 0: General purpose input or channel A clear to send active LOW
input (CTSAN).
IP1
5
43
47
I
Input 1: General purpose input or channel B clear to send active LOW
input (CTSBN).
IP2
40
34
38
I
Input 2: General-purpose input or counter/timer external clock input.
IP3
3
41
45
I
Input 3: General purpose input or channel A transmitter external clock
input (TxCA). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
IP4
43
37
41
I
Input 4: General purpose input or channel A receiver external clock
input (RxCA). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
IP5
42
36
40
I
Input 5: General purpose input or channel B transmitter external clock
input (TxCB). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
IP6
41
35
39
I
Input 6: General purpose input or channel B receiver external clock
input (RxCB). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
VCC
44
38, 39
42
Pwr
Power Supply: 3.3 V ± 10 % or 5 V ± 10 % supply input.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
10 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 2.
Symbol
Pin description for 80xxx bus interface (Intel) …continued
Pin
Type
Description
Pwr
Ground
PLCC44 QFP44 HVQFN48
GND
22
n.c.
1, 23, 34 23
[1]
16, 17
18[1]
6, 13, 24, 25, Pwr
36, 37, 43
Not connected
HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 3.
Symbol
Pin description for 68xxx bus interface (Motorola)
Pin
Type
Description
PLCC44
QFP44 HVQFN48
I/M
12
11
7
I
Bus configuration: When LOW configures the bus interface to the
conditions shown in this table.
D0
28
22
23
I/O
D1
18
12
14
I/O
D2
27
21
22
I/O
Data bus: Bidirectional 3-state data bus used to transfer commands,
data and status between the DUART and the CPU. D0 is the least
significant bit.
D3
19
13
15
I/O
D4
26
20
21
I/O
D5
20
14
16
I/O
D6
25
19
20
I/O
D7
21
15
17
I/O
CEN
39
33
35
I
Chip enable: Active LOW input signal. When LOW, data transfers
between the CPU and the DUART are enabled on D0 to D7 as
controlled by the R/WN and A0 to A3 inputs. When HIGH, places the
D0 to D7 lines in the 3-state condition.
R/WN
9
3
3
I
Read/Write: Input signal. When CEN is LOW, R/WN HIGH input
indicates a read cycle; when LOW indicates a write cycle.
IACKN
41
35
39
I
Interrupt acknowledge: Active LOW input indicating an interrupt
acknowledge cycle. Usually asserted by the CPU in response to an
interrupt request. When asserted places the interrupt vector on the
bus and asserts DACKN.
DACKN
10
4
4
O
Data transfer acknowledge: A3-state active LOW output asserted in
a write, read, or interrupt acknowledge cycle to indicate proper
transfer of data between the CPU and the DUART.
A0
2
40
44
I
A1
4
42
46
I
Address inputs: Select the DUART internal registers and ports for
read/write operations.
A2
6
44
48
I
A3
7
1
1
I
32
34
I
RESETN 38
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR,
OPR, OPCR), puts OP0 to OP7 in the HIGH state, stops the
counter/timer, and puts channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to
MR1. See Figure 10.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
11 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 3.
Symbol
Pin description for 68xxx bus interface (Motorola) …continued
Pin
Type
Description
19
O
Interrupt request: Active LOW, open-drain, output which signals the
CPU that one or more of the eight maskable interrupting conditions
are true. This pin requires a pull-up.
30
32
I
Crystal 1: Crystal or external clock input. A crystal or clock of the
specified limits must be supplied at all times. When a crystal is used, a
capacitor must be connected from this pin to ground (see Figure 17).
37
31
33
O
Crystal 2: Connection for other side of the crystal. When a crystal is
used, a capacitor must be connected from this pin to ground (see
Figure 17). If X1/CLK is driven from an external source, this pin must
be left open.
RxDA
35
29
31
I
Channel A receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (Figure 2).
RxDB
11
5
5
I
Channel B receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (Figure 2).
TxDA
33
28
30
O
Channel A transmitter serial data output: The least significant bit is
transmitted first. This output is held in the ‘mark condition when the
transmitter is disabled, idle or when operating in local loopback mode.
See note on drive levels at block diagram (Figure 2).
TxDB
13
6
8
O
Channel B transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, idle, or when operating in local loopback mode.
See note on drive levels at block diagram (Figure 2).
OP0
32
27
29
O
Output 0: General purpose output or channel A request to send
(RTSAN, active LOW). Can be deactivated automatically on receive or
transmit.
OP1
14
7
9
O
Output 1: General purpose output or channel B request to send
(RTSBN, active LOW). Can be deactivated automatically on receive or
transmit.
OP2
31
26
28
O
Output 2: General purpose output, or channel A transmitter 1× or 16×
clock output, or channel A receiver 1× clock output.
OP3
15
8
10
O
Output 3: General purpose output or open-drain, active LOW
counter/timer output or channel B transmitter 1× clock output, or
channel B receiver 1× clock output.
OP4
30
25
27
O
Output 4: General purpose output or channel A open-drain, active
LOW, RxA interrupt ISR [1] output.
OP5
16
9
11
O
Output 5: General purpose output or channel B open-drain, active
LOW, RxB interrupt ISR[5] output.
OP6
29
24
26
O
Output 6: General purpose output or channel A open-drain, active
LOW, TxA interrupt ISR[0] output.
OP7
17
10
12
O
Output 7: General purpose output, or channel B open-drain, active
LOW, TxB interrupt ISR[4] output.
IP0
8
2
2
I
Input 0: General purpose input or channel A clear to send active LOW
input (CTSAN).
IP1
5
43
47
I
Input 1: General purpose input or channel B clear to send active LOW
input (CTSBN).
IP2
40
34
38
I
Input 2: General purpose input or counter/timer external clock input.
PLCC44
QFP44 HVQFN48
INTRN
24
18
X1/CLK
36
X2
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Table 3.
Symbol
Pin description for 68xxx bus interface (Motorola) …continued
Pin
Type
Description
45
I
Input 3: General purpose input or channel A transmitter external clock
input (TxCA). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
37
41
I
Input 4: General purpose input or channel A receiver external clock
input (RxCA). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
42
36
40
I
Input 5: General purpose input or channel B transmitter external clock
input (TxCB). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
44
38, 39
42
Pwr
Power Supply: 3.3 V ± 10 % or 5 V ± 10 % supply input.
16, 17
18[1]
Pwr
Ground
6, 13, 24,
25, 36, 37,
43
-
Not connected
PLCC44
QFP44 HVQFN48
IP3
3
41
IP4
43
IP5
VCC
GND
22
n.c.
1, 23, 34 23
[1]
HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. Functional description
6.1 Block diagram
The SC28L92 DUART consists of the following eight major sections: data bus buffer,
operation control, interrupt control, timing, communications channels A and B, input port
and output port. Refer to Section 4 “Block diagram”.
6.1.1 Data bus buffer
The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the operation control block to allow read and write operations to take place
between the controlling CPU and the DUART.
6.1.2 Operation control
The operation control logic receives operation commands from the CPU and generates
appropriate signals to internal sections to control device operation. It contains address
decoding and read and write circuits to permit communications with the microprocessor
via the data bus.
6.1.3 Interrupt control
A single active LOW interrupt output (INTRN) is provided which is activated upon the
occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be asserted. The ISR
can be read by the CPU to determine all currently active interrupting conditions. Outputs
OP3 to OP7 can be programmed to provide discrete interrupt outputs for the transmitter,
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receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their
output buffers are changed to the open-drain active LOW configuration. The OP pins may
be used for DMA and modem control as well (see Section 7.4).
6.1.4 FIFO configuration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to
operate at a fill capacity of either 8 bytes or 16 bytes. This feature may be used if it is
desired to operate the SC28L92 in strict compliance with the SC26C92. The 8 byte or
16 byte mode is controlled by the MR0A[3] bit. A logic 0 value for this bit sets the 8-bit
mode (the default); a logic 1 sets the 16 byte mode. MR0A bit 3 sets the FIFO size for both
channels.
The FIFO fill interrupt level automatically follow the programming of the MR0A[3] bit. See
Table 25 and Table 26.
6.1.5 68xxx mode
When the I/M pin is connected to GND (ground), the operation of the SC28L92 switches to
the bus interface compatible with the Motorola bus interfaces. Several of the pins change
their function as follows:
IP6 becomes IACKN input
RDN becomes DACKN
WRN becomes R/WN
The interrupt vector is enabled and the interrupt vector will be placed on the data bus
when IACKN is asserted LOW. The interrupt vector register is located at address 0xC. The
contents of this register are set to 0x0F on the application of RESETN.
The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay
from the falling edge of CEN. If the CEN is withdrawn before two edges of the X1 clock
occur, the generation of DACKN is terminated. Systems not strictly requiring DACKN
may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the
bus cycle time.
6.2 Timing circuits
6.2.1 Crystal clock
The timing block consists of a crystal oscillator, a baud rate generator, a programmable
16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from
a crystal connected across the X1/CLK and X2 inputs. If an external clock of the
appropriate frequency is available, it may be connected to X1/CLK. The clock serves as
the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and
other internal circuits. A clock signal within the limits specified in Section 10 “Dynamic
characteristics” must always be supplied to the DUART. If an external clock is used
instead of a crystal, X1 should be driven using a configuration similar to the one in
Figure 17. Nominal crystal rate is 3.6864 MHz. Rates up to 8 MHz may be used.
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6.2.2 Baud rate generator
The baud rate generator operates from the oscillator or external clock input at the X1 input
and is capable of generating 28 commonly used data communications baud rates ranging
from 50 kBd to 38.4 kBd. Programming bit 0 of MR0 to a logic 1 gives additional baud
rates of 57.6 kBd, 115.2 kBd and 230.4 kBd (500 kHz with X1 at 8.0 MHz). Note that the
MR0A[2:0] control this change and that the change applies to both channels. MR0B[2:0]
are reserved.
The baud rates are based on an input frequency of 3.6864 MHz. Changing the X1
frequency will change all baud rates by ratio of 3.6864 MHz to the new frequency. All rates
generated by the BRG will be in the 16× mode. The clock outputs from the BRG are at 16×
the actual baud rate.
The counter/timer can be used as a timer to produce a 16× clock for any other baud rate
by counting down the crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and transmitter, of any of these baud rates or
external timing signal. The use of the counter/timer also requires the generation of a
frequency 16× of the baud rate. See Section 6.2.3.
6.2.3 Counter/timer
The Counter/timer is a 16-bit programmable divider that operates in one of three modes:
counter, timer and time-out. In the timer mode it generates a square wave. In the counter
mode it generates a time delay. In the time-out mode it monitors the time between
received characters. The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTLR) and the Counter/Timer Upper Register (CTUR) as its divisor.
The counter/timer clock source and mode of operation (counter or timer) is selected by the
Auxiliary Control Register bits 6 to 4 (ACR[6:4]). The output of the counter/timer may be
used for a baud rate and/or may be output to the OP pins for some external function that
may be totally unrelated to data transmission. The counter/timer also sets the
counter/timer ready bit in the Interrupt Status Register (ISR) when its output transitions
from logic 1 to logic 0. A register read address (see Table 4) is reserved to issue a start
counter/timer command and a second register read address is reserved to issue a stop
command. The value of D[7:0] is ignored. The START command always loads the
contents of CTUR, CTLR to the counting registers. The STOP command always resets
the ISR[3] bit in the interrupt status register.
6.2.4 Timer mode
In the timer mode a symmetrical square wave is generated whose half period is equal in
time to division of the selected counter/timer clock frequency by the 16-bit number loaded
in the CTLR CTUR. Thus, the frequency of the counter/timer output will be equal to the
counter/timer clock frequency divided by twice the value of the CTUR CTLR. While in the
timer mode the ISR bit 3 (ISR[3]) will be set each time the counter/timer transitions from
logic 1 to logic 0 (HIGH-to-LOW). This continues regardless of issuance of the stop
counter command. ISR[3] is reset by the stop counter command.
Note: Reading of the CTU and CTL registers in the timer mode is not meaningful. When
the C/T is used to generate a baud rate and the C/T is selected through the CSR then the
receivers and/or transmitter will be operating in the 16× mode. Calculation for the
number n to program the counter/timer upper and lower registers is shown in Equation 1.
The value of the divisor n is
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counter/timer input clock
n = -------------------------------------------------------------------------2 × 16 × ( desired baud rate )
(1)
Often this division will result in a non-integer number; 26.3 for example. One may only
program integer numbers to a digital divider. Therefore 26 (0x1A) would be chosen. If 26.7
were the result of the division, then 27 (0x1B) would be chosen. This gives a baud rate
error of 0.3/26.3 or 0.3/26.7 that yields a percentage error of 1.14 % or 1.12 %
respectively, well within the ability of the asynchronous mode of operation. Higher input
frequency to the counter reduces the error effect of the fractional division.
6.2.5 Counter mode
In the counter mode the counter/timer counts the value of the CTLR CTUR down to zero
and then sets the ISR[3] bit and sets the counter/timer output from 1 to 0. It then rolls over
to 65,365 and continues counting with no further observable effect. Reading the C/T in the
counter mode outputs the present state of the C/T. If the C/T is not stopped, a read of the
C/T may result in changing data on the data bus.
6.2.6 Time-out mode
The time-out mode uses the received data stream to control the counter. The time-out
mode forces the C/T into the timer mode. Each time a received character is transferred
from the shift register to the Rx FIFO, the counter is restarted. If a new character is not
received before the counter reaches zero count, the counter ready bit is set, and an
interrupt can be generated. This mode can be used to indicate when data has been left in
the Rx FIFO for more than the programmed time limit. If the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and the message ends
before the FIFO is full, the CPU will not be interrupted for the remaining characters in the
Rx FIFO.
By programming the C/T such that it would time-out in just over one character time, the
above situation could be avoided. The processor would be interrupted any time the data
stream had stopped for more than one character time. Note: This is very similar to the
watchdog time of MR0. The difference is in the programmability of the delay time and that
the watchdog timer is restarted by either a receiver load to the Rx FIFO or a system read
from it.
This mode is enabled by writing the appropriate command to the command register.
Writing 0xA to CRA or CRB will invoke the time-out mode for that channel. Writing 0xC to
CRA or CRB will disable the time-out mode. Only one receiver should use this mode at a
time. However, if both are on, the time-out occurs after both receivers have been inactive
for the time-out period. The start of the C/T will be on the logic OR of the two receivers.
The time-out mode disables the regular start counter or stop counter commands and puts
the C/T into counter mode under the control of the received data stream. Each time a
received character is transferred from the shift register to the Rx FIFO, the C/T is stopped
after one C/T clock, reloaded with the value in CTUR and CTLR and then restarted on the
next C/T clock. If the C/T is allowed to end the count before a new character has been
received, the counter ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an
interrupt. Since receiving a character restarts the C/T, the receipt of a character after the
C/T has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the
Set Time-out Mode On command, CRx = 0xA, will also clear the counter ready bit and
stop the counter until the next character is received. The counter/timer is controlled with
six commands: Start/Stop C/T, Read/Write Counter/Timer lower register and Read/Write
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Counter/Timer upper register. These commands have slight differences depending on the
mode of operation. Please see the detail of the commands in Section 7.3.3 “Command
registers”.
6.2.7 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be
a false interrupt, i.e., an interrupt without a cause. This may result when a time-out
interrupt occurs and then, before the interrupt is serviced, another character is received,
i.e., the data stream has started again. (The interrupt latency is longer than the pause in
the data stream.) In this case, when a new character has been received, the counter/timer
will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the
interrupt service begins for the previously seen interrupt, a read of the ISR will show the
Counter Ready bit not set. If nothing else is interrupting, this read of the ISR will return a
0x00 character. This action may present the appearance of a spurious interrupt.
6.2.8 Communications channels A and B
Each communications channel of the SC28L92 comprises a full-duplex asynchronous
receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud rate generator, the counter/timer, or from an
external input. The transmitter accepts parallel data from the CPU, converts it to a serial
bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a
composite serial stream of data on the TxD output pin. The receiver accepts serial data on
the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity
bit (if any), or break condition and sends an assembled character to the CPU via the
receive FIFO. Three status bits (break received, framing and parity errors) are also
FIFOed with each data character.
6.2.9 Input port
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the CPU by
performing a read operation at address 0xD. A HIGH input results in a logic 1 while a LOW
input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also
serve as auxiliary inputs to certain portions of the DUART logic, modem and DMA.
Four change-of-state detectors are provided which are associated with inputs IP3, IP2,
IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH transition of these inputs, lasting longer
than 25 µs to 50 µs, will set the corresponding bit in the input port change register. The
bits are cleared when the register is read by the CPU. Any change of state can also be
programmed to generate an interrupt to the CPU.
The input port change of state detection circuitry uses a 38.4 kHz sampling clock derived
from one of the baud rate generator taps. This results in a sampling period of slightly more
than 25 µs (this assumes that the clock input is 3.6864 MHz). The detection circuitry, in
order to guarantee that a true change in level has occurred, requires two successive
samples at the new logic level be observed. As a consequence, the minimum duration of
the signal change is 25 µs if the transition occurs coincident with the first sample pulse.
The 50 µs time refers to the situation in which the change of state is just missed and the
first change of state is not detected until 25 µs later.
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6.2.10 Output port
The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR
and ROPR registers. The OPCR register controls the source of the data for the output
ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by
the MR and CR registers. When the OPR is the source of the data for the output ports, the
data at the ports is inverted from that in the OPR register. The content of the OPR register
is controlled by the set output port bits command and the reset output bits command.
These commands are at 0xE and 0xF, respectively. When these commands are used,
action takes place only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the set output port bits command will result in OPR5
being set to one. The OP5 would then be set to zero (VSS). Similarly, a one in bit position 5
of the data word associated with the reset output ports bits command would set OPR5 to
zero and, hence, the pin OP5 to a one (VDD).
These pins along with the IP pins and their change-of-state detectors are often used for
modem and DMA control.
6.3 Operation
6.3.1 Transmitter
The SC28L92 is conditioned to transmit data when the transmitter is enabled through the
command register. The SC28L92 indicates to the CPU that it is ready to accept a
character by setting the TxRDY bit in the status register. This condition can be
programmed to generate an interrupt request at OP6 or OP7 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMPT bits will be set in the status
register. When a character is loaded to the transmit FIFO the TxEMPT bit will be reset.
The TxEMPT will not set until: 1) the transmit FIFO is empty and the transmit shift register
has finished transmitting the stop bit of the last character written to the transmit FIFO, or
2) the transmitter is disabled and then re-enabled. The TxRDY bit is set whenever the
transmitter is enabled and the Tx FIFO is not full. Data is transferred from the holding
register to transmit shift register when it is idle or has completed transmission of the
previous character. Characters cannot be loaded into the Tx FIFO while the transmitter is
disabled.
The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD
output pin. It automatically sends a start bit followed by the programmed number of data
bits, an optional parity bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new character is not
available in the Tx FIFO, the TxD output remains HIGH and the TxEMT bit in the Status
Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when
the CPU loads a new character into the Tx FIFO.
If the transmitter is disabled it continues operating until the character currently being
transmitted and any characters in the Tx FIFO, including parity and stop bits, have been
transmitted. New data cannot be loaded to the Tx FIFO when the transmitter is disabled.
When the transmitter is reset it stops sending data immediately.
The transmitter can be forced to send a break (a continuous LOW condition) by issuing a
START BREAK command via the CR register. The break is terminated by a STOP BREAK
command or a transmitter reset.
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If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be LOW in order
for the character to be transmitted. The transmitter will check the state of the CTS input at
the beginning of each character transmitted. If it is found to be HIGH, the transmitter will
delay the transmission of any following characters until the CTS has returned to the LOW
state. CTS going HIGH during the serialization of a character will not affect that character.
The transmitter can also control the RTSN outputs, OP0 or OP1 via MR2[5]. When this
mode of operation is set, the meaning of the OP0 or OP1 signals will usually be end of
message. See description of bit MR2[5] in Table 30 “MR2A - Mode Register 2 channel A
(address 0x0) bit description” for more detail. This feature may be used to automatically
turn around a transceiver in simplex systems.
6.3.2 Receiver
The SC28L92 is conditioned to receive data when enabled through the command register.
The receiver looks for a HIGH-to-LOW (mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16×
clock for 7 clocks to 1⁄2 clocks (16× clock mode) or at the next rising edge of the bit time
clock (1× clock mode). If RxD is sampled HIGH, the start bit is invalid and the search for a
valid start bit begins again. If RxD is still LOW, a valid start bit is assumed and the receiver
continues to sample the input at one bit time intervals at the theoretical center of the bit,
until the proper number of data bits and parity bit (if any) have been assembled, and one
stop bit has been detected. The least significant bit is received first. The data is then
transferred to the receive FIFO and the RxRDY bit in the SR is set to a 1. This condition
can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character
length is less than 8 bits, the most significant unused bits in the Rx FIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for the next start bit.
However, if a non-zero character was received without a stop bit (framing error) and RxD
remains LOW for one half of the bit period after the stop bit was sampled, then the
receiver operates as if a new start bit transition had been detected at that point (one-half
bit time after the stop bit was sampled).
The parity error, framing error and overrun error (if any) are strobed into the SR from the
next byte to be read from the Rx FIFO. If a break condition is detected (RxD is LOW for
the entire character including the stop bit), a character consisting of all zeros will be
loaded into the Rx FIFO and the received break bit in the SR is set to 1. The RxD input
must return to HIGH for two (2) clock edges of the X1 crystal clock for the receiver to
recognize the end of the break condition and begin the search for a start bit.
This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the
clock of the controller is not synchronous to the X1 clock.
6.3.3 Transmitter reset and disable
Note the difference between transmitter disable and reset. A transmitter reset stops
transmitter action immediately, clears the transmitter FIFO and returns the idle state. A
transmitter disable withdraws the transmitter interrupts but allows the transmitter to
continue operation until all bytes in its FIFO and shift register have been transmitted
including the final stop bits. It then returns to its idle state.
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6.3.4 Receiver FIFO
The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16
characters. Data is loaded from the receive shift register into the topmost empty position
of the FIFO. The RxRDY bit in the status register is set whenever one or more characters
are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled
with data. Either of these bits can be selected to cause an interrupt. A read of the Rx FIFO
outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its
associated status bits (see Section 6.3.5) are popped thus emptying a FIFO position for
new data.
A disabled receiver with data in its FIFO may generate an interrupt (see Section 6.3.5). Its
status bits remain active and its watchdog, if enabled, will continue to operate.
6.3.5 Receiver status bits
In addition to the data word, three status bits (parity error, framing error and received
break) are also appended to each data character in the FIFO. The overrun error, MR1[5],
is not FIFOed.
Status can be provided in two ways, as programmed by the error mode control bit in the
mode register. In the character mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO. In the block mode,
the status provided in the SR for these three bits is the logic OR of the status for all
characters coming to the top of the FIFO since the last reset error from the command
register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is
popped only when the Rx FIFO is read. Therefore the status register should be read prior
to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive
shift register until a FIFO position is available. If an additional character is received while
this state exits, the contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4]) will be set upon receipt of the
start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid start bit was received and the FIFO is full.
When a FIFO position becomes available, the RTSN output will be reasserted (set LOW)
automatically. This feature can be used to prevent an overrun, in the receiver, by
connecting the RTSN output to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters can be read. However, no additional
characters can be received until the receiver is enabled again. If the receiver is reset, the
FIFO and all of the receiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is enabled again.
6.3.6 Receiver reset and disable
Receiver disable stops the receiver immediately. Data being assembled in the receiver
shift register is lost. Data and status in the FIFO is preserved and may be read. A
re-enable of the receiver after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
20 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
A receiver reset will discard the present shift register date, reset the receiver ready bit
(RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO
read/write pointers.
6.3.7 Watchdog
A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The
purpose of this timer is to alert the control processor that characters are in the Rx FIFO
which have not been read. This situation may occur at the end of a transmission when the
last few characters received are not sufficient to cause an interrupt.
This counter times out after 64 bit times. It is reset each time a character is transferred
from the receiver shift register to the Rx FIFO or a read of the Rx FIFO is executed.
6.3.8 Receiver time-out mode
In addition to the watchdog timer described in Section 6.3.7, the counter/timer may be
used for a similar function. Its programmability, of course, allows much greater precision of
time-out intervals.
The time-out mode uses the received data stream to control the counter. Each time a
received character is transferred from the shift register to the Rx FIFO, the counter is
restarted. If a new character is not received before the counter reaches zero count, the
counter ready bit is set, and an interrupt can be generated. This mode can be used to
indicate when data has been left in the Rx FIFO for more than the programmed time limit.
Otherwise, if the receiver has been programmed to interrupt the CPU when the receive
FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is
data left in the FIFO. The CTU and CTL value would be programmed for just over one
character time, so that the CPU would be interrupted as soon as it has stopped receiving
continuous data. This mode can also be used to indicate when the serial line has been
marking for longer than the programmed time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last character received has started the count. If
there is no new data during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
The time-out mode is enabled by writing the appropriate command to the command
register. Writing 0xA to CRA or CRB will invoke the time-out mode for that channel.
Writing 0xC to CRA or CRB will disable the time-out mode. The time-out mode should
only be used by one channel at once, since it uses the C/T. If, however, the time-out mode
is enabled from both receivers, the time-out will occur only when both receivers have
stopped receiving data for the time-out period. CTU and CTL must be loaded with a value
greater than the normal receive character period. The time-out mode disables the regular
start counter or stop counter commands and puts the C/T into counter mode under the
control of the received data stream. Each time a received character is transferred from the
shift register to the Rx FIFO, the C/T is stopped after one C/T clock, reloaded with the
value in CTU and CTL and then restarted on the next C/T clock. If the C/T is allowed to
end the count before a new character has been received, the counter ready bit, ISR[3], will
be set. If IMR[3] is set, this will generate an interrupt. Receiving a character after the C/T
has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the set
time-out mode on command, CRx = 0xA, will also clear the counter ready bit and stop the
counter until the next character is received.
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SC28L92
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
6.3.9 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be
a false interrupt, i.e., an interrupt without a cause. This may result when a time-out
interrupt occurs and then, before the interrupt is serviced, another character is received,
i.e., the data stream has started again. (The interrupt latency is longer than the pause in
the data stream.) In this case, when a new character has been receiver, the counter/timer
will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the
interrupt service begins for the previously seen interrupt, a read of the ISR will show the
counter ready bit not set. If nothing else is interrupting, this read of the ISR will return a
0x00 character.
6.3.10 Multi-drop mode (9-bit or wake-up)
The DUART is equipped with a wake-up mode for multi-drop applications. This mode is
selected by programming bits MR1A[4:3] or MR1B[4:3] to 11 for channels A and B,
respectively. In this mode of operation, a master station transmits an address character
followed by data characters for the addressed slave station. The slave stations, with
receivers that are normally disabled, examine the received data stream and wake-up the
CPU (by setting RxRDY) only upon receipt of an address character. The CPU compares
the received address to its station address and enables the receiver if it wishes to receive
the subsequent data characters. Upon receipt of another address character, the CPU may
disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed number of data bits, and
Address/Data (A/D) bit, and the programmed number of stop bits. The polarity of the
transmitted A/D bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which identifies the
corresponding data bits as data while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit
position, which identifies the corresponding data bits as an address. The CPU should
program the mode register prior to loading the corresponding data bits into the Tx FIFO.
In this mode, the receiver continuously looks at the received data stream, whether it is
enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into
the Rx FIFO if the received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all received characters are
transferred to the CPU via the Rx FIFO. In either case, the data bits are loaded into the
data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity
error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally
whether or not the receive is enabled.
7. Programming
7.1 Register overview
The operation of the DUART is programmed by writing control words into the appropriate
registers. Operational feedback is provided via status registers which can be read by the
CPU. The addressing of the registers is described in Table 4.
The contents of certain control registers are initialized to zero on RESET. Care should be
exercised if the contents of a register are changed during operation, since certain
changes may cause operational problems.
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SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
For example, changing the number of bits per character while the transmitter is active may
cause the transmission of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are
not enabled, and certain changes to the ACR should only be made while the C/T is
stopped.
Each channel has three mode registers (MR0, MR1 and MR2) which control the basic
configuration of the channel. Access to these registers is controlled by independent MR
address pointers. These pointers are set to 0x0 or 0x1 by MR control commands in the
command register Miscellaneous Commands. Each time the MR registers are accessed
the MR pointer increments, stopping at MR2. It remains pointing to MR2 until set to 0x0 or
0x1 via the miscellaneous commands of the command register. The pointer is set to 0x1
on reset for compatibility with previous Philips Semiconductors UART software.
Mode, command, clock select, and status registers are duplicated for each channel to
provide total independent operation and control. Refer to Section 7.2 for register bit
overview. The reserved registers at addresses 0x2 and 0xA should never be read during
normal operation since they are reserved for internal diagnostics.
Table 4.
SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)[1]
Binary address
Read operation (RDN = 0 and CEN = 0)
Write operation (WRN = 0 and CEN = 0)
0
0
0
0
Mode Register A (MR0A, MR1A, MR2A)
Mode Register A (MR0A, MR1A, MR2A)
0
0
0
1
Status Register A (SRA)
Clock Select Register A (CSRA)
0
0
1
0
reserved
Command Register A (CRA)
0
0
1
1
Rx Holding Register A (RxFIFOA)
Tx Holding Register A (TxFIFOA)
0
1
0
0
Input Port Change Register (IPCR)
Auxiliary Control Register (ACR)
0
1
0
1
Interrupt Status Register (ISR)
Interrupt Mask Register (IMR)
0
1
1
0
Counter/Timer Upper (CTU)
C/T Upper Preset Register (CTPU)
0
1
1
1
Counter/Timer Lower (CTL)
C/T Lower Preset Register (CTPL)
1
0
0
0
Mode Register B (MR0B, MR1B, MR2B)
Mode Register B (MR0B, MR1B, MR2B)
1
0
0
1
Status Register B (SRB)
Clock Select Register B (CSRB)
1
0
1
0
reserved
Command Register B (CRB)
1
0
1
1
Rx Holding Register B (RxFIFOB)
Tx Holding Register B (TxFIFOB)
1
1
0
0
Interrupt vector (68xxx mode)
Interrupt vector (68xxx mode)
1
1
0
0
Miscellaneous register (Intel mode), IVR
Motorola mode
Miscellaneous register (Intel mode), IVR
Motorola mode
1
1
0
1
Input Port Register (IPR)
Output Port Configuration Register (OPCR)
1
1
1
0
start counter command
Set Output Port Bits Command (SOPR)
1
1
1
1
stop counter command
Reset output Port Bits Command (ROPR)
[1]
The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter
enable bits).
Table 5.
Registers for channels A and B
Register name
Channel A register
Channel B register
Access
Mode Register
MRnA
MRnB
R/W
Status Register
SRA
SRB
R only
Clock Select
CSRA
CSRB
W only
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SC28L92
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 5.
Registers for channels A and B …continued
Register name
Channel A register
Channel B register
Access
Command Register
CRA
CRB
W only
Receiver FIFO
RxFIFOA
RxFIFOB
R only
Transmitter FIFO
TxFIFOA
TxFIFOB
W only
Mnemonic
Access
Table 6.
Registers supporting both channels
Register name
Input Port Change Register
IPCR
R
Auxiliary Control Register
ACR
W
Interrupt Status Register
ISR
R
Interrupt Mask Register
IMR
W
Counter/Timer Upper value
CTU
R
Counter/Timer Lower value
CTL
R
Counter/Timer Preset Upper
CTPU
W
Counter/Timer Preset Lower
CTPL
W
Input Port Register
IPR
R
Output Configuration Register
OPCR
W
Set Output Port
SOPR
W
Reset Output Port
ROPR
W
Interrupt vector or GP register
IVR/GP
R/W
7.2 Condensed register bit formats
Table 7.
MR0 - Mode Register 0
7
6
RxWATCHDOG
RxINT[2]
Table 8.
5
4
TxINT[1:0]
3
2
1
0
FIFOSIZE
BAUDRATE
EXTENDED II
TEST2
BAUDRATE
EXTENDED I
3
2
1
0
MR1 - Mode Register 1
7
6
5
RxRTS
control
RxINT[1]
ERRORMODE
Table 9.
4
PARITYMODE
PARITYTYPE
bits per character
MR2 - Mode Register 2
7
6
channel mode
Table 10.
5
4
RTSN
Control Tx
CTSN
Enable Tx
3
2
1
0
1
0
stop bit length
CSR - Clock Select Register
7
6
5
4
3
receiver clock select code
transmitter clock select code
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SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 11.
CR - Command Register
7
6
5
4
channel command code
Table 12.
3
2
1
0
disable Tx
enable Tx
disable Rx
enable Rx
SR - channel Status Register
7
6
5
4
3
2
1
0
received
break
framing error
parity error
overrun error
TxEMT
TxRDY
RxFULL
RxRDY
3
2
1
0
RxRDYA
TxRDYA
1
0
RxRDYA
FFULLA
TxRDYA
2
1
0
2
1
0
Table 13.
IMR - Interrupt Mask Register (enables interrupts)
7
6
5
4
change input
port
change break
B
RxRDYB
TxRDTYB
Table 14.
ISR - Interrupt Status Register
7
6
5
4
input port
change
change break
B
RxRDYB
FFULLB
TxRDTYB
Table 15.
counter ready change break
A
3
2
counter ready change break
A
CTPU - Counter/Timer Preset Register, Upper
7
6
5
4
3
8 MSB of the BRG timer divisor
Table 16.
CTPL - Counter/Timer Preset Register, Lower
7
6
5
4
3
8 LSB of the BRG timer divisor
Table 17.
ACR - Auxiliary Control Register and change of state control
7
6
BRG set
select
Table 18.
5
4
counter/timer mode and clock source
select (see Table 54 on page 44)
3
2
1
0
enable IP3
COS interrupt
enable IP2
COS interrupt
enable IP1
COS interrupt
enable IP0
COS interrupt
IPCR - Input Port Change Register
7
6
5
4
3
2
1
0
delta IP3
delta IP2
delta IP1
delta IP0
state of IP3
state of IP2
state of IP1
state of IP0
Table 19.
IPR - Input Port Register
7
6
5
4
3
2
1
0
state of IP7
state of IP6
state of IP5
state of IP4
state of IP3
state of IP2
state of IP1
state of IP0
Table 20.
SOPR - Set Output Port bits Register (SOPR)
7
6
5
4
3
2
1
0
set OP7
set OP6
set OP5
set OP4
set OP3
set OP2
set OP1
set OP0
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 21.
ROPR - Reset Output Port bits Register (ROPR)
7
6
5
4
3
2
1
0
reset OP7
reset OP6
reset OP5
reset OP4
reset OP3
reset OP2
reset OP1
reset OP0
Table 22. OPCR - Output Port Configuration Register
OP1 and OP0 are the RTSN output and are controlled by the MR register
7
6
5
4
3
2
1
0
configure
OP7
configure
OP6
configure
OP5
configure
OP4
configure
OP3
configure
OP3
configure
OP2
configure
OP2
7.3 Register descriptions
7.3.1 Mode registers
7.3.1.1
Mode Register 0 channel A (MR0A)
Table 23. MR0A - Mode Register 0 channel A (address 0x0) bit allocation
MR0 is accessed by setting the MR pointer to logic 0 via the command register command B.
7
6
RxWATCHDOG
RxINT[2]
Table 24.
5
4
TxINT[1:0]
3
2
1
0
FIFOSIZE
BAUDRATE
EXTENDED II
TEST2
BAUDRATE
EXTENDED I
MR0A - Mode Register 0 channel A (address 0x0) bit description
Bit
Symbol
Description
7
RxWATCHDOG
This bit controls the receiver watchdog timer.
0 = disable
1 = enable
When enabled, the watchdog timer will generate a receiver interrupt if
the receiver FIFO has not been accessed within 64 bit times of the
receiver 1× clock. The watchdog timer is used to alert the control
processor that data is in the Rx FIFO that has not been read. This
situation will occur when the byte count of the last part of a message
is not large enough to generate an interrupt.
The watchdog timer presents itself as a receiver interrupt with the
RxRDY bit set in SR and ISR.
6
RxINT[2]
Bit 2 of receiver FIFO interrupt level. This bit along with bit 6 of MR1
sets the fill level of the FIFO that generates the receiver interrupt.
Note that this control is split between MR0 and MR1. This is for
backward compatibility to the SC26C92 and SCC2681.
For the receiver these bits control the number of FIFO positions filled
when the receiver will attempt to interrupt. After the reset the receiver
FIFO is empty. The default setting of these bits cause the receiver to
attempt to interrupt when it has one or more bytes in it; see Table 25.
5 and 4
TxINT[1:0]
Transmitter interrupt fill level. For the transmitter these bits control the
number of FIFO positions empty when the receiver will attempt to
interrupt; see Table 26. After the reset the transmit FIFO has 8 bytes
empty. It will then attempt to interrupt as soon as the transmitter is
enabled. The default setting (TxINT[1:0] = 00) condition the
transmitter to attempt to interrupt only when it is completely empty. As
soon as one byte is loaded, it is no longer empty and hence will
withdraw its interrupt request.
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 24.
MR0A - Mode Register 0 channel A (address 0x0) bit description …continued
Bit
Symbol
Description
3
FIFOSIZE
FIFO size for channel A and channel B. Selects the FIFO depth at
8-byte or 16-byte.
0 = 8 bytes
1 = 16 bytes
2
BAUDRATE
EXTENDED I
Bits MR0[2:0] are used to select one of the six baud rate groups. See
Table 35 for the group organization.
1
TEST2
000 = Normal mode
0
BAUDRATE
EXTENDED II
001 = Extended mode I
100 = Extended mode II
Other combinations of MR0[2:0] should not be used.
Table 25.
Receiver FIFO interrupt fill level[1]
RxINT[2:1] (bits MR0[6] and MR1[6])
Interrupt condition
FIFOSIZE = 0 (8 bytes)
00
1 or more bytes in FIFO (RxRDY)
01
3 or more bytes in FIFO
10
6 or more bytes in FIFO
11
8 bytes in FIFO (RxFULL)
FIFOSIZE = 1 (16 bytes)
00
1 or more bytes in FIFO (RxRDY)
01
8 or more bytes in FIFO
10
12 or more bytes in FIFO
11
16 bytes in FIFO (RxFULL)
[1]
Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes
effect only after a read or a write to the FIFO.
Table 26.
Transmitter FIFO interrupt fill level[1]
TxINT[1:0] (bits MR0[5:4])
Interrupt condition
FIFOSIZE = 0 (8 bytes)
00
8 bytes empty (TxEMPTY)
01
4 or more bytes empty
10
6 or more bytes empty
11
1 or more bytes empty (TxRDY)
FIFOSIZE = 1 (16 bytes)
00
16 bytes empty (TxEMPTY)
01
8 or more bytes empty
10
12 or more bytes empty
11
1 or more bytes empty (TxRDY)
[1]
Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes
effect only after a read or a write to the FIFO.
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7.3.1.2
Mode Register 1 channel A (MR1A)
Table 27. MR1A - Mode Register 1 channel A (address 0x0) bit allocation
MR1A is accessed when the channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer
command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A[1].
[1]
7
6
5
RxRTS
control
RxINT[1]
ERRORMODE
4
3
PARITYMODE
2
PARITYTYPE
1
0
bits per character
In block error mode, block error conditions must be cleared by using the error reset command (command 0x4) or a receiver reset.
Table 28.
MR1A - Mode Register 1 channel A (address 0x0) bit description
Bit
Symbol
Description
7
RxRTS
Channel A receiver request to send control (flow control). This bit
controls the deactivation of the RTSAN output (OP0) by the receiver.
This output is normally asserted by setting OPR[0] and negated by
resetting OPR[0]. Proper automatic operation of flow control requires
OPR[0] (channel A) or OPR[1] (channel B) to be set to logic 1.
0 = No RTS control
1 = RTS control
RxRTS = 1 causes RTSAN to be negated (OP0 is driven to a
logic 1 [VCC]) upon receipt of a valid start bit if the channel A FIFO is
full. This is the beginning of the reception of the 9th byte. If the FIFO is
not read before the start of the 10th or 17th byte, an overrun condition
will occur and the 10th or 17th or 17th byte will be lost. However, the
bit in OPR[0] is not reset and RTSAN will be asserted again when an
empty FIFO position is available. This feature can be used for flow
control to prevent overrun in the receiver by using the RTSAN output
signal to control the CTSN input of the transmitting device.
6
RxINT[1]
Bit 1 of the receiver interrupt control. See description of RxINT[2] in
Table 25 and Table 26.
5
ERRORMODE
Channel A error mode select.
0 = character
1 = block
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break) for channel A. In the character mode, status
is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logic OR) of the
status for all characters coming to the top of the FIFO since the last
reset error command for channel A was issued.
4 and 3
PARITYMODE
Channel A parity mode select
00 = with parity
01 = force parity
10 = no parity
11 = multi-drop special mode
If with parity or force parity is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects channel A to operate in the
special multi-drop mode described in Section 6.3.10 “Multi-drop mode
(9-bit or wake-up)”.
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 28.
MR1A - Mode Register 1 channel A (address 0x0) bit description …continued
Bit
Symbol
Description
2
PARITYTYPE
Channel A parity type select
0 = even
1 = odd
This bit selects the parity type (odd or even) if the with parity mode is
programmed by MR1A[4:3], and the polarity of the forced parity bit if
the force parity mode is programmed. It has no effect if the no parity
mode is programmed. In the special multi-drop mode it selects the
polarity of the A/D bit.
1:0
-
Channel A bits per character select.
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
7.3.1.3
Mode Register 2 channel A (MR2A)
Table 29. MR2A - Mode Register 2 channel A (address 0x0) bit allocation
MR2A is accessed when the channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to
MR2A do not change the pointer.
7
6
channel mode
5
4
RTSN
Control Tx
CTSN
Enable Tx
Table 30.
3
2
1
0
stop bit length
MR2A - Mode Register 2 channel A (address 0x0) bit description
Bit
Symbol
Description
7 and 6
-
Channel A mode select. Each channel of the DUART can operate in one of
the following four modes:
00 = Normal mode (default)
01 = Automatic echo mode
10 = Local loopback mode
11 = Remote loopback mode
Table 31 gives a description of the channel modes
The user must exercise care when switching into and out of the various
modes. The selected mode will be activated immediately upon mode
selection, even if this occurs in the middle of a received or transmitted
character. Likewise, if a mode is deselected the device will switch out of the
mode immediately. An exception to this is switching out of auto echo or
remote loopback modes: if the deselection occurs just after the receiver
has sampled the stop bit (indicated in auto echo by assertion of RxRDY),
and the transmitter is enabled, the transmitter will remain in auto echo
mode until the entire stop has been retransmitted.
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 30.
MR2A - Mode Register 2 channel A (address 0x0) bit description …continued
Bit
Symbol
Description
5
-
Channel A transmitter Request To Send (RTS) control.
0 = No RTS control
1 = RTS control
This bit controls the deactivation of the RTSAN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset
automatically one bit time after the characters in the channel A transmit
shift register and in the Tx FIFO, if any, are completely transmitted
including the programmed number of stop bits, if the transmitter is not
enabled
This feature can be used to automatically terminate the transmission of a
message as follows (line turnaround):
1. Program auto-reset mode: MR2A[5] = 1
2. Enable transmitter
3. Assert RTSAN: OPR[0] = 1
4. Send message
5. Disable transmitter after the last character is loaded into the channel A
Tx FIFO
6. The last character will be transmitted and OPR[0] will be reset one bit
time after the last stop bit, causing RTSAN to be negated
4
-
Channel A transmitter Clear To Send (CTS) control.
0 = Input CTSAN(IP0) has no effect on the transmitter
1 = CTS control enabled
If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time
it is ready to send a character. If IP0 is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes LOW.
Changes in CTSAN while a character is being transmitted do not affect the
transmission of that character.
3 to 0
-
Stop bit length select. This field programs the length of the stop bit
appended to the transmitted character. Stop bit lengths of 9⁄16 to 1 and
1 − 9⁄16 to 2 bits, in increments of 1⁄16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1 − 1⁄16 to 2
stop bits can be programmed in increments of 1⁄16 bit. In all cases, the
receiver only checks for a mark condition at the center of the stop bit
position (one half-bit time after the last data bit, or after the parity bit if
enabled is sampled). Refer to Table 32 for the values.
If an external 1× clock is used for the transmitter:
MR2A[3] = 0 selects one stop bit
MR2A[3] = 1 selects two stop bits
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Table 31.
DUART mode description
Mode
Description
Normal
The transmitter and receiver operating independently.
Automatic
echo
Places the channel in the automatic echo mode, which automatically retransmits the
received data. The following conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. The receiver must be enabled, but the transmitter need not be enabled
4. The channel A TxRDY and TxEMT status bits are inactive
5. The received parity is checked, but is not regenerated for transmission, i.e.
transmitted parity bit is as received
6. Character framing is checked, but the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
8. CPU to receiver communication continues normally, but the CPU to transmitter
link is disabled
Local
loopback
Selects local loopback diagnostic mode. In this mode:
1. The transmitter output is internally connected to the receiver input
2. The transmit clock is used for the receiver
3. The TxDA output is held HIGH
4. The RxDA input is ignored
5. The transmitter must be enabled, but the receiver need not be enabled
6. CPU to transmitter and receiver communications continue normally
Remote
loopback
Selects remote loopback diagnostic mode. In this mode:
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. Received data is not sent to the local CPU, and the error status conditions are
inactive
4. The received parity is not checked and is not regenerated for transmission, i.e.,
transmitted parity is as received
5. The receiver must be enabled
6. Character framing is not checked, and the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
Table 32.
Stop bit length
MR2A[3:0] (hexadecimal)
Stop bit length[1]
0
0.563
1
0.625
2
0.688
3
0.750
4
0.813
5
0.875
6
0.938
7
1.000
8
1.563
9
1.653
A
1.688
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Table 32.
MR2A[3:0] (hexadecimal)
Stop bit length[1]
B
1.750
C
1.813
D
1.875
E
1.938
F
2.000
[1]
7.3.1.4
Stop bit length …continued
Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character
Mode Register 0 channel B (MR0B)
MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The
pointer is set to MR0 by RESET or by a set pointer command applied via CRB. After
reading or writing MR0B, the pointer will point to MR1B.
The bit definitions for this register are identical to MR0A, except the FIFO size bit and that
all control actions apply to the channel B receiver, transmitter, the corresponding inputs
and outputs. MR0B[2:0] are reserved.
7.3.1.5
Mode Register 1 channel B (MR1B)
MR1B (address 0x8) is accessed when the channel B MR pointer points to MR1. The
pointer is set to MR1 by RESET or by a set pointer command applied via CRB. After
reading or writing MR1B, the pointer will point to MR2B.
The bit definitions for this register are identical to MR1A, except that all control actions
apply to the channel B receiver and transmitter and the corresponding inputs and outputs.
7.3.1.6
Mode Register 2 channel B (MR2B)
MR2B (address 0x8) is accessed when the channel B MR pointer points to MR2, which
occurs after any access to MR1B. Accesses to MR2B do not change the pointer.
The bit definitions for mode register are identical to the bit definitions for MR2A, except
that all control actions apply to the channel B receiver and transmitter and the
corresponding inputs and outputs.
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7.3.2 Clock select registers
Table 33.
CSRA - Clock select register channel A (address 0x1) and
CSRB - Clock select register channel B (address 0x9) bit allocation
7
6
5
4
3
receiver clock select code
7.3.2.1
2
1
0
transmitter clock select code
Clock Select Register channel A (CSRA)
Table 34.
CSRA - Clock select register channel A (address 0x1) bit description
Bit
Symbol
Description
7 to 4
-
Receiver clock select. The baud rate clock for the channel A receiver is as
shown in Table 35, except as follows:
1110 = IP4 - 16×
1111 = IP4 - 1×
The receiver clock is always a 16× clock except for CSRA[7:4] = 1111
3 to 0
-
Transmitter clock select. The baud rate clock for the channel A transmitter is
as shown in Table 35, except as follows:
1110 = IP3 - 16×
1111 = IP3 - 1×
The transmitter clock is always a 16× clock except for CSRA[3:0] = 1111
Table 35. Baud rate (based on a 3.6864 MHz crystal clock)
See Table 36 for bit rate characteristics.
CSR[7:4]
CSR[3:0]
MR0[0] = 0 (Normal mode)
MR0[0] = 1 (Extended mode I)
MR0[2] = 1 (Extended mode II)
ACR[7] = 0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
0000
50
75
300
450
4,800
7,200
0001
110
110
110
110
880
880
0010
134.5
134.5
134.5
134.5
1,076
1,076
0011
200
150
1200
900
19.200
14.400
0100
300
300
1800
1800
28.800
28.800
0101
600
600
3600
3600
57.600
57.600
0110
1,200
1,200
7200
7,200
115,200
115,200
0111
1,050
2,000
1,050
2,000
1,050
2,000
1000
2,400
2,400
14,400
14,400
57,600
57,600
1001
4,800
4,800
28,800
28,800
4,800
4,800
1010
7,200
1,800
7,200
1,800
57,600
14,400
1011
9,600
9,600
57,600
57,600
9,600
9,600
1100
38,400
19,200
230,400
115,200
38,400
19,200
1101
Timer
Timer
Timer
Timer
Timer
Timer
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Table 36. Bit rate generator characteristics[1]
Crystal or clock = 3.6864 MHz.
Normal rate (baud)
Actual 16× clock (kHz)
Error (%)
50
0.8
0
75
1.2
0
110
1.759
−0.069
134.5
2.153
0.059
150
2.4
0
200
3.2
0
300
4.8
0
600
9.6
0
1050
16.756
−0.260
1200
19.2
0
1800
28.8
0
2000
32.056
0.175
2400
38.4
0
4800
76.8
0
7200
115.2
0
9600
153.6
0
19200
307.2
0
38400
614.4
0
[1]
7.3.2.2
Duty cycle of 16× clock is 50 % ± 1 %.
Clock Select Register channel B (CSRB)
Table 37.
CSRB - Clock select register channel B (address 0x9) bit description
Bit
Symbol
Description
7 to 4
-
Receiver clock select. The baud rate clock for the channel B receiver is as
shown in Table 35, except as follows:
1110 = IP6 - 16×
1111 = IP6 - 1×
The receiver clock is always a 16× clock except for CSRB[7:4] = 1111
3 to 0
-
Transmitter clock select. The baud rate clock for the channel A transmitter is
as shown in Table 35, except as follows:
1110 = IP5 - 16×
1111 = IP5 - 1×
The transmitter clock is always a 16× clock except for CSRB[3:0] = 1111
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7.3.3 Command registers
Table 38.
7
CRA - Command register channel A (address 0x2) and
CRB - Command register channel B (address 0xA) bit allocation
6
5
4
channel command code
7.3.3.1
3
2
1
0
disable Tx
enable Tx
disable Rx
enable Rx
Command Register channel A (CRA)
CRA is a register used to supply commands to channel A. Multiple commands can be
specified in a single write to CRA as long as the commands are non-conflicting, e.g., the
enable transmitter and reset transmitter commands cannot be specified in a single
command word.
Table 39.
CRA - Command register channel A (address 0x2) bit description
Bit
Symbol
Description
7 to 4
-
Miscellaneous commands. Execution of the commands in the upper four bits
of this register must be separated by 3 X1 clock edges. Other reads or writes
(including writes to the lower four bits) may be inserted to achieve this
separation. A description of miscellaneous commands is given in Table 40.
3
-
Disable channel A transmitter. This command terminates transmitter operation
and reset the TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the Tx FIFO when the transmitter is disabled,
the transmission of the character(s) is completed before assuming the inactive
state.
2
-
Enable channel A transmitter. Enables operation of the channel A transmitter.
The TxRDY and TxEMT status bits will be asserted if the transmitter is idle.
1
-
Disable channel A receiver. This command terminates operation of the
receiver immediately-a character being received will be lost. The command
has no effect on the receiver status bits or any other control registers. If the
special multi-drop mode is programmed, the receiver operates even if it is
disabled. See Section 6.3.10.
0
-
Enable channel A receiver. Enables operation of the channel A receiver. If not
in the special wake-up mode, this also forces the receiver into the search for
start-bit state.
Table 40.
Miscellaneous commands
Command
Description
0000
No command.
0001
Reset MR pointer. Causes the channel A MR pointer to point to MR1.
0010
Reset receiver. Resets the channel A receiver as if a hardware reset had been
applied. The receiver is disabled and the FIFO is flushed.
0011
Reset transmitter. Resets the channel A transmitter as if a hardware reset had
been applied.
0100
Reset error status. Clears the channel A received break, parity error, and overrun
error bits in the status register (SRA[7:4]). Used in character mode to clear OE
status (although RB, PE and FE bits will also be cleared) and in block mode to clear
all error status after a block of data has been received.
0101
Reset channel A break change interrupt. Causes the channel A break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero.
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Table 40.
7.3.3.2
Miscellaneous commands …continued
Command
Description
0110
Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the
start of the break condition will be delayed up to two bit times. If the transmitter is
active the break begins when transmission of the character is completed. If a
character is in the Tx FIFO, the start of the break will be delayed until that
character, or any other loaded subsequently are transmitted. The transmitter must
be enabled for this command to be accepted.
0111
Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will
remain HIGH for one bit time before the next character, if any, is transmitted.
1000
Assert RTSN. Causes the RTSN output to be asserted (LOW).
1001
Negate RTSN. Causes the RTSN output to be negated (HIGH).
1010
Set time-out mode on. The receiver in this channel will restart the C/T as each
receive character is transferred from the shift register to the Rx FIFO. The C/T is
placed in the counter mode, the start counter or stop counter commands are
disabled, the counter is stopped, and the counter ready bit, ISR[3], is reset. (see
also watchdog timer description in the receiver Section 6.3.7.)
1011
Set MR pointer to 0x0.
1100
Disable time-out mode. This command returns control of the C/T to the regular start
counter or stop counter commands. It does not stop the counter, or clear any
pending interrupts. After disabling the time-out mode, a stop counter command
should be issued to force a reset of the ISR[3] bit.
1101
Not used.
1110
Power-down mode on. In this mode, the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands other
than disable Power-down mode (1111) requires a X1/CLK. While in the
Power-down mode, do not issue any commands to the CR except the disable
Power-down mode command. The contents of all registers will be saved while in
this mode. It is recommended that the transmitter and receiver be disabled prior to
placing the DUART into Power-down mode. This command is in CRA only.
1111
Disable Power-down mode. This command restarts the oscillator. After invoking this
command, wait for the oscillator to start up before writing further commands to the
CR. This command is in CRA only. For maximum power reduction input pins should
be at VSS or VDD.
Command Register channel B (CRB)
CRB is a register used to supply commands to channel B. Multiple commands can be
specified in a single write to CRB as long as the commands are non-conflicting, e.g., the
enable transmitter and reset transmitter commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions for CRA, with the
exception of miscellaneous commands 0xE and 0xF which are used for Power-down
mode. These two commands are not used in CRB. All other control actions that apply to
CRA also apply to CRB.
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7.3.4 Status registers
7.3.4.1
Status Register channel A (SRA)
Table 41.
SRA - Status register channel A (address 0x1) bit allocation
7
6
5
4
3
2
1
0
received
break[1]
framing
error[1]
parity
error[1]
overrun
error
TxEMTA
TxRDYA
RxFULLA
RxRDYA
[1]
These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
Table 42.
SRA - Status register channel A (address 0x1) bit description
Bit
Symbol
Description
7
-
Channel A received break.
0 = no
1 = yes
This bit indicates that an all zero character of the programmed length has been
received without a stop bit. Only a single FIFO position is occupied when a
break is received: further entries to the FIFO are inhibited until the RxDA line
returns to the marking state for at least one-half a bit time two successive
edges of the internal or external 1× clock. This will usually require a HIGH
time of one X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
When this bit is set, the channel A change in break bit in the ISR (ISR[2]) is set.
ISR[2] is also set when the end of the break condition, as defined above, is
detected.
The break detect circuitry can detect breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until at least the end of the next character time in order for it to be
detected.
This bit is reset by command 0x4 (0100) written to the command register or by
receiver reset.
6
-
Channel A framing error.
0 = no
1 = yes
This bit, when set, indicates that a stop bit was not detected (not a logic 1)
when the corresponding data character in the FIFO was received. The stop bit
check is made in the middle of the first stop bit position.
5
-
Channel A parity error.
0 = no
1 = yes
This bit is set when the with parity or force parity mode is programmed and the
corresponding character in the FIFO was received with incorrect parity.
In the special multi-drop mode the parity error bit stores the receive A/D
(Address/Data) bit.
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Table 42.
SRA - Status register channel A (address 0x1) bit description …continued
Bit
Symbol
Description
4
-
Channel A overrun error.
0 = no
1 = yes
This bit, when set, indicates that one or more characters in the received data
stream have been lost. It is set upon receipt of a new character when the FIFO
is full and a character is already in the receive shift register waiting for an empty
FIFO position. When this occurs, the character in the receive shift register (and
its break detect, parity error and framing error status, if any) is lost.
This bit is cleared by a reset error status command.
3
TxEMTA
Channel A transmitter empty.
0 = no
1 = yes
This bit will be set when the transmitter under runs, i.e., both the TxEMT and
TxRDY bits are set. This bit and TxRDY are set when the transmitter is first
enabled and at any time it is re-enabled after either (a) reset, or (b) the
transmitter has assumed the disabled state. It is always set after transmission
of the last stop bit of a character if no character is in the Tx Holding Register
(TxFIFOA) awaiting transmission.
It is reset when the Tx Holding Register (TxFIFOA) is loaded by the CPU, a
pending transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the under run condition.
2
TxRDYA
Channel A transmitter ready.
0 = no
1 = yes
This bit, when set, indicates that the transmit FIFO is not full and ready to be
loaded with another character. This bit is cleared when the transmit FIFO is
loaded by the CPU and there are (after this load) no more empty locations in
the FIFO. It is set when a character is transferred to the transmit shift register.
TxRDYA is reset when the transmitter is disabled and is set when the
transmitter is first enabled. Characters loaded to the Tx FIFO while this bit is
logic 0 will be lost. This bit has different meaning from ISR[0].
1
FFULLA
Channel A FIFO full.
0 = no
1 = yes
This bit is set when a character is transferred from the receive shift register to
the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight
(or 16) FIFO positions are occupied. It is reset when the CPU reads the receive
FIFO. If a character is waiting in the receive shift register because the FIFO is
full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit
has different meaning from ISR1 when MR1[6] is programmed to a logic 1
0
RxRDYA
Channel A receiver ready.
0 = no
1 = yes
This bit indicates that a character has been received and is waiting in the FIFO
to be read by the CPU. It is set when the character is transferred from the
receive shift register to the FIFO and reset when the CPU reads the receive
FIFO, only if (after this read) there are no more characters in the FIFO - the Rx
FIFO becomes empty.
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7.3.4.2
Status Register channel B (SRB)
Table 43.
SRB - Status register channel B (address 0x9) bit allocation
7
6
5
4
3
2
1
0
received
break[1]
framing
error[1]
parity
error[1]
overrun
error
TxEMTB
TxRDYB
RxFULLB
RxRDYB
[1]
These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
The bit definitions for this register are identical to the bit definitions for SRA, except that all
status applies to the channel B receiver and transmitter and the corresponding inputs and
outputs.
7.3.5 Output Configuration Control Register (OPCR)
This register controls the signal presented by the OP[7:2] pins. The signal presented by
the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default
condition of the OP pins is to drive the complement of the data in the OPR[7:0] register.
When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain
configuration. Otherwise, they drive strong logic 0 or logic 1 levels.
Table 44.
OPCR - Output configuration control register (address 0xD) bit allocation
7
6
5
4
configure
OP7
configure
OP6
configure
OP5
configure
OP4
Table 45.
3
2
configure OP3
1
0
configure OP2
OPCR - Output configuration control register (address 0xD) bit description
Bit
Symbol
Description
7
-
OP7 output select
0 = The complement of OPR[7]
1 = The channel B transmitter interrupt output which is the complement of
ISR[4]. When in this mode OP7 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
6
-
OP6 output select
0 = The complement of OPR[6]
1 = The channel A transmitter interrupt output which is the complement of
ISR[0]. When in this mode OP6 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
5
-
OP5 output select
0 = The complement of OPR[5]
1 = The channel B receiver interrupt output which is the complement of
ISR[5]. When in this mode OP5 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
4
-
OP4 output select
0 = The complement of OPR[4]
1 = The channel A receiver interrupt output which is the complement of
ISR[1]. When in this mode OP4 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
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Table 45.
OPCR - Output configuration control register (address 0xD) bit description
Bit
Symbol
Description
3 and 2
-
OP3 output select
00 = The complement of OPR[3]
01 = The counter/timer output, in which case OP3 acts as an open-drain
output. In the timer mode, this output is a square wave at the programmed
frequency. In the counter mode, the output remains HIGH until terminal
count is reached, at which time it goes LOW. The output returns to the
HIGH state when the counter is stopped by a stop counter command. Note
that this output is not masked by the contents of the IMR.
10 = The 1× clock for the channel B transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1× clock is output.
11 = The 1× clock for the channel B receiver, which is the clock that
samples the received data. If data is not being received, a free running 1×
clock is output.
1 and 0
-
OP2 output select
00 = The complement of OPR[2]
01 = The 16× clock for the channel A transmitter. This is the clock selected
by CSRA[3:0], and will be a 1× clock if CSRA[3:0] = 1111.
10 = The 1× clock for the channel A transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1× clock is output.
11 = The 1× clock for the channel A receiver, which is the clock that
samples the received data. If data is not being received, a free running 1×
clock is output.
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7.3.6 Set Output Port bits Register (SOPR)
Ones in the byte written to this register will cause the corresponding bit positions in the
OPR to set to 1. Zeros have no effect. This allows software to set individual bits without
keeping a copy of the OPR bit configuration.
Table 46.
SOPR - Set output port bits register (address 0xE) bit allocation
7
6
5
4
3
2
1
0
set OP7
set OP6
set OP5
set OP4
set OP3
set OP2
set OP1
set OP0
Table 47.
SOPR - Set output port bits register (address 0xE) bit description
Bit
Symbol
Description
7
-
OPR 7
1 = set bit
0 = no change
6
-
OPR 6
1 = set bit
0 = no change
5
-
OPR 5
1 = set bit
0 = no change
4
-
OPR 4
1 = set bit
0 = no change
3
-
OPR 3
1 = set bit
0 = no change
2
-
OPR 2
1 = set bit
0 = no change
1
-
OPR 1
1 = set bit
0 = no change
0
-
OPR 0
1 = set bit
0 = no change
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7.3.7 Reset Output Port bits Register (ROPR)
Ones in the byte written to the ROPR will cause the corresponding bit positions in the
OPR to set to 0. Zeros have no effect. This allows software to reset individual bits without
keeping a copy of the OPR bit configuration.
Table 48.
ROPR - Reset output port bits register (address 0xF) bit allocation
7
6
5
4
3
2
1
0
reset OP7 reset OP6 reset OP5 reset OP4 reset OP3 reset OP2 reset OP1 reset OP0
Table 49.
ROPR - Reset output port bits register (address 0xF) bit description
Bit
Symbol
Description
7
-
OPR 7
1 = reset bit
0 = no change
6
-
OPR 6
1 = reset bit
0 = no change
5
-
OPR 5
1 = reset bit
0 = no change
4
-
OPR 4
1 = reset bit
0 = no change
3
-
OPR 3
1 = set bit
0 = no change
2
-
OPR 2
1 = reset bit
0 = no change
1
-
OPR 1
1 = reset bit
0 = no change
0
-
OPR 0
1 = reset bit
0 = no change
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.8 Output Port Register (OPR)
Table 50. OPR - Output port register (no address) bit allocation
The output pins (OP pins) drive the complement of the data in this register as controlled by SOPR
and ROPR.
7
6
5
4
3
2
1
0
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Table 51.
OPR - Output port register (no address) bit description
Bit
Symbol
Description
7
-
pin OP7
0 = pin HIGH
1 = pin LOW
6
-
pin OP6
0 = pin HIGH
1 = pin LOW
5
-
pin OP5
0 = pin HIGH
1 = pin LOW
4
-
pin OP4
0 = pin HIGH
1 = pin LOW
3
-
pin OP3
0 = pin HIGH
1 = pin LOW
2
-
pin OP2
0 = pin HIGH
1 = pin LOW
1
-
pin OP1
0 = pin HIGH
1 = pin LOW
0
-
pin OP0
0 = pin HIGH
1 = pin LOW
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.9 Auxiliary Control Register (ACR)
Table 52.
ACR - Auxiliary control register (address 0x4) bit allocation
7
BRG set
select
6
5
4
counter/timer mode and clock source select
Table 53.
3
2
1
0
enable IP3
enable IP2
enable IP1
enable IP0
COS interrupt COS interrupt COS interrupt COS interrupt
ACR - Auxiliary control register (address 0x4) bit description
Bit
Symbol
7
-
Description
Baud rate generator set select.
This bit selects one of two sets of baud rates to be generated by the BRG (see
Table 35).
The selected set of rates is available for use by the channel A and B receivers
and transmitters as described for CSRA in Table 34 and for CSRB in Table 37.
Baud rate generator characteristics are given in Table 36.
6 to 4
-
Counter/timer mode and clock source select.
This field selects the operating mode of the counter/timer and its clock source
as shown in Table 54.
3 to 0
-
IP3, IP2, IP1 and IP0 change-of-state interrupt enable.
0 = off
1 = enabled
This field selects which bits of the input port change register (IPCR) cause the
input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in
the enabled state the setting of the corresponding bit in the IPCR will also
result in the setting of ISR [7], which results in the generation of an interrupt
output if IMR [7] = 1. If a bit is in the off state, the setting of that bit in the IPCR
has no effect on ISR [7].
Table 54.
ACR[6:4] field definition[1]
ACR[6:4]
Mode
Clock source
000
counter
external (IP2)
001
counter
TxCA - 1× clock of channel A transmitter
010
counter
TxCB - 1× clock of channel B transmitter
011
counter
crystal or external clock (X1/CLK) divided by 16
100
timer
external (IP2)
101
timer
external (IP2) divided by 16
110
timer
crystal or external clock (X1/CLK)
111
timer
crystal or external clock (X1/CLK) divided by 16
[1]
The timer mode generates a square wave.
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7.3.10 Input Port Change Register (IPCR)
Table 55.
IPCR - Input port change register (address 0x4) bit allocation
7
6
5
4
3
2
1
0
delta IP3
delta IP2
delta IP1
delta IP0
state of
IP3
state of
IP2
state of
IP1
state of
IP0
Table 56.
IPCR - Input port change register (address 0x4) bit description
Bit
Symbol
Description
7 to 4
-
IP3, IP2, IP1 and IP0 change of state.
0 = no change
1 = change
These bits are set when a change of state, as defined in Section 6.2.9 “Input
port”, occurs at the respective input pins. They are cleared when the IPCR is
read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in
the interrupt status register. The setting of these bits can be programmed to
generate an interrupt to the CPU.
3 to 0
-
IP3, IP2, IP1 and IP0 state.
0 = LOW
1 = HIGH
These bits provide the current state of the respective inputs. The information is
unlatched and reflects the state of the input pins at the time the IPCR is read.
7.3.11 Interrupt Status Register (ISR)
This register provides the status of all potential interrupt sources. The contents of this
register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a logic 1
and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted
(LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no
effect on the INTRN output. Note that the IMR does not mask the reading of the ISR. The
true status will be provided regardless of the contents of the IMR. The contents of this
register are initialized to 0x0 when the DUART is reset.
Table 57.
ISR - Interrupt status register (address 0x5) bit allocation
7
6
5
4
3
2
1
0
change
input port
change
break B
RxRDYB
TxRDYB
counter
ready
change
break A
RxRDYA
TxRDYA
Table 58.
ISR - Interrupt status register (address 0x5) bit description
Bit
Symbol
Description
7
-
Input port change status.
0 = not active
1 = active
This bit is a logic 1 when a change of state has occurred at the IP0, IP1, IP2, or
IP3 inputs and that event has been selected to cause an interrupt by the
programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR.
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Table 58.
ISR - Interrupt status register (address 0x5) bit description …continued
Bit
Symbol
Description
6
-
Channel B change in break.
0 = not active
1 = active
This bit, when set, indicates that the channel B receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel B reset break change interrupt command.
5
RxRDYB
RxB interrupt.
0 = not active
1 = active
This bit indicates that the channel B receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
4
TxRDYB
TxB interrupt.
0 = not active
1 = active
This bit indicates that the channel B transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
3
-
Counter ready.
0 = not active
1 = active
In the counter mode, this bit is set when the counter reaches terminal count and
is reset when the counter is stopped by a stop counter command.
In the timer mode, this bit is set once each cycle of the generated square wave
(every other time that the counter/timer reaches zero count). The bit is reset by a
stop counter command. The command, however, does not stop the
counter/timer.
2
-
Channel A change in break.
0 = not active
1 = active
This bit, when set, indicates that the channel A receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel A reset break change interrupt command.
1
RxRDYA
RxA interrupt.
0 = not active
1 = active
This bit indicates that the channel A receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
0
TxRDYA
TxA interrupt.
0 = not active
1 = active
This bit indicates that the channel A transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
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SC28L92
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.12 Interrupt Mask Register (IMR)
The programming of this register selects which bits in the ISR causes an interrupt output.
If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the
INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the
programmable interrupt outputs OP3 to OP7 or the reading of the ISR.
Table 59.
IMR - Interrupt mask register (address 0x5) bit allocation
7
6
5
4
3
2
1
0
input port
change
change
break B
RxRDYB
FFULLB
TxRDYB
counter
ready
change
break A
RxRDYA
FFULLA
TxRDYA
Table 60.
IMR - Interrupt mask register (address 0x5) bit description
Bit
Symbol
Description
7
-
Input port change.
0 = not enabled
1 = enabled
6
-
Channel B change in break.
0 = not enabled
1 = enabled
5
RxRDYB
FFULLB
RxB interrupt.
0 = not enabled
1 = enabled
4
TxRDYB
TxB interrupt.
0 = not enabled
1 = enabled
3
-
Counter ready.
0 = not enabled
1 = enabled
2
-
Channel A change in break.
0 = not enabled
1 = enabled
1
RxRDYA
FFULLA
RxA interrupt.
0 = not enabled
1 = enabled
0
TxRDYA
TxA interrupt.
0 = not enabled
1 = enabled
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7.3.13 Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register
(GP; 80xxx mode)
This register stores the Interrupt Vector. It is initialized to 0x0F on hardware reset and is
usually changed from this value during initialization of the SC28L92. The contents of this
register will be placed on the data bus when IACKN is asserted LOW or a read of address
0xC is performed.
When not operating in the 68xxx mode, this register may be used as a general purpose
one byte storage register. A convenient use could be to store a shadow of the contents of
another SC28L92 register (IMR, for example).
Table 61.
IVR/GP - Interrupt vector register or general purpose register (address 0xC)
bit allocation
7
6
5
4
3
2
1
0
interrupt vector (68xxx mode) or one byte storage (80xxx mode)
7.3.14 Counter/timer registers
Table 62.
CTPU - Counter/Timer Preset Upper register (address 0x6) bit description
Bit
Symbol
Description
7:0
-
The upper eight (8) bits for the 16-bit counter/timer preset register
Table 63.
CTPL - Counter/Timer preset Lower register (address 0x7) bit description
Bit
Symbol
Description
7:0
-
The lower eight (8) bits for the 16-bit counter/timer preset register
The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be
used by the counter/timer in either the counter or timer modes of operation. The minimum
value which may be loaded into the CTPU/CTPL registers is 0x0002. Note that these
registers are write only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is twice the value (in
C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a
data clock. The formula for calculating the divisor n to load to the CTPU and CTPL for a
particular 1× data clock is shown in Equation 2.
counter/timer clock frequency
n = ----------------------------------------------------------------------------------2 × 16 × ( desired baud rate )
(2)
Often this division will result in a non-integer number; 26.3, for example. One can only
program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a
baud rate error of 0.3/26.3 which is 1.14 %; well within the ability asynchronous mode of
operation.
The C/T will not be running until it receives an initial start counter command (read at
address A3 to A0 = 1110). After this, while in timer mode, the C/T will run continuously.
Receipt of a start counter command (read with A3 to A0 = 1110) causes the counter to
terminate the current timing cycle and to begin a new cycle using the values in CTPU and
CTPL. If the value in CTPU and CTPL is changed, the current half-period will not be
affected, but subsequent half periods will be affected.
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The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is
reset by a stop counter command (read with A3 to A0 = 1111). The command however,
does not stop the C/T. The generated square wave is output on OP3 if it is programmed to
be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the
CPU is counted down to 0. Counting begins upon receipt of a start counter command.
Upon reaching terminal count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The
counter continues counting past the terminal count until stopped by the CPU. If OP3 is
programmed to be the output of the C/T, the output remains HIGH until terminal count is
reached, at which time it goes LOW. The output returns to the HIGH state and ISR[3] is
cleared when the counter is stopped by a stop counter command. The CPU may change
the values of CTPU and CTPL at any time, but the new count becomes effective only on
the next start counter commands. If new values have not been loaded, the previous count
values are preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU,
CTL) may be read by the CPU. It is recommended that the counter be stopped when
reading to prevent potential problems which may occur if a carry from the lower 8 bits to
the upper 8 bits occurs between the times that both halves of the counter are read.
However, note that a subsequent start counter command will cause the counter to begin a
new count cycle using the values in CTPU and CTPL.
When the C/T clock divided by 16 is selected, the maximum divisor becomes 1,048,575.
7.4 Output port notes
The output ports are controlled from four places: the OPCR register, the OPR register, the
MR registers and the command register (except the SCC2681 and SCC68681). The
OPCR register controls the source of the data for the output ports OP2 to OP7. The data
source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the
OPR is the source of the data for the output ports, the data at the ports is inverted from
that in the OPR register.
The content of the OPR register is controlled by the Set Output Port bits command and
the Reset Output Port bits command. These commands are at 0xE and 0xF, respectively.
When these commands are used, action takes place only at the bit locations where ones
exist. For example, a logic 1 in bit location 5 of the data word used with the Set Output
Port bits command will result in OPR5 being set to one. The OP5 would then be set to
logic 0 (VSS). Similarly, a logic 1 in bit position 5 of the data word associated with the
Reset Output Ports bits command would set OPR5 to logic 0 and, hence, the pin OP5 to a
logic 1 (VDD).
7.5 The CTS, RTS, CTS enable Tx signals
Clear To Send (CTS) is usually meant to be a signal to the transmitter meaning that it may
transmit data to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The
CTS signal is active LOW; thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is
usually meant to be a signal from the receiver indicating that the receiver is ready to
receive data. It is also active LOW and is, thus, called RTSAN for RxA and RTSBN for
RxB. RTSAN is on pin OP0 and RTSBN is on OP1. A receiver’s RTS output will usually be
connected to the CTS input of the associated transmitter. Therefore, one could say that
RTS and CTS are different ends of the same wire.
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SC28L92
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
MR2[4] is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1).
When this bit is set to one AND the CTS input is driven HIGH, the transmitter will stop
sending data at the end of the present character being serialized. It is usually the RTS
output of the receiver that will be connected to the transmitter’s CTS input. The receiver
will set RTS HIGH when the receiver FIFO is full AND the start bit of the 9th or 17th
character is sensed. Transmission then stops with 9 or 17 valid characters in the receiver.
When MR2[4] is set to one, CTSN must be at zero for the transmitter to operate. If MR2[4]
is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1[7] is
the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the
receiver, the meaning of that pin will be.
8. Limiting values
Table 64. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
[1][2]
Max
Unit
−40
+85
°C
Tamb
ambient temperature
Tstg
storage temperature
−65
+150
°C
VCC
voltage from VCC to GND
[3]
−0.5
+7.0
V
VS
voltage from any pin to GND
[3]
−0.5
VCC + 0.5 V
PD
package power dissipation
PLCC44
-
2.4
W
QFP44
-
1.78
W
HVQFN48
-
0.5
W
PLCC44
-
19
mW/°C
QFP44
-
14
mW/°C
HVQFN48
-
28
mW/°C
Pder
dissipation derating factor
above 25 °C
[1]
For operation at elevated temperatures, the device must be derated based on 150 °C maximum junction
temperature.
[2]
Parameters are valid over specified temperature range.
[3]
This product includes circuitry specifically designed for the protection of its internal devices from damaging
effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to
avoid applying any voltages larger than the rated maxima.
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
9. Static characteristics
Table 65. Static characteristics, 5 V operation[1]
VCC = 5 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
VIL
input LOW voltage
VIH
input HIGH voltage
output LOW voltage
VOL
Conditions
Min
Typ
Max
Unit
-
-
0.8
V
except pin X1/CLK
2.4
1.5
-
V
pin X1/CLK
0.8VCC
2.4
-
V
-
0.2
0.4
V
VCC − 0.5 -
-
V
IOL = 2.4 mA
except open-drain outputs;
IOH = −400 µA
[2]
VOH
output HIGH voltage
II(1XPD)
Power-down mode input current VI = 0 V to VCC
on pin X1/CLK
0.5
0.05
0.5
µA
IIL(X1)
operating input LOW current on
pin X1/CLK
−130
-
0
µA
IIH(X1)
operating input HIGH current on VI = VCC
pin X1/CLK
0
-
130
µA
II
input leakage current
VI = 0 V
VI = 0 V to VCC
all except input port pins
input port pins
[3]
−0.5
+0.05
+0.5
µA
−8
+0.05
+0.5
µA
IOZH
output off current HIGH, 3-state
data bus
VI = VCC
-
-
0.5
µA
IOZL
output off current LOW, 3-state
data bus
VI = 0 V
−0.5
-
-
µA
IODL
open-drain output LOW current
in off state
VI = 0 V
−0.5
-
-
µA
IODH
open-drain output HIGH current
in off state
VI = VCC
-
-
0.5
µA
ICC
power supply current
CMOS input levels
operating mode
-
7
25
mA
Power-down mode
-
≤1
5
µA
[4]
[1]
The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Typical values are at 25 °C, typical supply voltages, and typical processing parameters.
[2]
Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF,
constant current source = 2.6 mA.
[3]
Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS. Input port pins at
VCC source 0.0 µA.
[4]
All outputs are disconnected. Inputs are switching between CMOS levels of VCC − 0.2 V and VSS + 0.2 V.
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
001aae302
60
tDD
(ns)
(1)
40
(2)
20
12 pF 30 pF
100 pF
125 pF
230 pF
0
0
40
80
120
160
200
240
CL (pF)
(1) VCC = 3.3 V; Tamb = 25 °C
(2) VCC = 5.0 V; Tamb = 25 °C
Bus cycle times:
80xxx mode: tDD + tRWD = 70 ns for VCC = 5 V or 40 ns for VCC = 3.3 V + rise and fall time of control signals.
68xxx mode: tCSC + tDAT + 1 cycle of the X1 clock for = 70 ns for VCC = 5 V + rise and fall time of control signals.
Fig 9. Port timing as a function of capacitive loading at typical conditions
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3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 66. Static characteristics, 3.3 V operation[1]
VCC = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
VIL
input LOW voltage
-
0.65
0.2VCC V
VIH
input HIGH voltage
0.8VCC
1.7
-
V
VOL
output LOW voltage
-
0.2
0.4
V
IOL = 2.4 mA
Typ
Max
Unit
VCC − 0.5 VCC − 0.2 -
V
VI = 0 V to VCC
−0.5
+0.05
+0.5
µA
operating input LOW current
on pin X1/CLK
VI = 0 V
−80
-
0
µA
IIH(X1)
operating input HIGH current
on pin X1/CLK
VI = VCC
0
-
80
µA
II
input leakage current
VI = 0 V to VCC
VOH
output HIGH voltage
except open-drain outputs;
IOH = −400 µA
II(1XPD)
Power-down mode input
current on pin X1/CLK
IIL(X1)
[2]
all except input port pins
[3]
−0.5
+0.05
+0.5
µA
input port pins
[3]
−8
+0.5
+0.5
µA
-
-
0.5
µA
IOZH
output off current HIGH,
3-state data bus
VI = VCC
IOZL
output off current LOW, 3-state VI = 0 V
data bus
−0.5
-
-
µA
IODL
open-drain output LOW current VI = 0 V
in off state
−0.5
-
-
µA
IODH
open-drain output HIGH
current in off state
VI = VCC
-
-
0.5
µA
ICC
power supply current
CMOS input levels
operating mode
-
-
5
mA
Power-down mode
-
≤1
5.0
µA
[4]
[1]
The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Typical values are at 25 °C, typical supply voltages, and typical processing parameters.
[2]
Test conditions for outputs: CL = 125 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 125 pF,
constant current source = 2.6 mA.
[3]
Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when they are at VSS. Input port pins at VCC source
0.0 µA.
[4]
All outputs are disconnected. Inputs are switching between CMOS levels of VCC − 0.2 V and VSS + 0.2 V.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
53 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
10. Dynamic characteristics
Table 67. Dynamic characteristics, 5 V operation[1]
VCC = 5.0 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
100
18
-
ns
Reset timing (see Figure 10)
tRES
reset pulse width
Bus timing[2] (see Figure 11)
tAS
A0 to A3 set-up time to RDN, WRN LOW
10
6
-
ns
tAH
A0 to A3 hold time from RDN, WRN LOW
20
12
-
ns
tCS
CEN set-up time to RDN, WRN LOW
0
-
-
ns
tCH
CEN hold time from RDN, WRN LOW
0
-
-
ns
tRW
WRN, RDN pulse width (LOW time)
15
8
-
ns
tDD
data valid after RDN LOW
-
40
55
ns
tDA
RDN LOW to data bus active
0
-
-
ns
tDF
data bus floating after RDN or CEN HIGH
-
-
20
ns
0
-
-
ns
25
17
-
ns
0
−12
-
ns
17
10
-
ns
125 pF load; see Figure 9
for smaller loads
[3]
tDI
RDN or CEN HIGH to data bus invalid
tDS
data bus set-up time before WRN or CEN
HIGH (write cycle)
tDH
data hold time after WRN HIGH
tRWD
[4]
[2][4]
HIGH time between read and/or write
cycles
Port timing[2] (see Figure 15)
tPS
port in set-up time before RDN LOW
(Read IP ports cycle)
0
−20
-
ns
tPH
port in hold time after RDN HIGH
0
−20
-
ns
tPD
OP port valid after WRN or CEN HIGH
(OPR write cycle)
-
40
60
ns
read Rx FIFO
(RxRDY/FFULL interrupt)
-
40
60
ns
write Tx FIFO (TxRDY
interrupt)
-
40
60
ns
reset command (delta
break change interrupt)
-
40
60
ns
stop C/T command
(counter/timer interrupt
-
40
60
ns
read IPCR (delta input port
change interrupt)
-
40
60
ns
write IMR (clear of change
interrupt mask bit(s))
-
40
60
ns
Interrupt timing (see Figure 16)
tIR
INTRN (or OP3 to OP7 when used as
interrupts)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
54 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 67. Dynamic characteristics, 5 V operation[1] …continued
VCC = 5.0 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
30
20
-
ns
Clock timing (see Figure 17)
X1/CLK HIGH or LOW time
tCLK
[5]
fCLK
X1/CLK frequency
tCTC
C/T clock (IP2) HIGH or LOW time (C/T
external clock input)
fCTC
C/T clock (IP2) frequency
tRX
RxC HIGH or LOW time
fRX
RxC frequency
0.1
3.686
8
MHz
30
10
-
ns
0
-
8
MHz
16×
30
10
-
ns
16×
0
-
16
MHz
0
-
1
MHz
30
10
-
ns
-
-
16
MHz
0
-
1
MHz
[5]
1×
tTX
TxC HIGH or LOW time
fTX
TxC frequency
[5][6]
16×
16×
1×
[5][6]
Transmitter timing, external clock (see Figure 18)
tTXD
TxD output delay from TxC LOW (TxC
input pin)
-
40
60
ns
tTCS
output delay from TxC output pin LOW to
TxD data output
-
6
30
ns
Receiver timing, external clock (see Figure 19)
tRXS
RxD data set-up time to RxC HIGH
50
40
-
ns
tRXH
RxD data hold time from RxC HIGH
50
40
-
ns
-
15
35
ns
68xxx or Motorola bus timing (see Figure 12, 13 and 14)[7]
tDCR
DACKN LOW (read cycle) from X1 HIGH
[7]
tDCW
DACKN LOW (write cycle) from X1 HIGH
-
15
35
ns
tDAT
DACKN high-impedance from CEN or
IACKN HIGH
-
8
10
ns
tCSC
CEN or IACKN set-up time to X1 HIGH for
minimum DACKN cycle
16
8
-
ns
[1]
The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF,
constant current source = 2.6 mA.
d) Typical values are the average values at +25 °C and 5 V.
[2]
Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
[3]
Guaranteed by characterization of sample units.
[4]
If CEN is used as the strobing input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal
must be negated for tRWD to guarantee that any status register changes are valid.
[5]
Minimum frequencies are not tested but are guaranteed by design.
[6]
Clocks for 1× mode should maintain a 60/40 duty cycle or better.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
55 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[7]
Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus
cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation
of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN
initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
Table 68. Dynamic characteristics, 3.3 V operation[1]
VCC = 3.3 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
100
20
-
ns
10
6
-
ns
Reset timing (see Figure 10)
reset pulse width
tRES
Bus
timing[2]
(see Figure 11)
tAS
A0 to A3 set-up time to RDN, WRN LOW
tAH
A0 to A3 hold time from RDN, WRN LOW
33
16
-
ns
tCS
CEN set-up time to RDN, WRN LOW
0
-
-
ns
tCH
CEN hold time from RDN, WRN LOW
0
-
-
ns
tRW
WRN, RDN pulse width (LOW time)
20
10
-
ns
tDD
data valid after RDN LOW
-
46
75
ns
tDA
RDN LOW to data bus active
0
-
-
ns
tDF
data bus floating after RDN or CEN HIGH
-
15
20
ns
125 pF load; see Figure 9
for smaller loads
[3]
tDI
RDN or CEN HIGH to data bus invalid
tDS
data bus set-up time before WRN or CEN
HIGH (write cycle)
tDH
data hold time after WRN HIGH
tRWD
[4]
[2][4]
HIGH time between read and/or write
cycles
0
-
-
ns
43
20
-
ns
0
−15
-
ns
27
10
-
ns
Port timing[2] (see Figure 15)
tPS
port in set-up time before RDN LOW
(Read IP ports cycle)
0
−20
-
ns
tPH
port in hold time after RDN HIGH
0
−20
-
ns
tPD
OP port valid after WRN or CEN HIGH
(OPR write cycle)
-
50
75
ns
read Rx FIFO
(RxRDY/FFULL interrupt)
-
40
79
ns
write Tx FIFO (TxRDY
interrupt)
-
40
79
ns
reset command (delta
break change interrupt)
-
40
79
ns
stop C/T command
(counter/timer interrupt
-
40
79
ns
read IPCR (delta input port
change interrupt)
-
40
79
ns
write IMR (clear of change
interrupt mask bit(s))
-
40
79
ns
Interrupt timing (see Figure 16)
tIR
INTRN (or OP3 to OP7 when used as
interrupts)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
56 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 68. Dynamic characteristics, 3.3 V operation[1] …continued
VCC = 3.3 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
35
25
-
ns
Clock timing (see Figure 17)
X1/CLK HIGH or LOW time
tCLK
[5]
fCLK
X1/CLK frequency
tCTC
C/T clock (IP2) HIGH or LOW time (C/T
external clock input)
fCTC
C/T clock (IP2) frequency
tRX
RxC HIGH or LOW time
fRX
RxC frequency
0.1
3.686
8
MHz
30
15
-
ns
0
-
8
MHz
16×
30
10
-
ns
16×
0
-
16
MHz
0
-
1
MHz
30
15
-
ns
-
-
16
MHz
0
-
1
MHz
[5]
1×
tTX
TxC HIGH or LOW time
fTX
TxC frequency
[5][6]
16×
16×
1×
[5][6]
Transmitter timing, external clock (see Figure 18)
tTXD
TxD output delay from TxC LOW (TxC
input pin)
-
40
78
ns
tTCS
output delay from TxC output pin LOW to
TxD data output
-
8
30
ns
Receiver timing, external clock (see Figure 19)
tRXS
RxD data set-up time to RxC HIGH
50
10
-
ns
tRXH
RxD data hold time from RxC HIGH
50
10
-
ns
-
18
57
ns
68xxx or Motorola bus timing (see Figure 12, 13 and 14)[7]
tDCR
DACKN LOW (read cycle) from X1 HIGH
[7]
tDCW
DACKN LOW (write cycle) from X1 HIGH
-
18
57
ns
tDAT
DACKN high-impedance from CEN or
IACKN HIGH
-
10
15
ns
tCSC
CEN or IACKN set-up time to X1 HIGH for
minimum DACKN cycle
30
10
-
ns
[1]
The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF,
constant current source = 2.6 mA.
d) Typical values are the average values at +25 °C and 3.3 V.
[2]
Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
[3]
Guaranteed by characterization of sample units.
[4]
If CEN is used as the strobing input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal
must be negated for tRWD to guarantee that any status register changes are valid.
[5]
Minimum frequencies are not tested but are guaranteed by design.
[6]
Clocks for 1× mode should maintain a 60/40 duty cycle or better.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
57 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[7]
Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus
cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation
of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN
initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
11. Timing diagrams
tRES
RESET
RESETN
tRES
001aae304
001aae303
a. 80xxx mode
b. 68xxx mode
Fig 10. Reset timing
A0 to A3
tAS
tAH
CEN
tCS
tCS
tRW
tRWD
RDN
tDD
D0 to D7
(read)
float
tDF
not valid
valid
float
tRWD
WDN
tDS
tDH
D0 to D7
(write)
valid
001aae305
Fig 11. Bus timing (80xxx mode)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
58 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
tCSC
X1/CLK
tAS
A0 to A3
tCS
tCH
R/WN
tAH
tRWD
CEN
tDD
D0 to D7
tDF
not valid
data valid
tDAH
tDA
DACKN
tDCR
tDAT
001aae306
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 12. Bus timing, read cycle (68xxx mode)
tCSC
X1/CLK
tAS
A0 to A3
tCS
tCH
R/WN
tAH
tRWD
CEN
tDH
tDS
D0 to D7
tDAH
DACKN
tDCW
tDAT
001aae308
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 13. Bus timing, write cycle (68xxx mode)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
59 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
tCSC
X1/CLK
INTRN
IACKN
tDD
tDF
D0 to D7
tDCR
tDAH
DACKN
tDAL
tCSD
tDAT
001aae309
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 14. Interrupt cycle timing (68xxx mode)
RDN
tPS
tPH
IP0 to IP6
001aae311
a. Input pins.
WRN
tPD
OP0 to OP6
old data
new data
001aae312
b. Output pins.
Fig 15. Port timing
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
60 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
VM
WRN
tIR
interrupt output(1)
VOL + 0.5 V
VOL
RDN
VM
tIR
interrupt output(1)
VOL + 0.5 V
VOL
001aae313
The test for open-drain outputs is intended to guarantee switching of the output transistor.
Measurement of this response is referenced from the midpoint of the switching signal, VM, to a
point 0.2 V above VOL. This point represents noise margin that assures true switching has
occurred. Beyond this level, the effects of external circuitry and test environment are
pronounced and can greatly affect the resultant measurement.
(1) IRQN or OP3 to OP7 when used as interrupt outputs.
Fig 16. Interrupt timing (80xxx mode)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
61 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
X1/CLK
C/T clock
RxC
TxC
tCLK
tCTC
tRX
tTX
VCC
resistor required
for TTL input
CLK
X1
tCLK
tCTC
tRX
tTX
3 pF
parasitic capacitance
470 Ω
X2
(must be left open)
SC28L92
X1
2 pF
C1
50 kΩ
to
100 kΩ
3.6864 MHz
C2
4 pF
X2
to UART circuit
3 pF
parasitic capacitance
001aae314
C1 = C2 ∼ 24 pF for CL = 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series.
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1, X2 pins.
Package capacitance approximately 4 pF.
Fig 17. Clock timing
1 bit time
(1 or 16 clocks)
TxC
(input)
tTXD
TxD
tTCS
TxC
(1× output)
001aae315
Fig 18. Transmitter external clocks
RxC
(1× input)
tRXS
tRXH
RxD
001aae316
Fig 19. Receiver external clock
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
62 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
D1
TxD
D2
D3
break
D4
D6
transmitter
enabled
TxRDY
(SR2)
WRN
D1
D8
D9
CTSN(1)
start
break
stop
break
D10
(IP0)
D11 will not
be written to
the TxFIFO
D12
RTSN(2)
(OP0)
OPR(0) = 1
OPR(0) = 1
001aae317
(1) Timing shown for MR2[4] = 1.
(2) Timing shown for MR2[5] = 1.
Fig 20. Transmitter timing
D1
RxD
D2
D8
D9
D10
D11
D12
D13
D12, D13 will be lost
due to receiver disable
receiver
enabled
RxRDY
(SR)
FFULL
(CR)
RxRDY/
FFULL
(OP5)(2)
RDN
status data
D1
OVERRUN
(SR)
status data
status data
status data
D2
D3
D10
D11 will be lost
due to overrun
reset by command
RTS(1)
(OP0)
001aae318
OPR[0] = 1
(1) Timing shown for MR1[7] = 1.
(2) Shown for OPCR[4] = 1 and MR[6] = 0.
Fig 21. Receiver timing
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
63 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
master station:
bit 9
TxD
ADD#1 1
bit 9
bit 9
D0
ADD#2 1
0
transmitter
enabled
TxRDY
(SR)
WRN
ADD#2
MR1[4:3] = 11 ADD#1
D0
MR1[2] = 0
MR1[2] = 1
peripheral station:
bit 9
RxD
0
MR1[2] = 1
bit 9
ADD#1 1
bit 9
bit 9
D0
bit 9
ADD#2 1
0
0
receiver
enabled
RxRDY
(SR)
RDN/WRN
MR1[4:3] = 11
ADD#1
status data
status data
D0
ADD#2
001aae319
Fig 22. Wake-up mode timing
12. Test information
I = 2.4 mA
INTRN
DACKN
+5 V
125 pF
I = 2.4 mA VOL return to VCC for a 0 level
I = 400 µA VOH return to VSS for a 1 level
D0 to D7
TxDA/TxDB
OP0 to OP7
125 pF
001aae320
Fig 23. Test conditions on outputs
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
64 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
13. Package outline
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
bp
ZE
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
e
UNIT A
A3
D(1) E(1)
eD
eE
HD
bp b1
max.
min.
4.57
4.19
mm
inches
0.81
0.66
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
0.51
0.25
3.05
0.53
0.33
0.180
0.02
0.165
0.01
0.12
0.021 0.032 0.656 0.656
0.05
0.013 0.026 0.650 0.650
0.63
0.59
0.63
0.59
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.695 0.695 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.685 0.685 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT187-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 24. Package outline SOT187-2 (PLCC44)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
65 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
2.1
0.25
0.05
1.85
1.65
0.25
0.4
0.2
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
10
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
97-08-01
03-02-25
SOT307-2
Fig 25. Package outline SOT307-2 (QFP44)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
66 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 x 6 x 0.85 mm
D
SOT778-4
A
B
terminal 1
index area
E
A
A1
c
detail X
C
e1
e
v
w
b
1/2 e
13
M
M
y1 C
C A B
C
y
24
L
25
12
e
e2
Eh
1/2 e
1
36
terminal 1
index area
48
37
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.25
0.15
0.2
6.1
5.9
4.75
4.45
6.1
5.9
4.75
4.45
0.4
4.4
4.4
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT778-4
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
04-07-30
04-10-07
Fig 26. Package outline SOT778-4 (HVQFN48)
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
67 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
68 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 69 and 70
Table 69.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 70.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 27.
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
69 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 71.
Abbreviations
Acronym
Description
DMA
Direct Memory Access
UART
Universal Asynchronous Receiver/Transmitter
FIFO
First In/First Out
CPU
Central Processing Unit
COS
Change Of State
BRG
Baud Rate Generator
MIDI
Musical Instrument Digital Interface
C/T
Counter/Timer
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
70 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
16. Revision history
Table 72.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SC28L92_7
20071219
Product data sheet
-
SC28L92_6
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
added HVQFN48 package option
Figure 1 “Block diagram (80xxx mode)” modified:
– reversed position of “control” and “timing” notations
– reversed direction of signals IP0 to IP6
•
Figure 2 “Block diagram (68xxx mode)” modified:
– corrected pin name from “RDN” to “R/WN”
– corrected pin name from “WRN” to “IACKN”
– corrected pin name from “RESET” to “RESETN”
– added signal DACKN
– reversed position of “control” and “timing” notations
– reversed direction of signals IP0 to IP5
•
Section 6.1.4 “FIFO configuration”:
– 1st paragraph, 4th sentence: changed “MR0[3] bit” to “MR0A[3] bit”
– 1st paragraph, added new 6th sentence
– 2nd paragraph: changed “MR0[3] bit” to “MR0A[3] bit”
•
Table 24 “MR0A - Mode Register 0 channel A (address 0x0) bit description”:
– description for bit 3: added “for channel A and channel B”
– description for bits [2:0]: in last line of description, changed “MR2[2:0]” to “MR0[2:0]”
•
Table 25:
– added Table note 1
– removed “(default)” (2 places)
•
Table 26:
– added Table note 1
– removed “(default)” (2 places)
•
•
Section 7.3.1.4 “Mode Register 0 channel B (MR0B)”, 2nd paragraph re-written.
Table 64 “Limiting values”: added specifications for HVQFN48 package
SC28L92_6
20060426
Product data sheet
-
SC28L92_5
(9397 750 13125)
SC28L92_5
(9397 750 13125)
20040907
Product specification
-
SC28L92_4
(9397 750 06796)
SC28L92_4
(9397 750 06796)
20000121
Product specification
-
SC28L92_3
(9397 750 05979)
SC28L92_3
(9397 750 05979)
19990507
Product specification
-
SC28L92_2
(9397 750 04465)
SC28L92_2
(9397 750 04465)
19981005
Preliminary specification
-
SC28L92_1
SC28L92_1
-
-
-
-
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
71 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
SC28L92_7
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 07 — 19 December 2007
72 of 73
SC28L92
NXP Semiconductors
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
19. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
7
7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.3
7.3.1.4
7.3.1.5
7.3.1.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data bus buffer . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation control . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 13
FIFO configuration . . . . . . . . . . . . . . . . . . . . . 14
68xxx mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing circuits. . . . . . . . . . . . . . . . . . . . . . . . . 14
Crystal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Baud rate generator . . . . . . . . . . . . . . . . . . . . 15
Counter/timer . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . 16
Time-out mode . . . . . . . . . . . . . . . . . . . . . . . . 16
Time-out mode caution . . . . . . . . . . . . . . . . . . 17
Communications channels A and B . . . . . . . . 17
Input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transmitter reset and disable . . . . . . . . . . . . . 19
Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . 20
Receiver status bits . . . . . . . . . . . . . . . . . . . . 20
Receiver reset and disable . . . . . . . . . . . . . . . 20
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Receiver time-out mode . . . . . . . . . . . . . . . . . 21
Time-out mode caution . . . . . . . . . . . . . . . . . . 22
Multi-drop mode (9-bit or wake-up). . . . . . . . . 22
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register overview . . . . . . . . . . . . . . . . . . . . . . 22
Condensed register bit formats. . . . . . . . . . . . 24
Register descriptions . . . . . . . . . . . . . . . . . . . 26
Mode registers . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode Register 0 channel A (MR0A) . . . . . . . . 26
Mode Register 1 channel A (MR1A) . . . . . . . . 28
Mode Register 2 channel A (MR2A) . . . . . . . . 29
Mode Register 0 channel B (MR0B) . . . . . . . . 32
Mode Register 1 channel B (MR1B) . . . . . . . . 32
Mode Register 2 channel B (MR2B) . . . . . . . . 32
7.3.2
7.3.2.1
7.3.2.2
7.3.3
7.3.3.1
7.3.3.2
7.3.4
7.3.4.1
7.3.4.2
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.4
7.5
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
Clock select registers . . . . . . . . . . . . . . . . . . .
Clock Select Register channel A (CSRA). . . .
Clock Select Register channel B (CSRB). . . .
Command registers . . . . . . . . . . . . . . . . . . . .
Command Register channel A (CRA) . . . . . .
Command Register channel B (CRB) . . . . . .
Status registers . . . . . . . . . . . . . . . . . . . . . . .
Status Register channel A (SRA). . . . . . . . . .
Status Register channel B (SRB). . . . . . . . . .
Output Configuration Control Register
(OPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Output Port bits Register (SOPR) . . . . . .
Reset Output Port bits Register (ROPR) . . . .
Output Port Register (OPR) . . . . . . . . . . . . . .
Auxiliary Control Register (ACR) . . . . . . . . . .
Input Port Change Register (IPCR) . . . . . . . .
Interrupt Status Register (ISR). . . . . . . . . . . .
Interrupt Mask Register (IMR) . . . . . . . . . . . .
Interrupt Vector Register (IVR; 68xxx mode)
or General Purpose register
(GP; 80xxx mode) . . . . . . . . . . . . . . . . . . . . .
Counter/timer registers. . . . . . . . . . . . . . . . . .
Output port notes . . . . . . . . . . . . . . . . . . . . . .
The CTS, RTS, CTS enable Tx signals . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . .
Test information. . . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
35
35
36
37
37
39
39
41
42
43
44
45
45
47
48
48
49
49
50
51
54
58
64
65
68
68
68
68
69
70
71
72
72
72
72
72
72
73
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 December 2007
Document identifier: SC28L92_7
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