Data Sheet

SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 05 — 12 January 2009
Product data sheet
1. General description
The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and
RXRDYn signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loopback capability allows
on-board diagnostics. Independent programmable baud rate generators are provided to
select transmit and receive baud rates.
The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
1.
2 channel UART
5 V, 3.3 V and 2.5 V operation
5 V tolerant on input only pins1
Industrial temperature range
Pin and functionally compatible to 16C2450 and software compatible with INS8250,
SC16C550
Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V
16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
16-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive FIFO interrupt trigger levels
Software selectable baud rate generator
Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break)
Transmit, Receive, Line Status and Data Set interrupts independently controlled
For data bus pins D7 to D0, see Table 23 “Limiting values”.
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
n Fully programmable character formatting:
u 5-bit, 6-bit, 7-bit or 8-bit characters
u Even, odd or no-parity formats
u 1, 11⁄2 or 2-stop bit
u Baud generation (DC to 5 Mbit/s)
n False start-bit detection
n Complete status reporting capabilities
n 3-state output TTL drive capabilities for bidirectional data bus and control bus
n Line break generation and detection
n Internal diagnostic capabilities:
u Loopback controls for communications link fault isolation
n Prioritized interrupt system controls
n Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
SC16C2550BIA44
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
SC16C2550BIBS
HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617-1
SC16C2550BIB48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
SC16C2550BIN40
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Topside mark
SC16C2550BIA44
SC16C2550BIA44
SC16C2550BIBS
2550B
SC16C2550BIB48
16C2550B
SC16C2550BIN40
SC16C2550BIN40
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
2 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
4. Block diagram
SC16C2550B
A0 to A2
CSA
CSB
TRANSMIT
SHIFT
REGISTER
TXA, TXB
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
D0 to D7
IOR
IOW
RESET
TRANSMIT
FIFO
REGISTER
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
002aaa595
XTAL1
Fig 1.
XTAL2
Block diagram of SC16C2550B
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
3 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5. Pinning information
25 CTSA
26 VCC
27 D0
28 D1
29 D2
30 D3
32 D5
terminal 1
index area
31 D4
5.1 Pinning
D6
1
24 RESET
D7
2
23 RTSA
RXB
3
22 OP2A
RXA
4
TXA
5
TXB
6
19 A0
OP2B
7
18 A1
CSA
8
17 A2
21 INTA
20 INTB
CTSB 16
RTSB 15
IOR 14
GND 13
IOW 12
XTAL2 11
9
CSB
XTAL1 10
SC16C2550BIBS
002aab746
Transparent top view
Fig 2.
Pin configuration for HVQFN32
SC16C2550BIN40
D0
1
40 VCC
D1
2
39 RIA
D2
3
38 CDA
D3
4
37 DSRA
D4
5
36 CTSA
D5
6
35 RESET
D6
7
34 DTRB
D7
8
33 DTRA
RXB
9
32 RTSA
RXA 10
31 OP2A
TXA 11
30 INTA
TXB 12
29 INTB
OP2B 13
28 A0
CSA 14
27 A1
CSB 15
26 A2
XTAL1 16
25 CTSB
XTAL2 17
24 RTSB
IOW 18
23 RIB
CDB 19
22 DSRB
GND 20
21 IOR
002aaa596
Fig 3.
Pin configuration for DIP40
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
4 of 43
SC16C2550B
NXP Semiconductors
1
40 CTSA
D0
TXRDYA
2
41 DSRA
D1
3
42 CDA
D2
4
43 RIA
D3
5
44 VCC
D4
6
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D5
7
39 RESET
D6
8
38 DTRB
D7
9
37 DTRA
RXB 10
36 RTSA
RXA 11
35 OP2A
SC16C2550BIA44
TXRDYB 12
33 INTA
TXB 14
32 INTB
CTSB 28
RTSB 27
RIB 26
IOR 24
DSRB 25
RXRDYB 23
GND 22
37 n.c.
38 CTSA
39 DSRA
40 CDA
42 VCC
41 RIA
43 TXRDYA
44 D0
45 D1
46 D2
47 D3
48 D4
D5
1
36 RESET
D6
2
35 DTRB
D7
3
34 DTRA
RXB
4
33 RTSA
RXA
5
32 OP2A
TXRDYB
6
TXA
7
TXB
8
29 INTB
OP2B
9
28 A0
CSA 10
27 A1
CSB 11
26 A2
n.c. 12
25 n.c.
31 RXRDYA
n.c. 24
CTSB 23
30 INTA
RTSB 22
RIB 21
IOR 19
DSRB 20
RXRDYB 18
GND 17
CDB 16
IOW 15
SC16C2550BIB48
002aaa598
Pin configuration for LQFP48
SC16C2550B_5
Product data sheet
002aaa597
Pin configuration for PLCC44
XTAL1 13
Fig 5.
CDB 21
29 A2
IOW 20
30 A1
CSB 17
XTAL2 19
31 A0
CSA 16
XTAL1 18
OP2B 15
XTAL2 14
Fig 4.
34 RXRDYA
TXA 13
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
5 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
HVQFN32 DIP40 PLCC44 LQFP48
A0
19
28
31
28
I
Address 0 select bit. Internal register address selection.
A1
18
27
30
27
I
Address 1 select bit. Internal register address selection.
A2
17
26
29
26
I
Address 2 select bit. Internal register address selection.
CSA
8
14
16
10
I
CSB
9
15
17
11
I
Chip Select A, B (active LOW). This function is associated
with individual channels, A through B. These pins enable data
transfers between the user CPU and the SC16C2550B for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective CSA, CSB
pin.
D0
27
1
2
44
I/O
D1
28
2
3
45
I/O
D2
29
3
4
46
I/O
D3
30
4
5
47
I/O
D4
31
5
6
48
I/O
D5
32
6
7
1
I/O
D6
1
7
8
2
I/O
D7
2
8
9
3
I/O
GND
13
20
22
17
I
Signal and power ground.
INTA
21
30
33
30
O
INTB
20
29
32
29
O
Interrupt A, B (3-state). This function is associated with
individual channel interrupts, INTA, INTB. INTA, INTB are
enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the Interrupt Enable Register (IER) and is active
when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty or when a modem status flag is detected.
IOR
14
21
24
19
I
Read strobe (active LOW strobe). A logic 0 transition on this
pin will load the contents of an internal register defined by
address bits A0 to A2 onto the SC16C2550B data bus
(D0 to D7) for access by external CPU.
IOW
12
18
20
15
I
Write strobe (active LOW strobe). A logic 0 transition on this
pin will transfer the contents of the data bus (D0 to D7) from the
external CPU to an internal register that is defined by address
bits A0 to A2.
OP2A
22
31
35
32
O
OP2B
7
13
15
9
O
Output 2 (user-defined). This function is associated with
individual channels, A through B. The state at these pin(s) are
defined by the user and through MCR register bit 3. INTA, INTB
are set to the active mode and OP2 to logic 0 when MCR[3] is
set to a logic 1. INTA, INTB are set to the 3-state mode and
OP2 to a logic 1 when MCR[3] is set to a logic 0. See Table 18
“Modem Control Register bits description”, bit 3 (MCR[3]).
Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function should be used at one time, INT
or OP2.
Data bus (bidirectional). These pins are the 8-bit, 3-state data
bus for transferring information to or from the controlling CPU.
D0 is the least significant bit and the first data bit in a transmit
or receive serial data stream.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
6 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
HVQFN32 DIP40 PLCC44 LQFP48
RESET
24
35
39
36
I
Reset (active HIGH). A logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output and
the receiver input will be disabled during reset time. (See
Section 7.10 “SC16C2550B external reset condition” for
initialization details.)
RXRDYA
-
-
34
31
O
RXRDYB -
-
23
18
O
Receive Ready A, B (active LOW). This function is associated
with PLCC44 and LQFP48 packages only. This function
provides the RX FIFO/RHR status for individual receive
channels (A-B). RXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive
ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty
or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA
mode 0).
TXRDYA
-
-
1
43
O
TXRDYB
-
-
12
6
O
VCC
26
40
44
42
I
Power supply input.
XTAL1
10
16
18
13
I
Crystal or external clock input. Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. Alternatively, an external clock can be connected to this
pin to provide custom data rates. (See Section 6.5
“Programmable baud rate generator”.) See Figure 6.
XTAL2
11
17
19
14
O
Output of the crystal oscillator or buffered clock. (See also
XTAL1.) Crystal oscillator output or buffered clock output.
Should be left open if an external clock is connected to XTAL1.
For extended frequency operation, this pin should be tied to
VCC via a 2 kΩ resistor.
CDA
-
38
42
40
I
CDB
-
19
21
16
I
Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through B. A logic 0 on this
pin indicates that a carrier has been detected by the modem for
that channel.
CTSA
25
36
40
38
I
CTSB
16
25
28
23
I
Transmit Ready A, B (active LOW). This function is
associated with PLCC44 and LQFP48 packages only. These
outputs provide the TX FIFO/THR status for individual transmit
channels (A, B). TXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the transmit data FIFOs. An
individual channel’s TXRDYA, TXRDYB buffer ready status is
indicated by logic 0, that is, at least one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA
mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers
(DMA mode 0).
Clear to Send (active LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on the CTSn
pin indicates the modem or data set is ready to accept transmit
data from the SC16C2550B. Status can be tested by reading
MSR[4]. This pin has no effect on the UART’s transmit or
receive operation.
SC16C2550B_5
Product data sheet
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Rev. 05 — 12 January 2009
7 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicates the modem or data set is powered-on and is ready
for data exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
HVQFN32 DIP40 PLCC44 LQFP48
DSRA
-
37
41
39
I
DSRB
-
22
25
20
I
DTRA
-
33
37
34
O
DTRB
-
34
38
35
O
RIA
-
39
43
41
I
RIB
-
23
26
21
I
RTSA
23
32
36
33
O
RTSB
15
24
27
22
O
RXA
4
10
11
5
I
RXB
3
9
10
4
I
TXA
5
11
13
7
O
TXB
6
12
14
8
O
n.c.
-
-
-
12, 24,
25, 37
-
Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through B.
A logic 0 on this pin indicates that the SC16C2550B is
powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set
the DTRn output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0] or after a reset.
This pin has no effect on the UART’s transmit or receive
operation.
Ring Indicator (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicates the modem has received a ringing signal from the
telephone line. A logic 1 transition on this input pin will generate
an interrupt.
Request to Send (active LOW). These outputs are associated
with individual UART channels, A through B. A logic 0 on the
RTSn pin indicates the transmitter has data ready and waiting
to send. Writing a logic 1 in the Modem Control Register
MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset this pin will be set to a logic 1. This pin has no
effect on the UART’s transmit or receive operation.
Receive data A, B. These inputs are associated with individual
serial channel data to the SC16C2550B receive input circuits,
A and B. The RXn signal will be a logic 1 during reset, idle (no
data) or when the transmitter is disabled. During the local
Loopback mode, the RXn input pin is disabled and TX data is
connected to the UART RX input, internally.
Transmit data A, B. These outputs are associated with
individual serial transmit channel data from the SC16C2550B.
The TXn signal will be a logic 1 during reset, idle (no data) or
when the transmitter is disabled. During the local Loopback
mode, the TXn output pin is disabled and TX data is internally
connected to the UART RX input.
not connected
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
8 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6. Functional description
The SC16C2550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is insured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C2550B represents such
an integration with greatly enhanced features. The SC16C2550B is fabricated with an
advanced CMOS process.
The SC16C2550B is an upward solution that provides a dual UART capability with
16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The
SC16C2550B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is realized in
the SC16C2550B by the transmit and receive FIFOs. This allows the external processor to
handle more networking tasks within a given time. For example, the ST16C2450 without a
receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a
character length of 11 bits, including start/stop bits at 115.2 kbit/s). This means the
external CPU will have to service the receive FIFO less than every 100 microseconds.
However, with the 16-byte FIFO in the SC16C2550B, the data buffer will not require
unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU
additional time for other applications and reducing the overall UART interrupt servicing
time. In addition, the four selectable receive FIFO trigger interrupt levels are uniquely
provided for maximum data throughput performance especially when operating in a
multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement
of the external controlling CPU, increases performance and reduces power consumption.
The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature set of the SC16C2550B is available through internal registers. Selectable
receive FIFO trigger levels, selectable TX and RX baud rates and modem interface
controls are all standard features. Following a power-on reset or an external reset, the
SC16C2550B is software compatible with the previous generation, ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bidirectionally transfer information
between an external CPU, the SC16C2550B package and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A through B. Individual channel select functions
are shown in Table 4.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
9 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 4.
Serial port selection
Chip Select
Function
CSA, CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 5. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) and a
user-accessible Scratchpad Register (SPR).
Table 5.
A2
Internal registers decoding
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
Interrupt Enable Register
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
1
Line Control Register
Line Control Register
1
0
0
Modem Control Register
Modem Control Register
1
0
1
Line Status Register
n/a
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Baud rate register set
(DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
10 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.3 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
Table 6.
Flow control mechanism
Selected trigger level (characters)
INTn pin activation
1
1
4
4
8
8
14
14
6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C2550B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. A condition can exist where a higher priority interrupt may mask the lower
priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reflected in the status register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C2550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center
of each stop bit received or each time the Receive Holding Register (RHR) is read. The
actual time-out value is 4 character time, including data information length, start bit, parity
bit and the size of stop bit, that is, 1×, 1.5× or 2× bit times.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
11 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.5 Programmable baud rate generator
The SC16C2550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC16C2550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generator is capable of
operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary
to use full rail swing on the clock input. The SC16C2550B can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins.
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates (see Table 7).
The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The
SC16C2550B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 7 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF
XTAL1
XTAL2
X1
1.8432 MHz
C2
33 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa870
Fig 6.
Crystal oscillator connection
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SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 7.
Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
(bit/s)
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(hexadecimal)
DLM
program value
(hexadecimal)
DLL
program value
(hexadecimal)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
6.6 DMA operation
The SC16C2550B FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an
empty location(s). The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C2550B activates the interrupt output pin
(INTn) for each data transmit or receive operation. When DMA mode is activated (DMA
Mode 1), the user takes the advantage of block mode operation by loading or unloading
the FIFO in a block sequence determined by the receive trigger level and the transmit
FIFO. In this mode, the SC16C2550B sets the TXRDYn (or RXRDYn) output pin when
characters in the transmit FIFO is below 16 or the characters in the receive FIFOs are
above the receive trigger level.
6.7 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see Figure 7). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins and instead are connected together
internally. The CTS, DSR, CD and RI are disconnected from their normal modem control
input pins and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]
(OP1). Loopback test data is entered into the transmit holding register via the user data
bus interface, D0 through D7. The transmit UART serializes the data and passes the serial
data to the receive UART via the internal loopback connection. The receive UART
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Rev. 05 — 12 January 2009
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SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
converts the serial data back into parallel data that is then made available at the user data
interface D0 through D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The modem
control interrupts are also operational.
SC16C2550B
D0 to D7
IOR
IOW
RESET
TRANSMIT
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL
LOGIC
A0 to A2
CSA, CSB
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MCR[4] = 1
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
MODEM
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
DSRA, DSRB
(OP1A, OP1B)
CLOCK AND
BAUD RATE
GENERATOR
RIA, RIB
(OP2A, OP2B)
CDA, CDB
002aaa599
XTAL1
Fig 7.
XTAL2
Internal Loopback mode diagram
SC16C2550B_5
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Rev. 05 — 12 January 2009
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SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7. Register descriptions
Table 8 details the assigned bit functions for the SC16C2550B internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
Table 8.
SC16C2550B internal registers
A2
A0
A1
Register Default[1] Bit 7
General register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 2
bit 1
bit 0
transmit
holding
register
interrupt
receive
holding
register
set[2]
0
0
0
RHR
XX
bit 7
bit 6
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
0
0
1
IER
00
0
0
0
0
modem receive
status
line
interrupt status
interrupt
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
reserved reserved DMA
0
0
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
0
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
1
LCR
00
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
bit 1
1
0
0
MCR
00
0
0
loop
back
OP2/INT (OP1)
enable
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
THR and THR
TSR
empty
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR
X0
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
∆CTS
1
1
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
word
length
bit 0
Special register set[3]
0
0
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
[1]
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2]
Accessible only when LCR[7] is logic 0.
[3]
Baud rate registers accessible only when LCR[7] is logic 1.
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag
in the LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
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15 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time
should be shifted to the center of the start bit. At this time the start bit is sampled and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 9.
Interrupt Enable Register bits description
Bit
Symbol
Description
7:4
IER[7:4]
not used
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a
receive data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1
IER[1]
Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will
be issued whenever the THR is empty and is associated with LSR[5]. In the
FIFO modes, this interrupt will be issued whenever the FIFO is empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
0
IER[0]
Receive Holding Register. In the 16C450 mode, this interrupt will be issued
when the RHR has data or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the
programmed trigger level or is cleared when the FIFO drops below the
trigger level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR register or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
•
•
•
•
•
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels and select the DMA mode.
7.3.1 DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation and is similar to
the 16C450 mode. Transmit Ready (TXRDYn) on PLCC44 and LQFP48 packages will go
to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready
(RXRDYn) on PLCC44 and LQFP48 packages will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is empty. TXRDYn on PLCC44 and LQFP48 packages remains a logic 0
as long as one empty FIFO location is available. The receive interrupt is set when the
receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
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17 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and
LQFP48 packages transitions LOW when the FIFO reaches the trigger level and
transitions HIGH when the FIFO empties.
7.3.2 FIFO mode
Table 10.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7:6]
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
logic 0 (or cleared) = normal default condition
logic 1 = RX trigger level
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to be
loaded until it is full. Refer to Table 11.
5:4
FCR[5:4]
Not used; initialized to logic 0.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C2550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0) and when there are no
characters in the transmit FIFO or Transmit Holding Register, the TXRDYn
pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the
TXRDYn pin will go to a logic 1 after the first character is loaded into the
Transmit Holding Register.
Receive operation in mode ‘0’: When the SC16C2550B is in mode ‘0’
(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDYn pin will be a logic 0.
Once active, the RXRDYn pin on PLCC44 and LQFP48 packages will go
to a logic 1 when there are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C2550B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin on PLCC44
and LQFP48 packages will be a logic 1 when the transmit FIFO is
completely full. It will be a logic 0 if one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached
or a Receive Time-out has occurred, the RXRDYn pin on PLCC44 and
LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1
after there are no more characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
logic 0 = Transmit FIFO not reset (normal default condition).
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
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SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 10.
FIFO Control Register bits description …continued
Bit
Symbol
Description
1
FCR[1]
RCVR FIFO reset.
logic 0 = Receive FIFO not reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFOs enabled.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to or they will not be programmed.
Table 11.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0
0
01
0
1
04
1
0
08
1
1
14
7.4 Interrupt Status Register (ISR)
The SC16C2550B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. A lower level interrupt may be seen after servicing the
higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”
shows the data values (bits 3:0) for the four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels.
Table 12.
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
1
0
LSR (Receiver Line Status Register)
2
0
1
0
0
RXRDY (Received Data Ready)
2
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
1
0
TXRDY (Transmitter Holding Register empty)
4
0
0
0
0
MSR (Modem Status Register)
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SC16C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 13.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC16C2550B mode.
logic 0 or cleared = default condition
5:4
ISR[5:4]
not used
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2 and 3 (see Table 12).
0
ISR[0]
INT status.
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 14.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3
LCR[5:3]
Programs the parity conditions (see Table 15)
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see Table 16).
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Table 15.
LCR[5:3] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
X
0
1
odd parity
0
1
1
even parity
0
0
1
forced parity ‘1’
1
1
1
forced parity ‘0’
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SC16C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 16.
LCR[2] stop bit length
LCR[2]
Word length (bits)
Stop bit length (bit times)
0
5, 6, 7, 8
1
1
5
11⁄2
1
6, 7, 8
2
Table 17.
LCR[1:0] word length
LCR[1]
LCR[0]
Word length (bits)
0
0
5
0
1
6
1
0
7
1
1
8
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 18.
Modem Control Register bits description
Bit
Symbol
Description
7:5
MCR[7:5]
reserved; set to ‘0’
4
MCR[4]
Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD and RI
are disconnected from the SC16C2550B I/O pins. Internally the modem
data and control pins are connected into a loopback data configuration
(see Figure 7). In this mode, the receiver and transmitter interrupts remain
fully operational. The Modem Control Interrupts are also operational, but
the interrupts’ sources are switched to the lower four bits of the Modem
Control. Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3
MCR[3]
OP2/INT enable
logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2 to a
logic 1 (normal default condition)
logic 1 = forces the INT (A, B outputs to the active mode and sets OP2 to
a logic 0
2
MCR[2]
(OP1). OP1A/OP1B are not available as an external signal in the
SC16C2550B. This bit is instead used in the Loopback mode only. In the
Loopback mode, this bit is used to write the state of the modem RI
interface signal.
1
MCR[1]
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0]
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550B and
the CPU.
Table 19.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error flags
associated with the remaining data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the Transmit Holding Register and the Transmit Shift Register
are both empty. It is reset to logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode, this bit is set to ‘1’ whenever the Transmit
FIFO and Transmit Shift Register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.
3
LSR[3]
Framing error.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop bit(s). In
the FIFO mode, this error is associated with the character at the top of the
FIFO.
2
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the Receive Shift Register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
22 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 19.
Line Status Register bits description …continued
Bit
Symbol
Description
0
LSR[0]
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem or
other peripheral device to which the SC16C2550B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 20.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the Loopback mode produces the state of MCR[3] (OP2).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the Loopback mode produces the state of MCR[2] (OP1).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the Loopback mode, this bit is equivalent to MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the Loopback mode, this bit is equivalent to MCR[1] (RTS).
3
MSR[3]
∆CD [1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
2
MSR[2]
∆RI [1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C2550B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1
MSR[1]
∆DSR [1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
∆CTS [1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1]
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
23 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.9 Scratchpad Register (SPR)
The SC16C2550B provides a temporary data register to store 8 bits of user information.
7.10 SC16C2550B external reset condition
Table 21.
Reset state for registers
Register
Reset state
IER
IER[7:0] = 0
FCR
FCR[7:0] = 0
ISR
ISR[7:1] = 0; ISR[0] = 1
LCR
LCR[7:0] = 0
MCR
MCR[7:0] = 0
LSR
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR
MSR[7:4] = input signals; MSR[3:0] = 0
SPR
SFR[7:0] = 1
DLL
DLL[7:0] = X
DLM
DLM[7:0] = X
Table 22.
Reset state for outputs
Output
Reset state
TXA, TXB
logic 1
OP2A, OP2B
logic 1
RTSA, RTSB
logic 1
DTRA, DTRB
logic 1
INTA, INTB
3-state condition
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
24 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
8. Limiting values
Table 23. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Vn
voltage on any other pin
Conditions
Min
Max
Unit
-
7
V
at D7 to D0 pins
GND − 0.3
VCC + 0.3
V
at input only pins
GND − 0.3
5.3
V
Tamb
operating temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ptot/pack
total power dissipation per package
-
500
mW
9. Static characteristics
Table 24. Static characteristics
Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified.
Symbol Parameter
VIL(clk)
clock LOW-level input voltage
Conditions
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
Unit
Min
Max
Min
Max
Min
Max
−0.3
+0.45
−0.3
+0.6
−0.5
+0.6
V
VIH(clk)
clock HIGH-level input voltage
1.8
VCC
2.4
VCC
3.0
VCC
V
VIL
LOW-level input voltage
except X1 clock
−0.3
+0.65
−0.3
+0.8
−0.5
+0.8
V
VIH
HIGH-level input voltage
except X1 clock
1.6
-
2.0
-
2.2
-
V
IOL = 5 mA
(data bus)
-
-
-
-
-
0.4
V
IOL = 4 mA
(other outputs)
-
-
-
0.4
-
-
V
IOL = 2 mA
(data bus)
-
0.4
-
-
-
-
V
IOL = 1.6 mA
(other outputs)
-
0.4
-
-
-
-
V
IOH = −5 mA
(data bus)
-
-
-
-
2.4
-
V
IOH = −1 mA
(other outputs)
-
-
2.0
-
-
-
V
IOH = −800 µA
(data bus)
1.85
-
-
-
-
-
V
IOH = −400 µA
(other outputs)
1.85
-
-
-
-
-
V
LOW-level output voltage
VOL
VOH
HIGH-level output voltage
on all
outputs[1]
ILIL
LOW-level input leakage current
-
±10
-
±10
-
±10
µA
IL(clk)
clock leakage current
-
±30
-
±30
-
±30
µA
ICC
supply current
-
3.5
-
4.5
-
4.5
mA
Ci
input capacitance
-
5
-
5
-
5
pF
[1]
Except XTAL2, VOL = 1 V typical.
f = 5 MHz
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
25 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
10. Dynamic characteristics
Table 25. Dynamic characteristics
Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified.
Symbol
Parameter
Conditions
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
Min
Max
Min
Max
Min
Max
Unit
tw1
clock pulse duration
10
-
6
-
6
-
ns
tw2
clock pulse duration
10
-
6
-
6
-
ns
-
48
-
80
0
-
0
-
[1][2]
fXTAL
oscillator/clock frequency
t6s
address set-up time
t6h
address hold time
0
-
0
-
0
-
ns
t7d
IOR delay from chip select
10
-
10
-
10
-
ns
t7w
IOR strobe width
77
-
26
-
23
-
ns
t7h
chip select hold time from
IOR
0
-
0
-
0
-
ns
t9d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
25 pF load
80
0
-
MHz
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
t13w
IOW strobe width
20
-
20
-
15
-
ns
t13h
chip select hold time from
IOW
0
-
0
-
0
-
ns
t15d
write cycle delay
25
-
25
-
20
-
ns
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from
Modem input
25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from 25 pF load
IOR
-
100
-
24
-
23
ns
t20d
delay from stop to set
interrupt
-
TRCLK
-
TRCLK
-
TRCLK
s
t21d
delay from IOR to reset
interrupt
-
100
-
29
-
28
ns
t22d
delay from start to set
interrupt
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit
start
t24d
delay from IOW to reset
interrupt
t25d
delay from stop to set
RXRDY
t26d
t27d
[3]
25 pF load
[3]
8TRCLK 24TRCLK 8TRCLK 24TRCLK 8TRCLK 24TRCLK s
-
100
-
45
-
40
ns
-
TRCLK
-
TRCLK
-
TRCLK
s
delay from IOR to reset
RXRDY
-
100
-
45
-
40
ns
delay from IOW to set
TXRDY
-
100
-
45
-
40
ns
[3]
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
26 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 25. Dynamic characteristics …continued
Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified.
Symbol
Parameter
Conditions
VCC = 2.5 V
t28d
delay from start to reset
TXRDY
[3]
tRESET
RESET pulse width
[4]
N
baud rate divisor
VCC = 3.3 V
VCC = 5.0 V
Unit
Min
Max
Min
Max
Min
Max
-
8TRCLK
-
8TRCLK
-
8TRCLK
s
200
-
40
-
40
-
ns
(216
1
− 1)
1
(216
− 1)
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency = -------
[3]
RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
[4]
Reset pulse must happen when these signals are inactive: CS, IOW, IOR.
1
(216
− 1)
1
t w3
10.1 Timing diagrams
t6h
valid
address
A0 to A2
t13h
t6s
active
CSA, CSB
t13d
IOW
t15d
t13w
active
t16s
D0 to D7
t16h
data
002aae279
Fig 8.
General write timing
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
27 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
t6h
valid
address
A0 to A2
t7h
t6s
active
CSA, CSB
t7d
t9d
t7w
IOR
active
t12h
t12d
D0 to D7
data
002aae278
Fig 9.
General read timing
IOW
active
t17d
RTSA, RTSB
DTRA, DTRB
change of state
change of state
CDA, CDB
CTSA, CTSB
DSRA, DSRB
change of state
t18d
INTA, INTB
change of state
t18d
active
active
active
t19d
IOR
active
active
active
t18d
change of state
RIA, RIB
002aae277
Fig 10. Modem input/output timing
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
28 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
tw2
tw1
EXTERNAL
CLOCK
002aaa112
tw3
1
f XTAL = ------t w3
Fig 11. External clock timing
start
bit
RXA, RXB
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
7 data bits
t20d
active
INTA, INTB
t21d
active
IOR
16 baud rate clock
002aae276
Fig 12. Receive timing
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
29 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
start
bit
D0
RXn
parity
bit
data bits (0 to 7)
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
t25d
active data
ready
RXRDYn
t26d
active
IOR
002aae275
Fig 13. Receive ready timing in non-FIFO mode
start
bit
RXA, RXB
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
D7
first byte that
reaches the
trigger level
t25d
active data
ready
RXRDYA, RXRDYB
t26d
active
IOR
002aae274
Fig 14. Receive ready timing in FIFO mode
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
30 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
start
bit
parity
bit
data bits (0 to 7)
TXA, TXB
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
7 data bits
active
transmitter ready
INTA, INTB
t22d
t24d
t23d
IOW
active
active
16 baud rate clock
002aae273
Fig 15. Transmit timing
start
bit
TXA, TXB
D0
IOW
active
D0 to D7
byte #1
parity
bit
data bits (0 to 7)
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
t28d
t27d
active
transmitter ready
TXRDYA, TXRDYB
transmitter
not ready
002aae272
Fig 16. Transmit ready timing in non-FIFO mode
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
31 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
start
bit
data bits (0 to 7)
D0
TXA, TXB
parity
bit
D1
D2
D3
D4
D5
D6
stop
bit
D7
5 data bits
6 data bits
7 data bits
IOW
active
t28d
D0 to D7
byte #16
t27d
TXRDYA, TXRDYB
FIFO full
002aae271
Fig 17. Transmit ready timing in FIFO mode (DMA mode ‘1’)
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
32 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
11. Package outline
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
bp
ZE
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
e
UNIT A
A3
D(1) E(1)
eD
eE
HD
bp b1
max.
min.
4.57
4.19
mm
inches
0.81
0.66
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
0.51
0.25
3.05
0.53
0.33
0.180
0.02
0.165
0.01
0.12
0.021 0.032 0.656 0.656
0.05
0.013 0.026 0.650 0.650
0.63
0.59
0.63
0.59
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.695 0.695 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.685 0.685 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT187-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 18. Package outline SOT187-2 (PLCC44)
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
33 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT617-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
1/2 e
16
y
y1 C
v M C A B
w M C
b
9
L
17
8
e
e2
Eh
1/2 e
1
terminal 1
index area
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 19. Package outline SOT617-1 (HVQFN32)
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
34 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 20. Package outline SOT313-2 (LQFP48)
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
35 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4
1.70
1.14
0.53
0.38
0.36
0.23
52.5
51.5
inches
0.19
0.02
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.1
0.6
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT129-1
051G08
MO-015
SC-511-40
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 21. Package outline SOT129-1 (DIP40)
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
36 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
37 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 26 and 27
Table 26.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 27.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
38 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Soldering of through-hole mount packages
13.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
13.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
13.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
39 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
13.4 Package related soldering information
Table 28.
Suitability of through-hole mount IC packages for dipping and wave soldering
Package
Soldering method
Dipping
Wave
CPGA, HCPGA
-
suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL
suitable
suitable[1]
PMFP[2]
-
not suitable
[1]
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2]
For PMFP packages hot bar soldering or manual soldering is suitable.
14. Abbreviations
Table 29.
Abbreviations
Acronym
Description
CPU
Central Processing Unit
DLL
Divisor Latch LSB
DLM
Divisor Latch MSB
DMA
Direct Memory Access
FIFO
First In/First Out
ISDN
Integrated Service Digital Network
LSB
Least Significant Bit
MSB
Most Significant Bit
RHR
Receive Holding Register
THR
Transmit Holding Register
TTL
Transistor-Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
40 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
15. Revision history
Table 30.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SC16C2550B_5
20090112
Product data sheet
-
SC16C2550B_4
Modifications:
•
Section 2 “Features”:
bullet item changed from “5 V tolerant inputs” to “5 V tolerant on input
only pins” and added Footnote 1.
•
Figure 7 “Internal Loopback mode diagram”:
3rd
– at signals coming out of ‘modem control logic’ block, changed from “OP1A, OP2B” to
“OP1A, OP1B”
•
Table 23 “Limiting values”:
– symbol Vn split to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”
•
Table 24 “Static characteristics”:
– changed symbol/parameter from “VIL(CK), LOW-level clock input voltage” to “VIL(clk), clock
LOW-level input voltage”
– changed symbol/parameter from “VIH(CK), HIGH-level clock input voltage” to “VIH(clk), clock
HIGH-level input voltage”
– changed symbol/parameter from “ICL, clock leakage” to “IL(clk), clock leakage current”
•
•
Table 25 “Dynamic characteristics”: added Table note [4] and its reference at tRESET
updated soldering information
SC16C2550B_4
20070215
Product data sheet
-
SC16C2550B_3
SC16C2550B_3
20050926
Product data sheet
-
SC16C2550B-02
SC16C2550B-02
(9397 750 14449)
20041214
Product data
-
SC16C2550B-01
SC16C2550B-01
(9397 750 11982)
20050719
Product data
-
-
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
41 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
SC16C2550B_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 12 January 2009
42 of 43
SC16C2550B
NXP Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
18. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9
Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
Hardware/software and time-out interrupts. . . 11
Programmable baud rate generator . . . . . . . . 12
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13
Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13
Register descriptions . . . . . . . . . . . . . . . . . . . 15
Transmit Holding Register (THR) and Receive
Holding Register (RHR) . . . . . . . . . . . . . . . . . 15
7.2
Interrupt Enable Register (IER) . . . . . . . . . . . 16
7.2.1
IER versus Transmit/Receive FIFO interrupt
mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.2
IER versus Receive/Transmit FIFO polled
mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17
7.3
FIFO Control Register (FCR) . . . . . . . . . . . . . 17
7.3.1
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3.1.1
Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 17
7.3.1.2
Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 17
7.3.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.4
Interrupt Status Register (ISR) . . . . . . . . . . . . 19
7.5
Line Control Register (LCR) . . . . . . . . . . . . . . 20
7.6
Modem Control Register (MCR) . . . . . . . . . . . 21
7.7
Line Status Register (LSR) . . . . . . . . . . . . . . . 22
7.8
Modem Status Register (MSR). . . . . . . . . . . . 23
7.9
Scratchpad Register (SPR) . . . . . . . . . . . . . . 24
7.10
SC16C2550B external reset condition . . . . . . 24
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25
9
Static characteristics. . . . . . . . . . . . . . . . . . . . 25
10
Dynamic characteristics . . . . . . . . . . . . . . . . . 26
10.1
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 27
11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33
12
Soldering of SMD packages . . . . . . . . . . . . . . 37
12.1
Introduction to soldering . . . . . . . . . . . . . . . . . 37
12.2
Wave and reflow soldering . . . . . . . . . . . . . . . 37
12.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 37
12.4
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Soldering of through-hole mount packages .
Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soldering by dipping or by solder wave . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
39
39
39
40
40
41
42
42
42
42
42
42
43
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 January 2009
Document identifier: SC16C2550B_5
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