Freescale Semiconductor Technical Data Sheet Document Number: MC13237 Rev. 1.3, 9/12/2013 MC13234/MC13237 Low Cost SoC Remote Control Platform for the 2.4 GHz IEEE® 802.15.4 Standard 1 Introduction The MC13234/MC13237 is Freescale’s low cost System-on-Chip (SoC) solution for the IEEE® 802.15.4 Standard that incorporates a complete, low power, 2.4 GHz radio frequency transceiver with TX/RX switch, an 8-bit HCS08 CPU, and a functional set of MCU peripherals into a 48-pin LGA package. This product targets wireless RF remote control and other cost-sensitive applications ranging from home TV and entertainment systems to medical and supports all ZigBee node types. The MC13234/MC13237 is a highly integrated solution, with very low power consumption. The MC13234/MC13237 contains an RF transceiver that is an 802.15.4 Standard 2006 compliant radio that operates in the 2.4 GHz ISM frequency band. The transceiver includes a low noise amplifier, 1 mW nominal output power amplifier (PA), internal voltage controlled oscillator (VCO), integrated transmit/receive switch, on-board power supply regulation, 12-bit ADC and full spread-spectrum encoding and decoding. The on-chip CPU is based on the Freescale HCS08 family of microcontroller units (MCU). The onboard © Freescale Semiconductor, Inc., 2012, 2013. All rights reserved. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Integrated IEEE 802.15.4 Transceiver (radio and modem) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 HCS08 8-bit central processing unit (CPU) 11 5 System clocks . . . . . . . . . . . . . . . . . . . . . . . 12 6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 System and power management . . . . . . . . 12 8 MCU peripherals . . . . . . . . . . . . . . . . . . . . . . 14 9 Development Environment . . . . . . . . . . . . . 19 10Pin Assignment and Connections . . . . . . . 20 11Electrical Specifications . . . . . . . . . . . . . . . 26 12Applications Information . . . . . . . . . . . . . . . 42 13Mechanical Diagrams (Case 2124-02, Non-JEDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 46 MCU peripheral set has been defined to support the targeted applications. A dedicated DMA block transfers packet data between RAM and the transceiver to off-load the CPU and allow higher efficiency and increased performance. 1.1 Ordering information Table 1 provides ordering information to include RAM, flash, and feature detail differences associated with the MC1323x family of devices Table 1. Orderable parts details Operating Temp Range (TA.) Device 2 Package Memory Options MC13234CHT –40° to 85° C LGA-48 8 KB RAM, 128 KB flash MC13234CHTR2 –40° to 85° C LGA-48 Tape and Reel 8 KB RAM, 128 KB flash MC13237CHT –40° to 85° C LGA-48 8 KB RAM, 128 KB flash MC13237CHTR2 –40° to 85° C LGA-48 Tape and Reel 8 KB RAM, 128 KB flash Features This section provides a simplified block diagram and highlights the MC13234/MC13237 features. 2.1 Block diagram Figure 1 shows a simplified block diagram of the MC13234/MC13237. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 2 Freescale Semiconductor 32 MHz 32.768 KHz (Optional) RF Oscillator/PLL & Clock Generation Clock & Reset Module (CRM) Timer Module (4 Timers, Each w/1Ch) 12 x 12 12x12 Modem TX TX/RX Switch Analog RX IEEE® Modem RX 802.15.4 PHY Sequence Manager HCS08 Core SCI/UART Interface Bus Interface & Memory Arbitrator I2C Module 802.15.4 Transceiver Advanced Security Module Analog Pwr Management & Voltage Reg MC1323x Keyboard Interface CPU Complex Low Battery Interrupt Controller 82 KB 128/ 128 KB KB FLASH 8 KB 5 KB / 8 KB RAM 28 GPIO Up to 32 Balun Digital Modem Data & Address Buses e Analog TX SPI Interface CMT (IR) Module Debug Module 12-Bit ADC Module NOTE: MC13237 Rev 1.1 does not support SPI module. It is planned to be fixed in a future revision. The 12-Bit ADC module is available only in MC13237 and not available in MC13234. Figure 1. MC13234/MC13237 simplified block diagram 2.2 • • • Features summary Fully compliant IEEE 802.15.4 Standard 2006 transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode — 2.4 GHz — Operates on one of 16 selectable channels per IEEE 802.15.4 — Programmable output power with 0 dBm nominal output power, programmable from –30 dBm to +2 dBm typical — Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE 802.15.4 Standard requirement of –85 dBm — Partial power down (PPD_RX) Listen mode available to reduce current while in receive mode and waiting for an incoming frame Small RF footprint — Integrated transmit/receive switch — Differential input/output port (typically used with a balun) — Low external component count Hardware acceleration for IEEE® 802.15.4 applications — DMA interface MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 3 • • • • • • • • • • — AES-128 security module — 16-bit random number generator — 802.15.4 auto-sequence support — 802.15.4 receiver frame filtering 32 MHz crystal reference oscillator; onboard load trim capability supplements external load capacitors Onboard 1 kHz oscillator for wake-up timing or an optional 32.768 kHz crystal for accurate low power timing Transceiver event timer module has 4 timer comparators available to help manage the auto-sequencer and to supplement MCU TPM resources HCS08 8-bit, 32 MHz CPU Flash memory — 131072dec bytes organized as 128 segments by 1024 bytes — Programmable over the full power supply range of 1.8 V–3.6 V — Automated program and erase algorithms — Flexible protection scheme to prevent accidental program or erase — Security feature to prevent unauthorized access to the flash RAM — 8 KBytes of SRAM Powerful in-circuit debug and flash programming available via on-chip module (BDM) — Two comparator and 9 trigger modes — Eight deep FIFO for storing change-of-flow addresses and event-only data — Tag and force breakpoints — In-circuit debugging with single breakpoint Multiple low power modes (less than 1 A in Stop3) Keyboard interrupt (KBI) modules — MC13234 – Two keyboard control modules capable of supporting up to a 12 x 12 keyboard matrix – 12 dedicated KBI pins support a 6 x 6 matrix without impacting other IO resources – 12 KBI interrupts with selectable polarity — MC13237 – One keyboard control module capable of supporting up to a 8 x 8 keyboard matrix – 8 dedicated KBI pins support a 4 x 4 matrix without impacting other IO resources – 8 KBI interrupts with selectable polarity Serial communication interface (SCI) — Full duplex non-return to zero (NRZ) — Baud rates as high as 1 Mbps can be supported — LIN master extended break generation MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 4 Freescale Semiconductor • • • • • • • • • — LIN slave extended break detection — Wake-up on active edge Serial peripheral interface (SPI) — Full-duplex or single-wire bidirectional — Double-buffered transmit and receive — Master or slave mode; MSB-first or LSB-first shifting Inter-integrated circuit (IIC) interface — Up to 100 kbps baud rate with maximum bus loading — Baud rates as high as 800 kbps can be programmed — Multi-master operation — Programmable slave address — Interrupt driven byte-by-byte data transfer — Supports broadcast mode and 10-bit addressing Four 16-bit timer/pulse width modulators (TPM[4:1]) — each TPM module has an assigned GPIO pin and provides — Single channel capability — Input capture — Output compare — Buffered edge-aligned or center-aligned PWM 8-Channel, 12-bit resolution ADC (available only in MC13237) — 11.2 Effective Number of Bits (ENOB) — 2.5 s conversion time — Internal 1.7 mV/C temperature sensor — Internal bandgap reference — Operation in Stop3 — Fully functional from 1.8 V to 3.6 V Carrier modulator timer (CMT) — IR remote carrier generator, modulator, and transmitter. Real-time counter (RTC) — 16-bit modulus counter with binary or decimal based prescaler; — External clock source for precise time base, time-of-day, calendar or task scheduling functions — Capable of greater than one day interrupt. System protection features — Programmable low voltage warning and interrupt (LVI) — Optional watchdog timer (COP) — Illegal opcode detection 1.8 V to 3.6 V operating voltage with on-chip voltage regulators. Up to 32 GPIO MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 5 • • — MC13234: 32 GPIOs — MC13237: 28 GPIOs — Hysteresis and selectable pullup resistors on all input pins — Configurable slew rate and drive strength on all output pins –40°C to +85°C operating temperature range RoHS-compliant 7 x 7 mm 48-pin LGA package Table 2. MC13234 and MC13237 Comparison Feature MC13234 Radio MC13237 IEEE 802.15.4 compliant CPU 32 MHz HCS08 Flash memory RAM 8K BDM Yes Low power modes Yes KBI 2.3 128K Two (12 interrupts) One (8 interrupts) SCI Yes SPI Yes IIC Yes TPM Yes CMT Yes RTC Yes LVD Yes COP Yes ADC No Yes GPIO 32 28 Software solutions Freescale provides a powerful software environment called the Freescale BeeKit Wireless Connectivity Toolkit. BeeKit is a comprehensive codebase of wireless networking libraries, application templates, and sample applications. The BeeKit Graphical User Interface (GUI), part of the BeeKit Wireless Connectivity Toolkit, allows users to create, modify, and update various wireless networking implementations. A wide range of software functionality is available to complement the MC13234/MC13237 and these are provided as codebases within BeeKit. The following sections describe the available tools, however due to continuous updates that occur on FSL software inquiries to applications engineering is recommended. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 6 Freescale Semiconductor 2.3.1 Simple Media Access Controller (SMAC) The Freescale Simple Media Access Controller (SMAC) is a simple ANSI C based code stack available as sample source code. The SMAC can be used for developing proprietary RF transceiver applications using the MC13234/MC13237. • Supports point-to-point and star network configurations • Proprietary networks • Source code and application examples provided 2.3.2 IEEE® 802.15.4 2006 Standard-Compliant MAC The Freescale 802.15.4 Standard-Compliant MAC is a code stack available as object code. The 802.15.4 MAC can be used for developing MC13234/MC13237 networking applications based on the full IEEE® 802.15.4 Standard that use custom Network Layer and application software. • Supports star, mesh, and cluster tree topologies • Supports beaconed networks • Supports GTS for low latency • Multiple power saving modes • AES-128 security module • 802.15.4 sequence support • 802.15.4 receiver frame filtering. 2.3.3 SynkroRF platform The SynkroRF Network is a general purpose, proprietary networking layer that sits on top of the IEEE® 802.15.4 MAC and PHY layers. It is designed for wireless personal area networks (WPANs) and conveys information over short distances among the participants in the network. It enables small, power efficient, inexpensive solutions to be implemented for a wide range of applications. Some key characteristics of an SynkroRF network are: • An over-the-air data rate of 250 kbps in the 2.4 GHz band. • 3 independent communication channels in the 2.4 GHz band (15, 20, and 25). • 2 network node types, controller and controlled nodes. • Channel agility mechanism. • Low latency TX mode automatically enabled in conditions of radio interference. • Fragmented mode transmission and reception, automatically enabled in conditions of radio interference. • Robustness and ease of use. • Essential functionality to build and support a CE network. The SynkroRF network layer uses components from the standard HC(S)08 Freescale platform, which is also used by the Freescale’s implementations of 802.15.4. MAC and ZigBee™ layers. For more details about the platform components, see the Freescale Platform Reference Manual. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 7 2.3.4 BeeStack Consumer Freescale’s ZigBee RF4CE stack, called BeeStack Consumer, is a networking layer that sits on top of the IEEE® 802.15.4 MAC and PHY layers. It is designed for standards-based wireless personal area networks (WPANs) of home entertainment products and conveys information over short distances among the participants in the network. It enables small, power efficient, inexpensive solutions to be implemented for a wide range of applications. Targeted applications include DTV, set top box, A/V receivers, DVD players, security, and other consumer products. Some key characteristics of a BeeStack Consumer network are: • An over-the-air data rate of 250 kbps in the 2.4 GHz band • 3 independent communication channels in the 2.4 GHz band • 2 network node types, controller node and target node • Channel agility mechanism • Provides robustness and ease of use • Includes essential functionality to build and support a CE network The BeeStack Consumer layer uses components from the standard HCS08 Freescale platform, which is also used by the Freescale implementations of 802.15.4. MAC or ZigBee™ layers. For more details about the platform components, see the Freescale Platform Reference Manual. 2.3.5 ZigBee-Compliant Network Stack Freescale’s BeeStack architecture builds on the ZigBee protocol stack. Based on the OSI Seven-Layer model, the ZigBee stack ensures inter-operability among networked devices. The physical (PHY), media access control (MAC), and network (NWK) layers create the foundation for the application (APL) layers. BeeStack defines additional services to improve the communication between layers of the protocol stack. At the application layer, the application support layer (ASL) facilitates information exchange between the application support sub-layer (APS) and application objects. Finally, ZigBee Device Objects (ZDO), in addition to other manufacturer-designed applications, allow for a wide range of useful tasks applicable to home and industrial automation. BeeStack uses the IEEE 802.15.4-compliant MAC/PHY layer that is not part of ZigBee itself. The NWK layer defines routing, network creation and configuration, and device synchronization. The application framework (AF) supports a rich array of services that define ZigBee functionality. ZigBee Device Objects (ZDO) implement application-level services in all nodes via profiles. A security service provider (SSP) is available to the layers that use encryption (NWK and APS), i.e., Advanced Encryption Standard (AES) 128-bit security. The complete Freescale BeeStack protocol stack includes the following components: • ZigBee Device Objects (ZDO) and ZigBee Device Profile (ZDP) • Application support sub-layer (APS) • Application framework (AF) • Network (NWK) layer • Security service provider (SSP) • IEEE 802.15.4-compliant MAC and Physical (PHY) layer MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 8 Freescale Semiconductor 3 Integrated IEEE 802.15.4 Transceiver (radio and modem) The MC13234/MC13237 is a IEEE® 802.15.4 fully-compliant transceiver providing a complete 2.4 GHz radio solution with 250 kbps offset-quadrature phase shift keying (O-QPSK) data in 5.0 MHz channel spacings with full spread-spectrum encode and decode. The modem supports the full requirement of the IEEE® 802.15.4 Standard functionality to transmit, receive, and do clear channel assessment (CCA), energy detect (ED), and link quality indication (LQI). Some top level transceiver features supported are listed below: • Programmable output power with 0 dBm nominal output power, programmable from –30 dBm to +2 dBm typical • Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet • Differential bidirectional RF input/output port • Integrated transmit/receive switch • Receive current can be reduced while waiting or listening for an incoming frame using partial power down (PPD) mode1 (see Table 11) 3.1 RF interface and usage The MC13234/MC13237 RF interface provides a bidirectional, differential port that connects directly to a balun. The balun connects directly to a single-ended antenna and converts that interface to a full differential, bidirectional, on-chip interface with transmit/receive switch, LNA, and complementary PA outputs. This combination allows for a small footprint and low cost RF solution to be realized. 3.2 Transceiver register interface and operation The transceiver is controlled by set of interface registers that are memory-mapped into the CPU address space. MC13234/MC13237 supports independent transmit, receive, or CCA/ED (energy detection) modes of operation and combinations. Additional features of the transceiver include: • DMA function that moves data directly between RAM and transceiver buffers during diplexed transmit and receive operation on a cycle-steal basis. This feature offloads the data transfer from the CPU, thus providing higher performance. • Interrupt capability that is dependent on RX packet data availability. An interrupt can be generated based on a programmed count of RX data bytes that have been received and moved to RAM. This allows CPU filtering of RX data before completion of the packet reception to accelerate response to the packet. • Four (4) transceiver event timer comparators to supplement MCU peripheral timer resources for PHY and MAC timing requirements. 3.3 IEEE 802.15.4 acceleration hardware MC13234/MC13237 transceiver has several hardware features to reduce the software stack size, offload the function from the CPU, and improve performance. A list of features supported is provided below: MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 9 • • • • • • • • 3.4 2003 & 2006 versions of the IEEE® 802.15.4 standard is full supported. Slotted and unslotted modes Beacon enabled and non-beacon enabled networks DMA data transfer between RAM and radio Separate AES-128 security module 16-bit random number generator 802.15.4 sequence support — RX (conditionally followed by TXAck) — TX — CCA (used for CCA and ED cycles) — TX/RX (TX followed by unconditional RX or RCACK) — Continuous CCA 802.15.4 receiver frame filtering Partial Power Down Receive mode (PPD_RX) The MC13234/MC13237 provides a unique Partial Power Down Receive (PPD_RX) mode. A summary of PPD_RX mode of operation when selected is described below: • Whenever a receive cycle is initiated, the receiver is not turned fully on to save current until receive energy of a preset level is detected • The receiver will turn fully on only when triggered by energy at a pre-determined preset level thus enabling reception of the expected frame. Afterwards, the receiver will begin operating in the full-on state that is considered to be the same as the standard receive state • The preset level can be programmed for various RX input power levels Use of the PPD_RX mode provides two distinct advantages: • Reduced “Listen” mode current — The receive current is significantly reduced while waiting for a frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its RF-active time waiting for incoming frames from clients or other devices, the net power savings can be significant. • Reduced sensitivity as a desired effect — The PPD_RX mode provides different levels of reduced sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the receiver such that the device does not respond to incoming frames with an energy level below the desired threshold. This could be useful for security, net efficiency, reduced noise triggering, and many other purposes. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 10 Freescale Semiconductor 4 HCS08 8-bit central processing unit (CPU) The onboard CPU is a 32 MHz 8-bit HCS08 core. It executes a super set of the 68HC08 instruction set with added BGND instructions. The HCS08 CPU is fully source and object code compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes are added to improve C compiler efficiency and to support a new background debug system. It has an 8-bit data bus, a 16-bit address bus, and a 2-stage instruction pipe that facilitates the overlapping of instruction fetching and execution. There are 29 vectors for internal interrupt sources and one vector for an external interrupt pin. The debug or BDM module provides a serial one-wire interface for non-intrusive debugging of application programs. Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • 64-KB CPU address space with banked memory management unit for greater than 64 KB • 16-bit stack pointer (any size stack anywhere in 64-KB CPU address space) • 16-bit index register (H:X) with powerful indexed addressing modes • 8-bit accumulator (A) • Many instructions treat X as a second general-purpose 8-bit register • Seven addressing modes: — Inherent — Operands in internal registers — Relative — 8-bit signed offset to branch destination — Immediate — Operand in next object code byte(s) — Direct — Operand in memory at 0x0000–0x00FF — Extended — Operand anywhere in 64-KB address space — Indexed relative to H:X — Five submodes including auto increment — Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 11 5 System clocks The primary system reference frequency is a 32 MHz crystal oscillator. The crystal requirements for the oscillator and oscillator performance must support a +/–40 ppm frequency accuracy to meet the IEEE® 802.15.4 Standard requirements. All system clocks are generated from this source. Features of the clock system include: • The 32 MHz reference oscillator has onboard programmable capacitive loading that allows software tuning of frequency accuracy • CPU clock as high as 32 MHz • Bus clock (and peripheral clock) equals 1/2 CPU clock • Clocks to individual peripherals can be independently disabled for best power management • CPU clock can be lowered to 500 kHz for lower power (250 kHz bus clock) An optional 32.768 kHz crystal oscillator is available for accurate low power timing and the real time clock (RTC). Also, an onboard, low accuracy 1 kHz oscillator is available for sleep timing wake-up. 6 Memory The MC13234/MC13237 memory resources consist of RAM, Flash program memory for nonvolatile data storage, control/status registers for I/O, peripherals, management, and the transceiver. Features include: • 128 Kbyte flash • 8 Kbyte SRAM • Security circuitry to prevent unauthorized access to RAM and flash contents 7 System and power management MC13234/MC13237 is a low power device that also supports extensive system control and power management modes to maximize battery life and provide system protection. 7.1 Modes of operation The MC13234/MC13237 modes of operation include: • • Active background mode for code development Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 12 Freescale Semiconductor • • • • LPRun mode — CPU clock is set to 500 kHz and peripheral clocks (bus clock) to 250 kHz and the internal voltage regulators are in standby Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation is maintained LPWait mode — CPU shuts down to conserve power; peripheral clocks are restricted to 250 kHz and the internal voltage regulator is in standby Stop modes — System clocks are stopped and voltage regulator is in standby — Stop3 — All internal circuits are powered for fast recovery (32 MHz oscillator on-off optional) NOTE: See Table 9 for further details on modes of operation 7.2 Power management The MC13234/MC13237 power management is controlled through programming of the modes of operation. Different modes allow for different levels of power-down. Additional features include: • The transceiver is powered as required • The analog radio is only powered-up as required to do a TX, RX, or CCA/ED operation • Peripheral control clock gating can be disabled on an MCU module-by-module basis to provide lowest power • Programmed mode manages — Degree of chip power down — Retention of programmed parameters — Clock management • Power-down and wake-up (clocks and analog blocks) are gracefully controlled • RTC can be used as wake-up timer • Wake-up available through KBI and UART RX asynchronous interrupts • Real-time counter (RTC) module — 16-bit modulus counter with binary or decimal based prescaler for precise time base, time-of-day, calendar or task scheduling functions — Capable of greater than one day interrupt — Can also be used for device wake-up 7.3 System protection The MC13234/MC13237 provides several vehicles to maintain security or a high level of system robustness: • Watchdog computer operating properly (COP) reset with option to run from dedicated internal clock source or bus clock • Low-voltage warning and detection with reset or interrupt; selectable trip points • Illegal opcode detection with reset • Flash block protection MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 13 8 MCU peripherals The MC13234/MC13237 has a functional set of MCU peripherals focused for intended applications. For further information on application use-cases please refer to the Reference Manual. 8.1 Parallel input/output (GPIO) MC13234 and MC13237 have 32 and 28 general purpose I/O signals, respectively. These GPIO signals are distributed among four I/O ports (PTA, PTB, PTC, and PTD). Many of these pins are shared with on-chip peripherals such as timer systems, communication ports, or keyboard interrupts. When these other modules are not controlling the port pins, they revert to general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output (write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal pullup device (provided the pin is configured as an input), and a slew rate control bit controls the rise and fall times of the pins. Parallel I/O features include: • A total of 32 or 28 general-purpose I/O pins in four ports (PTA2 is output only) • Hysteresis input buffers • Software-controlled pullups on each input pin • Software-controlled slew rate output buffers 8.2 Keyboard interrupt modules (KBI) MC13234 has two (2) KBI modules; KBI1 shares eight (8) port B pins and KBI2 shares four (4) port C pins. MC13237 has one (1) KBI module; KBI1 shares eight (8) port B pins. Any KBI pin can be enabled as a keyboard input that can act as an interrupt request. As a result, the total 12 KBI inputs (MC13234) allows as large as a 12x12 keyboard matrix. The total 8 KBI inputs (MC13237) allows as large as a 8x8 keyboard matrix with use of other GPIO pins as outputs to the matrix. All enabled KBI inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. They also can be configured for either rising edge / high-level or falling-edge/low-level sensitivity. When enabled for rising edge / high level sensitivity, a pulldown resistor is enabled, and when enabled for falling edge / low level sensitivity, a pullup resistor is enabled. The KBI features include: • KBI1 has eight (8) keyboard interrupt pins with individual pin enable bits. • KBI2 (available only in MC13234) has four (4) keyboard interrupt pins with individual pin enable bits. • Supports up to a 12x12 (MC13234) or 8x8 (MC13237) keyboard matrix. An 8x8 matrix (MC13234) or 4x4 (MC13237) matrix can be supported without impacting other I/O functions. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. pullups and pulldowns enabled by selected mode. • Individual signal software enabled interrupts for KBI1 and KBI2. • Can be used for device wake-up MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 14 Freescale Semiconductor 8.3 Serial communications interface (SCI) module The MC13234/MC13237 has one serial communications interface module — sometimes called a universal asynchronous receiver/transmitter (UART). Typically, this port is used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, and it can also be used to communicate with other embedded controllers. The SCI module has a single, flexible frac-N (13-bit modulo counter, 5-bit fractional counter) baud rate generator used both for transmit and receive. With a maximum 16 MHz peripheral clock, baud rates as high as 1 Mbps can be supported (standard is 921,600 baud). This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wake-up, and double buffering on transmit and receive are also included. Features of SCI module include: • Dedicated TXD and RXD pins • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable high accuracy baud rates (frac-N generator) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wake-up by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 8.4 Serial peripheral interface (SPI) module The MC13234/MC13237 has one serial peripheral interface module. The SPI is a synchronous serial data input/output port used for interfacing with serial memories, peripheral devices, or other processors. The SPI allows an 8-bit serial bit stream to be shifted simultaneously into and out of the device at a programmed bit-transfer rate (called 4-wire mode). There are four (4) pins associated with the SPI port (SPICLK, MOSI, MISO, and SS). MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 15 The SPI module can be programmed for master or slave operation. It also supports a 3-wire mode where for master mode the MOSI becomes MOMI, a bidirectional data pin, and for slave mode the MISO becomes SISO, a bidirectional data pin. In 3-wire mode, data is transferred in only one direction at a time. The SPI bit clock is derived from the peripheral input clock with a maximum 16 MHz operation. A programmable prescaler (maximum divide-by-8) drives a second baud rate programmable divider (maximum divide-by-256) to develop the bit clock. The maximum SPI transfer rate is 8 MHz. Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • 8-bit only transfer size • Programmable transmit bit rate (8 MHz max) • Double-buffered transmit and receive • Serial clock phase and polarity options (supports all 4 options) • Optional slave select output • Selectable MSB-first or LSB-first shifting 8.5 Inter-integrated circuit (IIC) interface module The MC13234/MC13237 has one inter-integrated circuit interface module that provides a method of communication between a number of other integrated circuits. The IIC Bus interface provides a bidirectional, 2-pin (SDA bus data and SCL bus clock) serial bus designed to operate up to 100 kbps with maximum bus loading and timing. The module is capable of operating at higher baud rates, up to a maximum of peripheral clock/20 (800 kbps), with reduced bus loading. Features of IIC module include: • Compatible with IIC bus standard • Multi-master operation • Software programmable clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus busy detection • General call recognition • 10-bit address extension MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 16 Freescale Semiconductor 8.6 Timer/PWM (TPM) modules The MC13234/MC13237 has four (4) independent timer/PWM modules, each with one channel. Each TPM module is based on a 16-bit counter and provides input capture, output compare, and Pulse Width Modulation (PWM). Each TPM module has one associated I/O pin for input capture or counter/PWM output. TPM module features include: • Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels • Module clock source is peripheral clock or reference oscillator divided-by-1024 • Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Module enable • One interrupt per channel plus a terminal count interrupt for each TPM module • Channel features: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 8.7 Carrier Modulator Timer (CMT) Module The MC13234/MC13237 Carrier Modulator Timer module is intended as an IR LED driver for remote control “blaster” applications. The module consists of a carrier generator, modulator, and transmitter that drives data to package pin # 31 (PTD4/CMT/AD3) either in baseband or in FSK mode. The CMT.../IRO pin drives (modulates) the IR diode directly or through a buffer depending on the applications current requirement. The current drive capability of this pin is specified for 20mA. The CMT module features include: • Four (4) modes of operation: — Time with independent control of high and low times — Baseband — Frequency Shift Key (FSK) — Direct software control of CMT....IRO pin • Extended space operation in time, baseband, and FSK modes • Module clock source is peripheral clock (16 MHz max) • Interrupt on end of cycle • Ability to disable CMT...IRO pin and use as timer interrupt MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 17 8.8 Real Time Counter (RTC) Module The MC13234/MC13237 Real Time Counter module consists of one(1) 16-bit counter, one(1) 16-bit comparator, several binary-based and decimal-based prescaler dividers, three (3) clock sources, and one(1) programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake-up from low power modes (Stop2, Stop3, and Wait). RTC can be clocked from bus clock, the optional 32.768 kHz oscillator or the onboard 1 kHz low power oscillator. Features of the RTC module include: • 16-bit up-counter — 16-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with programmable 16 bit prescaler — 32.768 kHz optional crystal oscillator. — 32 MHz reference oscillator — 1 kHz low power RC oscillator • Useful for time base tick or time-of-day clock • Can be used for device wake-up; capable of greater than one day time-out period. 8.9 12-Bit Analog-to-Digital Conversion (ADC) Module The MC13237 integrates an 8 channel, 12-bit resolution Successive Approximation Register (SAR) analog-to-digital conversion (ADC) module. The analog input channels are shared/multiplexed with standard GPIO pins as shown in Figure 3. The ADC module is available in MC13237 only; not available in MC13234. Features of the ADC module include: • 11.2 Effective Number of Bits (ENOB) • Linear successive approximation algorithm with 12-bits resolution • Operation in Stop3 mode • 2.5 s conversion time • Internal bandgap reference • Operation over full VBATT voltage range • Internal 1.7 mV/°C temperature sensor • Output data can be formatted in 8-, 10-, or 12-bit justified format • Single or continuous conversion • Configurable sample time and conversion speed / power. • Auto compare for less-than, greater than, or equal to programmable value • Converter subsystem shut-down MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 18 Freescale Semiconductor 9 Development Environment Development support for the HCS08 on the MC13234/MC13237 includes the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire (signal BKGD) debug interface to the MCU that provides a convenient interface for programming the on-chip flash and other storage. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. Address and data bus signals are not available on external pins. Debug is done through commands fed into the MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. Features include: • Single-wire background debug interface • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) • On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. • Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 19 10 Pin Assignment and Connections RF_P RF_N NC VDD_ANA VREG_VCO 48 47 46 45 44 43 42 41 40 39 38 PTA1/EXTAL_32K 2 RESET 3 PTA2 4 PTA3/IRQ 5 PTA4/XTAL_32KOUT 6 PTA5/SDA 7 PTA6/SCL 8 PTA7/BKGD/MS VBATT_3 VBATT_2 1 RF_BIAS NC PTA0/XTAL_32K VREG_ANA VREG_LO2 Device Pin Assignments VBATT_1 37 36 EXTAL_32M 35 XTAL_32M 34 PTD7 33 PTD6/RXD 32 PTD5/TXD 31 PTD4/CMT 30 PTD3/TPM3 29 PTD2/TPM2 9 28 PTD1/TPM1 PTB0/KBI1P0 10 27 PTD0/TPM0 PTB1/KBI1P1 11 26 PTC7/MOSI PTB2/KBI1P2 12 25 24 PTC6/MISO 22 23 PTC1/KBI2P1 PTC2/KBI2P2 PTC3/KBI2P3 PTC4/SPICLK PTC5/SS 21 VBATT_4 20 PTC0/KBI2P0 PTB6/KBIP6 17 18 19 PTB7/KBIP7 16 PTB3/KBIP3 13 14 15 PTB4/KBIP4 MC13234CHT PTB5/KBIP5 10.1 Figure 2. MC13234 Pinout MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 20 Freescale Semiconductor 5 PTA4/XTAL_32KOUT 6 PTA5/SDA 7 PTA6/SCL 8 PTA7/BKGD/MS 45 44 43 42 41 40 39 38 VBATT_3 47 46 RF_BIAS VREG_VCO PTA3/IRQ VDD_ANA 4 NC PTA2 RF_N 3 RF_P RESET VBATT_2 2 NC PTA1/EXTAL_32K 48 VREG_LO2 1 VREG_ANA VBATT_1 PTA0/XTAL_32K 37 36 EXTAL_32M 35 XTAL_32M 34 PTD7/AD6 33 PTD6/RXD/AD5 32 PTD5/TXD/AD4 31 PTD4/CMT/AD3 30 PTD3/TPM3/AD2 29 PTD2/TPM2/AD1 9 28 PTD1/TPM1/AD0 PTB0/KBI1P0 10 27 PTD0/TPM0 PTB1/KBI1P1 11 26 PTC7/MOSI PTB2/KBI1P2 12 25 24 PTC6/MISO 21 22 23 VBATT_4 VSSA_ADC VREFL VREFH VDDA_ADC PTC4/SPICLK 20 PTC5/SS/AD7 17 18 19 PTB7/KBIP7 PTB6/KBIP6 PTB5/KBIP5 16 PTB4/KBIP4 13 14 15 PTB3/KBIP3 MC13237CHT Figure 3. MC13237 Pinout MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 21 10.2 Pin Definitions Table 4 details the MC13234 pinout and functionality. Table 3. MC13234 Pin Function Description Pin # Pin Name Type Description Functionality 1 PTA0/XTAL_32K Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator output 2 PTA1/EXTAL_32K Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator input For normal use, 10 kOhm resistor to ground recommended 3 RESET Digital Input/Output Device asynchronous hardware reset. Active low. Onboard Pullup Normally input; gets driven low for a period after a reset 4 PTA2 Digital Output Port A Bit 2 / Test Mode enable. TM mode input. Must be biased low exiting POR for normal operation 5 PTA3/IRQ Digital Input/Output Port A Bit 3 / IRQ. 6 PTA4/ XTAL_32KOUT Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz clock Optional 32.768 kHz output clock output for measuring 32 kHz oscillator accuracy (ppm) 7 PTA5/SDA Digital Input/Output Port A Bit 5 / IIC Bus data Defaults to open drain for IIC 8 PTA6/SCL Digital Input/Output Port A Bit 6 / IIC Bus clock Defaults to open drain for IIC 9 PTA7/BKGD/MS Digital Input/Output Port A Bit 7 / Background / Mode Select Debug signal 10 PTB0/KBI1P0 Digital Input/Output Port B Bit 0 / KBI1 Input Bit 0 Wake-up capability 11 PTB1/KBI1P1 Digital Input/Output Port B Bit 1 / KBI1 Input Bit 1 Wake-up capability 12 PTB2/KBI1P2 Digital Input/Output Port B Bit 2 / KBI1 Input Bit 2 Wake-up capability 13 PTB3/KBI1P3 Digital Input/Output Port B Bit 3 / KBI1 Input Bit 3 Wake-up capability 14 PTB4/KBI1P4 Digital Input/Output Port B Bit 4 / KBI1 Input Bit 4 Wake-up capability 15 PTB5/KBI1P5 Digital Input/Output Port B Bit 5 / KBI1 Input Bit 5 Wake-up capability 16 PTB6/KBI1P6 Digital Input/Output Port B Bit 6 / KBI1 Input Bit 6 Wake-up capability 17 PTB7/KBI1P7 Digital Input/Output Port B Bit 7 / KBI1 Input Bit 7 Wake-up capability 18 PTC0/KBI2P0 Digital Input/Output Port C Bit 0 / KBI2 Input Bit 0 19 VBATT_4 Power Input VDD supply input 1 20 PTC1/KBI2P1 Digital Input/Output Pot C Bit 1 / KBI2 Input Bit 1 21 PTC2/KBI2P2 Digital Input/Output Pot C Bit 2 / KBI2 Input Bit 2 22 PTC3/KBI2P3 Digital Input/Output Pot C Bit 3 / KBI2 Input Bit 3 23 PTC4/SPICLK Digital Input/Output Port C Bit 4 / SPI clock 24 PTC5/SS Digital Input/Output Port C Bit 5 / SPI slave select 25 PTC6/MISO Digital Input/Output Port C Bit 6 / SPI MISO 26 PTC7/MOSI/32M_OUT Digital Input/Output Connect to system VDD supply Port C Bit 7 / SPI MOSI / 32 MHz XTAL output MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 22 Freescale Semiconductor Table 3. MC13234 Pin Function Description (continued) Pin # Pin Name Description Functionality 27 PTD0/TPM0 Digital Input/Output Port D Bit 0 / TPM0 signal TPM0 timer output / gate input signal 28 PTD1/TPM1 Digital Input/Output Port D Bit 1/ TPM1 signal TPM1 timer output / gate input signal. 29 PTD2/TPM2 Digital Input/Output Port D Bit 2 / TPM2 signal TPM2 timer output / gate input signal. 30 PTD3/TPM3 Digital Input/Output Port D Bit 3 / TPM3 signal TPM3 timer output / gate input signal. 31 PTD4/CMT Digital Input/Output Port D Bit 4 / CMT output Hi drive output for IR diode. 32 PTD5/TXD Digital Input/Output Port D Bit 5 / UART TXD output UART has no hardware flow control. 33 PTD6/RXD Digital Input/Output Port D Bit 6 / UART RXD input / AD5 signal UART has no hardware flow control. 34 PTD7 Digital Input/Output Port D Bit 7 35 XTAL_32M Analog Output 32 MHz reference oscillator output 36 EXTAL_32M Analog input 32 MHz reference oscillator input 37 VBATT_3 Power Input VDD supply input1 38 VREG_VCO VCO Reg Out / in VCO regulator output and input to VCO Bypass to ground with 220 nF 1.8 Vdc VDD capacitor. 39 VDD_ANA Analog Power Input Analog 1.8 Vdc Input 40 NC 41 RF_N 42 43 Connect to system VDD supply Connect to VREG_ANA No connection to device May be left open or connect to ground RF Input/Output Modem RF input/output negative Bi-directional RF port for the internal LNA and PA RF_P RF Input/Output Modem RF input/output positive Bi-directional RF port for the internal LNA and PA RF_BIAS RF Voltage Output Switched RF bias voltage (1.8 Vdc) High for TX; low for RX Power Input 1 VDD supply input Connect to system VDD supply 44 VBATT_2 45 NC 46 VREG_LO2 LO2 Reg Out LO2 regulator output @ 1.8 Vdc Bypass to ground with 220 nF capacitor. 47 VREG_ANA ANA Reg Out Analog regulator output @ 1.8 Vdc Bypass to ground with 220 nF capacitor. Connect to VDD_ANA 48 VBATT_1 Power Input VDD supply to Analog regulator1 Connect to system VDD supply Power Input System ground Flag GND 1 Type May be left open or connect to ground VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13234/MC13237. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 23 Table 4 details the MC13237 pinout and functionality. Table 4. MC13237 Pin Function Description Pin # Pin Name Type Description Functionality 1 PTA0/XTAL_32K Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator output 2 PTA1/EXTAL_32K Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator input 3 RESET Digital Input/Output Device asynchronous hardware reset. Normally input; gets driven low for Active low. Onboard Pullup a period after a reset 4 PTA2 Digital Output Port A Bit 2 / Test Mode enable. 5 PTA3/IRQ Digital Input/Output Port A Bit 3 / IRQ. 6 PTA4/ XTAL_32KOUT Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz clock output Optional 32.768 kHz output clock for measuring 32 kHz oscillator accuracy (ppm) 7 PTA5/SDA Digital Input/Output Port A Bit 5 / IIC Bus data Defaults to open drain for IIC 8 PTA6/SCL Digital Input/Output Port A Bit 6 / IIC Bus clock Defaults to open drain for IIC 9 PTA7/BKGD/MS Digital Input/Output Port A Bit 7 / Background / Mode Select Debug signal 10 PTB0/KBI1P0 Digital Input/Output Port B Bit 0 / KBI1 Input Bit 0 Wake-up capability 11 PTB1/KBI1P1 Digital Input/Output Port B Bit 1 / KBI1 Input Bit 1 Wake-up capability 12 PTB2/KBI1P2 Digital Input/Output Port B Bit 2 / KBI1 Input Bit 2 Wake-up capability 13 PTB3/KBI1P3 Digital Input/Output Port B Bit 3 / KBI1 Input Bit 3 Wake-up capability 14 PTB4/KBI1P4 Digital Input/Output Port B Bit 4 / KBI1 Input Bit 4 Wake-up capability 15 PTB5/KBI1P5 Digital Input/Output Port B Bit 5 / KBI1 Input Bit 5 Wake-up capability 16 PTB6/KBI1P6 Digital Input/Output Port B Bit 6 / KBI1 Input Bit 6 Wake-up capability 17 PTB7/KBI1P7 Digital Input/Output Port B Bit 7 / KBI1 Input Bit 7 Wake-up capability 18 PTC5/SS/AD7 Digital Input/Output Port C Bit 5 / SPI Slave Select / AD7 Signal 19 VBATT_4 Power Input VDD supply input 1 20 VSSA_ADC Digital Input/Output ADC analog ground 21 VREFL Digital Input/Output ADC low reference voltage 22 VREFH Digital Input/Output ADC high reference voltage 23 VDDA_ADC Digital Input/Output ADC analog power supply 24 PTC4/SPICLK Digital Input/Output Port C Bit 4 / SPI Clock 25 PTC6/MISO Digital Input/Output Port C Bit 6 / SPI MISO 26 PTC7/MOSI Digital Input/Output Port C Bit 7 / SPI MOSI 27 PTD0/TPM0 Digital Input/Output Port D Bit 0 / TPM0 signal For normal use, 10 kOhm resistor to ground recommended TM mode input. Must be biased low exiting POR for normal operation Connect to system VDD supply TPM0 timer output / gate input signal MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 24 Freescale Semiconductor Table 4. MC13237 Pin Function Description (continued) Pin # Pin Name Description Functionality 28 PTD1/TPM1/AD0 Digital Input/Output Port D Bit 1/ TPM1 signal /AD0 signal TPM1 timer output / gate input signal. ADC input 0 29 PTD2/TPM2/AD1 Digital Input/Output Port D Bit 2 / TPM2 signal /AD1 signal TPM2 timer output / gate input signal. ADC input 1 30 PTD3/TPM3/AD2 Digital Input/Output Port D Bit 3 / TPM3 signal /AD2 signal TPM3 timer output / gate input signal. ADC input 2 31 PTD4/CMT/AD3 Digital Input/Output Port D Bit 4/ CMT output / AD3 signal 32 PTD5/TXD/AD4 Digital Input/Output Port D Bit 5 / UART TXD output / AD4 UART has no hardware flow signal control. ADC input 4 33 PTD6/RXD/AD5 Digital Input/Output Port D Bit 6 / UART RXD input / AD5 signal UART has no hardware flow control. ADC input 5 34 PTD7/AD6 Digital Input/Output Port D Bit 7 / AD6 signal ADC input 6 35 XTAL_32M Analog Output 32 MHz reference oscillator output 36 EXTAL_32M Analog input 32 MHz reference oscillator input 37 VBATT_3 Power Input VDD supply input1 Connect to system VDD supply 38 VREG_VCO VCO Reg Out / in VCO regulator output and input to VCO 1.8 Vdc VDD Bypass to ground with 220 nF capacitor. 39 VDD_ANA Analog Power Input Analog 1.8 Vdc Input 40 NC 41 RF_N 42 Hi drive output for IR diode. ADC input 3 Connect to VREG_ANA No connection to device May be left open or connect to ground RF Input/Output Modem RF input/output negative Bi-directional RF port for the internal LNA and PA RF_P RF Input/Output Modem RF input/output positive Bi-directional RF port for the internal LNA and PA 43 RF_BIAS RF Voltage Output Switched RF bias voltage (1.8 Vdc) High for TX; low for RX 44 VBATT_2 Power Input VDD supply input1 Connect to system VDD supply 45 NC Input No connection to device May be left open or connect to ground 46 VREG_LO2 LO2 Reg Out LO2 regulator output @ 1.8 Vdc Bypass to ground with 220 nF capacitor. 47 VREG_ANA ANA Reg Out Analog regulator output @ 1.8 Vdc Bypass to ground with 220 nF capacitor. Connect to VDD_ANA 48 VBATT_1 Power Input VDD supply to Analog regulator1 Connect to system VDD supply Power Input System ground Flag GND 1 Type VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13234/MC13237. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 25 11 Electrical Specifications This section details maximum ratings for the 48-pin LGA package, recommended operating conditions, DC characteristics, and AC characteristics. 11.1 Package Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maximum rating is not guaranteed. Stress beyond the limits specified in Table 5 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VBATT) or the programmable pullup resistor associated with the pin is enabled. Table 5 shows the maximum ratings for the 48-Pin LGA package. Table 5. LGA Package Maximum Ratings Rating Symbol Value Unit Maximum Junction Temperature TJ 125 C Storage Temperature Range Tstg 125 C Moisture Sensitivity Level MSL3-260 260 C VBATT –0.3 to 3.7 Vdc Vin –0.3 to (VDD + 0.3) Vdc Pmax 10 dBm Reflow Soldering Temperature Power Supply Voltage Digital Input Voltage RF Input Power Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: All pins meets ESD Human Body Model (HBM) = 2 kV 11.2 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with the JESD22 Stress Test Qualification for Commercial Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). All latchup test testing is in conformity with the JESD78 IC Latch-Up Test. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 26 Freescale Semiconductor A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Table 6. ESD and Latch-up Test Conditions1 Model Description Symbol Value Unit R1 1500 C 100 pF — 1 Series resistance R1 0 Storage capacitance C 200 pF Number of pulses per pin2 — 1 Series resistance Human Body Storage capacitance Number of pulses per Machine pin2 Minimum input voltage limit – 1.8 V Maximum input voltage limit 4.32 V Latch-up 1 2 There is no equivalent circuit (model) for CDM per JESD22-C101-A. This number represents a minimum number for both positive pulse(s) and negative pulse(s) Table 7. ESD and Latch-Up Protection Characteristics Rating1,2 No. Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 — V 2 Machine model (MM) VMM 200 — V 3 Charge device model (CDM) VCDM 750 — V 4 Latch-up current at TA = 85C ILAT 100 — mA 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 2 All package pins including RF pins. 11.3 Recommended Operating Conditions NOTE The MC13234/MC13237 transceiver provides an IEEE® 802.15.4 Standard PHY compliant node over all recommended operating conditions. Table 8. Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit VBATT 1.81 2.7 3.6 Vdc Input Frequency fin 2.405 — 2.480 GHz Operating Temperature Range TA –40 25 85 C Logic Input Voltage Low VIL 0 — 30% VBATT V Power Supply Voltage (VBATT) MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 27 Table 8. Recommended Operating Conditions (continued) Characteristic Symbol Min Typ Max Unit Logic Input Voltage High VIH 70% VBATT — VBATT V Output Load Current (with specified VOLmax and VOHmin) All standard GPIO CMT output IRO IO — — — — 3 20 mA Pmax — — 10 dBm RF Input Power Crystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 Standard.) 1 fref 32 MHz Only Although the device functions at VDDmin, the supply must first rise above VLVDL. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. 11.4 DC Electrical Characteristics Table 9. DC Electrical Characteristics1 (Typical conditions: VBATT = 2.7 V, TA = 25 °C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit VDD 1.82 2.7 3.6 Vdc VDD_RUN 1.6 ADC Voltage Reference High VREFH 1.8 ADC Voltage Reference Low VREFL Power Supply Voltage (voltage applied to power input pins; VBATT_1, VBATT_2, VBATT_3, VBATT_4 and VDDA_ADC) Minimum CPU RUN voltage (Radio and peripherals not guaranteed operational; CPU, RAM, and Flash operational) Vdc 2.7 VDDA_ ADC VSSA_ ADC Vdc Vdc VRAM VPOR VLVDH 2.18 2.20 2.23 2.26 2.32 2.32 Vdc Low-voltage detection threshold - low range (all conditions) VDD falling VDD rising VLVDL 1.67 1.68 1.70 1.77 1.80 1.96 Vdc Low-voltage warning threshold - high range (all conditions) VDD falling VDD rising VLVWH 2.25 2.30 2.32 2.36 2.45 2.42 Vdc Low-voltage warning threshold - low range (all conditions) VDD falling VDD rising VLVWL 1.79 1.74 1.81 1.84 1.91 1.99 Vdc Power-on reset (POR) voltage VPOR — 1.0 — Vdc |IOZ| –1.0 — 1.0 Minimum RAM retention voltage (voltage applied to VBATT power input pins) Low-voltage detection threshold - high range (all Vdc conditions3) VDD falling VDD rising High impedance (off-state) leakage current (per pin) (VIn = VDD or VSS, all input/outputs, device must not be in low power mode) A MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 28 Freescale Semiconductor Table 9. DC Electrical Characteristics1 (continued) (Typical conditions: VBATT = 2.7 V, TA = 25 °C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Input Current (VIN = 0 V or VDDINT) (VIn = VDD or VSS, all input/outputs, device must not be in low power mode) IIN –1.0 — +1.0 µA Input Low Voltage (All digital inputs) VIL 0 — 30% VBATT V Input High Voltage (all digital inputs) VIH 70% VBATT — VBATT V Input hysteresis (all digital inputs) Vhys 0.06 VDD Internal pull up resistors4 (all port pins and IRQ except CMT) RPU — 20 — Internal CMT pull up resistor4 RPU — 10 — Internal pull down (KBI pins and IRQ) RPD — 20 — Output High Voltage All standard GPIO = 3 mA CMT output IRO = 20 mA VOH 80% VBATT — VBATT V Output Low Voltage (All digital outputs) All standard GPIO = 3 mA CMT output IRO = 20 mA VOL 0 — 20% VBATT V Input capacitance (all non-supply pins) CIn — 3 — pF resistors4 — V kOhm kOhm kOhm 1 All ADC-related specifications apply only to the MC13237. Although the device functions at VDDmin, the supply must first rise about VLVDL. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. 3 Denotes full voltage supply and temperature ranges. 4 Measurement condition for pull resistors: V = V IN SS for pullup and VIN = VDD for pulldown. 2 MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 29 11.5 Supply Current Characteristics Table 10. Supply Current Charactertistics1 (Typical conditions: VBATT = 2.7 V, TA = 25 °C, unless otherwise noted.) Mode Stop3 Details Min. Typ. Max. Unit • All internal circuitry off, RAM, I/O, internal registers & selectable peripheral registers retained, 32 MHz reference oscillator off, KBI active, RTC off, LVD off. RF in reset. — 0.45 — uA • All internal circuitry off, RAM, I/O, internal registers & selectable peripheral registers retained, 32 MHz reference oscillator off, KBI active, RTC on with 1 kHz oscillator, LVD off. RF in reset. — 0.55 — • All internal circuitry off, RAM, I/O, internal registers & selectable peripheral registers retained, 32 MHz reference oscillator off, KBI active, RTC on with 32.768 kHz oscillator, LVD off. RF in reset. — 2.65 — • All internal circuitry off, RAM, I/O, internal registers & selectable peripheral registers retained, 32 MHz reference oscillator on, KBI active, RTC on with 32 MHz oscillator, LVD off. RF in reset. — 330 — • All internal circuitry off, RAM, I/O, internal registers & selectable peripheral registers retained, 32 MHz reference oscillator on, KBI active, RTC on with 32 MHz oscillator, LVD on. RF in reset. • ADC optionally on2. — 450 — 0.50 0.56 0.62 mA — 2.9 — mA 0.53 0.75 0.85 mA 4.0 4.7 4.9 mA Low Power Wait (LPWait) • Entered from LPRun. • Processor off, bus clock @ 250 kHz, voltage regulator in standby. • Peripherals and modem clock disabled. RF in reset. Wait Processor off, system clocks are running and voltage regulator on. RF in reset or active mode. Low Power Run (LPRun) • Processor forced to 500 kHz and bus clock @ 250 kHz. • Peripheral state and RAM retained. Voltage regulators in standby. • Peripherals and modem clocks disabled. RF in reset. Run • Processor running @ 32 MHz and peripheral clock @ 16 MHz. • All peripherals clocks disabled3 & RAM active, voltage regulators fully on. • RF in reset. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 30 Freescale Semiconductor Table 10. Supply Current Charactertistics1 (continued) (Typical conditions: VBATT = 2.7 V, TA = 25 °C, unless otherwise noted.) Mode Details Min. Typ. Max. Unit Transmit (TX) • MCU in LPRUN (peripheral clock@ 250 kHz) • RF in transmit mode (nominal power out)4 21.3 26.6 28.2 mA Receive Partial Power Down (RX_PPD) • MCU in LPRUN (peripheral clock@ 250 kHz) • RF in Receive Partial Power Down Mode — 22.3 — mA Receive (RX) • MCU in LPRUN (peripheral clock@ 250 kHz) • RF in receive mode either 1) waiting @ full sensitivity or 2) receiving an actual frame. 26.8 34.2 35 mA 1 For ADC supply current specifications, see Table 24. Requires the asynchronous ADC clock. For Stop3, LVD must be enabled to run in Stop if converting bandgap channel. 3 Register adjustment is per MC1323x Advance information, Rev 0.0 document: set SCGC1 and SCGC2 = 0X00 4 TX output power set to nominal (0 dBm) 2 Figure 4. Typical RUN Current versus CPU Clock (only 0.5, 1, 2, 4, 8, 16, and 32 MHz available) 11.6 RF AC Electrical Characteristics NOTE All specified RF parameters are referenced to the package pins and are the result of measurements with instrumentation in the reference circuit shown in Figure 5. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 31 Table 11. Receiver AC Electrical Characteristics for 802.15.4 Modulation Mode (Typical conditions: VBATT = 2.7 V, TA = 25 °C, fref = 32MHz, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit — –93 — dBm SENS — — –89 dBm SENSmax 10 — — dBm — — — — — 35 25 45 43 50 — — — — — dB 200 — — kHz 80 — — ppm Sensitivity for 1% Packet Error Rate (PER) (+25 °C, @ package interface)1 SENS25 °C Sensitivity for 1% Packet Error Rate (PER) (Over all conditions) 2 Saturation (maximum input level) Channel Rejection for 1% PER +5 MHz (adjacent channel)3 –5 MHz (adjacent channel)3 +10 MHz (alternate channel)4 –10 MHz (alternate channel)4 >= 15 MHz5 Frequency Error Tolerance6 Symbol Rate Error 1 2 3 4 5 6 Tolerance6 Measured at fc = 2450 MHz. All conditions includes –40°C to +85°C, VBATT = 1.8 V to 3.6 V, and full frequency range IEEE 802.15.4 Standard specifies minimum adjacent channel rejection as 0 dB IEEE 802.15.4 Standard specifies minimum alternate channel rejection as 30 dB This parameter represents an average of all readings across all channels Minimum set by IEEE 802.15.4 Standard Table 12. Transmitter AC Electrical Characteristics for 802.15.4 Modulation Mode (Typical conditions: VBATT = 2.7 V, TA = 25 °C, fref = 32 MHz, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Pout –2.5 0 2.3 dBm — +2 — dBm — <16 18 % Output Power Control Range — 30 — dB Over the Air Data Rate — 250 — kbps — –444 — dBm/(100 kHz) — –544 — dBm/(100 kHz) Nominal Output Power1 Maximum Output Power2 Error Vector Magnitude 2nd Harmonic3 3rd Harmonic and greater3 5 Spurious Emissions <1 GHz (quasi-peak detection mode) >1 GHz (peak detection mode) Lower Band Edge (peak detection mode) Upper Band Edge (peak detection mode) EVM — — –66 –40 –34 –23 dBm dBm/MHz dBm/MHz dBm/MHz 1 Register sets output power to nominal (0 dBm). Register sets output power to maximum. 3 Measurements taken at output of evaluation circuit set for maximum power out and averaged over 100 ms. 4 With use of external filtering / harmonic trap as implemented in reference circuit. 5 Derived from measured radiated values in units of dBuV/m and converted to EIRP (dBm). 2 MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 32 Freescale Semiconductor J1 SMA G3 G2 G4 1 G1 C2 10PF L1 2 0.0033UH L2 RF_P RF_N RF_BIAS/TINJ_P NC/TINJ_N 42 RF_N 1 2 Z1 C18 0.8PF Z_RF_P RF_BIAS Z_RF_N 41 43 45 3 1 2 5 4 0.0033UH RF_50 2 1 RF_P 6 L3 3.9nH C7 2PF 50/50 OHMS RF_BIAS C6 10PF 1 U2 HARMONIC TRAP MC1323X Figure 5. RF Parameter Reference Circuit Table 13. RF Port Impedance, Pin RF_P and RF_N Description Series equivalent effective device impedance across the differential port derived from characterization of match network 11.7 Frequency Symbol Typical Unit 2.405 GHz 2.442 GHz 2.480 GHz Zin 22.2 – j74.8 20.6 – j89.9 20.2 – j98.4 Crystal Reference Clock Oscillator Characteristics The reference oscillator model including external crystal in shown in Figure 6. The IEEE 802.15.4 Standard requires a frequency tolerance less than or equal to 40 ppm as shown in the oscillator specification Table 14. With a suitable crystal (refer to Table 15), the device frequency tolerance can typically trimmed to be held to 30 ppm over all conditions. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 33 REFERENCE OSCILLATOR 32 MHz MC1323x Coarse Tune [3:0] Coarse Tune [3:0] 0-4.215 pF with steps of 281 fF. 0-4.215 pF with steps of 281 fF. Fine Tune [3:0] Fine Tune [3:0] 0-300 fF with steps of 20 fF. 0-300 fF with steps of 20 fF. EXTAL_32M XTAL_32M Y1 CR Y STAL CL1 Cs tray Cs tray CL2 Figure 6. 32MHz Reference Oscillator Model Table 14. Reference Oscillator Specifications Characteristic Symbol Min Frequency (nominal) Typ Max 32.000000 30 Oscillator frequency tolerance over temperature range. Unit MHz 40 ppm External load capacitance CLext 8 pF Internal Osc startup time1 tcst 800 s 1 This is part of device wake-up time. Table 15. Recommended 32 MHz Crystal Specifications Parameter Frequency Frequency tolerance (cut tolerance) Value Unit Condition 32.000000 MHz 10 ppm max at 25 °C 16–18 2 ppm Over desired temperature range ppm max Equivalent series resistance 60 max Load capacitance 9 pF Shunt capacitance <2 pF Frequency stability (temperature drift) Aging Mode of oscillation max fundamental MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 34 Freescale Semiconductor 11.8 Optional 32.768 kHz Crystal Oscillator Specifications 32.768 kHz OSCILLATOR Rf EXTAL_32K XTAL_32K Y1 CRY STAL CL1 Cstray 1 Cstray 2 CL2 Figure 7. 32.768 kHz Oscillator Mode l Table 16. 32.768 Oscillator Crystal Typical Specifications Characteristic Symbol Min Typ Crystal frequency Frequency tolerance @ 25 °C 11.9 Load capacitance 12 Equivalent series resistance (ESR) 40 Max Unit 32.768 kHz 20 ppm 12.5 16 pF 130 k Shunt capacitance 2 pF Tolerated drive level 1 W Internal Low Speed Reference Oscillator Specifications Table 17. Internal 1 kHz Oscillator Specifications Characteristic Default Frequency @ 25 °C Oscillator frequency variation over temperature1 Deviation at -40 °C from 25 °C frequency Deviation at +85 °C from 25 °C frequency 1 Symbol Min Typ Max Unit 0.80 1.0 1.40 kHz — — –13 +6 % This percentage deviation is typical change from the individual device oscillator frequency at 25°C MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 35 11.10 Control Timing and CPU Bus Specifications Table 18. MCU Control Timing (Typical conditions: VBATT = 2.7 V, TA = 25 °C, fref = 32MHz, unless otherwise noted.) Parameter Symbol Min Typical Max Unit CPU frequency (tcyc = 1/RDIV) fCPU fref/641 — 32 1 MHz Bus Frequency (always 1/2 CPU clock) (tcyc = fBUS) fBUS fCPU/2 MHz External reset pulse width 100 — — ns External asynchronous minimum interrupt pulse width (KBI or IRQ)2 100 — — ns External synchronous minimum interrupt pulse width (KBI or IRQ)3 4 1.5 tcyc — — ns Wake-up time from Stop3 s 800 1 The 32 MHz reference clock. Minimum pulse to recognize a asynchronous transition 3 Minimum pulse to recognize a level sensitive 4 For determination of an actual key/push button in a matrix, this pulse with must remain present for the keyboard scan routine duration. Thus, the minimum pulse width would be determined by the software, not the detection hardware. 2 11.11 SPI Timing tCYC SPI_SCK tSS_H tSS_SU SPI_SS (slave in) tXX_SU SPI_MOSI (slave in) SPI_MISO (master in) tXX_H tMO,tSO SPI_MOSI (master out) SPI_MISO (slave out) Figure 8. SPI Timing Diagram Table 19 describes the timing requirements for the SPI system. MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 36 Freescale Semiconductor Table 19. SPI Timing Parameter Symbol Min tCYC tCYC tSS_SU tSS_H tSI_SU tSI_H tMI_SU tMI_H tMO tSO bus_Clk*2 Master SPI_SCK Period Slave SPI_SCK Period Slave SPI_SS Setup Time Slave SPI_SS Hold Time Slave SPI_MOSI Setup Time Slave SPI_MOSI Hold Time Master SPI_MISO Setup Time Master SPI_MISO Hold Time Master SPI_MOSI Output Time Slave SPI_MISO Output Time (with 15 pf load) Typical Max Unit bus_Clk *256 ns 10 ns 10 ns 10 ns 10 ns 10 ns 20 ns 0 ns 5 ns 20 ns 11.12 I2C Specifications Table 20 describes the timing requirements for the I2C system. The I2C module is driven by the peripheral bus clock (typically max 16 MHz) and the SCL bit clock is generated from a prescaler. Table 20. I2C Signal DC Specifications (I2C_SDA and I2C_SCL) Parameter Symbol Min Typical Max Unit Input Low Voltage VIL –0.3 — 0.3 VDDINT V Input High Voltage VIH 0.7 VBATT — VBATT + 0.3 V Input hysteresis Vhys 0.06 VBATT — — V Output Low Voltage1 (IOL = 5 mA) VOL 0 — 0.2 VBATT V Input Current (VIN = 0 V or VDDINT) IIN — — ±1 µA Pin capacitance Cin — — <10 pF 1 SDA and SCL are open drain outputs MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 37 SDA tf tSU;DAT tr tLOW tHD:STA tBUF tr SCL tf tHD tSU;STA tSU;STO tHIGH tHD;DAT S Sr P S 2 Figure 9. I C Timing Diagram NOTE timing limits reflect values that are necessary meet to the I2C Bus The specification. I2C Table 21. I2C Signal AC Specifications1 Parameter Symbol Standard-Mode Fast-Mode Unit Min Max Min Max fSCL 0 100 0 150 kHz tHD;STA 4.0 — 0.6 — s LOW period of the SCL clock tLOW 4.7 — 1.3 — s HIGH period of the SCL clock tHIGH 4.0 — 0.6 — s tSU;STA 4.7 — 0.6 — s tSHD;DAT 02 3.453 02 0.93 s — ns SCL clock frequency (when source) Hold time (repeated) Start condition. After this period, the first clock pulse is generated Set-up time for a repeated Start condition Data hold time tSU:DAT 250 — 1004 Rise time for both SDA and SCL signals tr — 1000 20 + 0.1Cb5 300 ns Fall time for both SDA and SCL signals tf — 300 20 + 0.1Cb5 300 ns tBUF 4.7 — 1.3 — s Cb — 400 — 400 pF Data setup time Bus free time between a Stop and Start condition Capacitive load for each bus line 1 All values referred to VIHmin and VILmax levels A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 The maximum t HD;DAT has to be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 2 MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 38 Freescale Semiconductor A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. 5 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, the faster fall-times are allowed. 4 11.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. The flash is 131072 bytes organized as 128 pages by 1024 bytes. NOTE Flash erase and program may be executed only with CPU clock programmed for 32 MHz (default). Flash operations are hardware state machine controlled. User code need not count cycles. The following information is supplied for calculating approximate time to program and erase. Table 22. Flash Characteristics Characteristic Symbol Min VBATT 1.6 Supply voltage for program/erase/read operation Typical Max Unit 3.6 V Byte program time (random location) tprog 40 s Per Byte program time (burst mode) - excludes start/end overhead tBurst 20 s Sector erase time tSector 20 ms Mass erase time tMass 20.1 ms cycles Program/erase endurance TL to TH = –40C to + 85C T = 25C 20,000 — — 100,000 Data retention @ 25C 100 tD_ret — years 11.14 ADC Characteristics ADC characteristics are applicable only to MC13237. Table 23. 12-bit ADC Operating Conditions Characteristic Supply voltage Conditions Absolute Delta to VDD (VDD-VDDA Ground voltage Delta to Ref Voltage High )2 VSS (VSS-VSSA)2 Symb Min Typ1 Max Unit VDDA 1.8 — 3.6 V VDDA –100 0 +100 mV VSSA –100 0 +100 mV VREFH 1.8 VDDA VDDA V Comment MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 39 Table 23. 12-bit ADC Operating Conditions (continued) Symb Min Typ1 Max Unit Ref Voltage Low VREFL VSSA VSSA VSSA V Input Voltage VADIN VREFL — VREFH V Input Capacitance CADIN — 4.5 5.5 Input Resistance RADIN — 5 7 — — — — 2 5 10 bit mode fADCK > 4MHz fADCK < 4MHz — — — — 5 10 8 bit mode (all valid fADCK) — — 10 0.4 — 8.0 0.4 — 4.0 Characteristic Analog Source Resistance Conditions pF k RAS 12 bit mode fADCK > 4MHz fADCK < 4MHz Comment External to MCU k ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1) fADCK MHz 1 Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT Pad leakage due to input protection ZAS RAS SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 10. ADC Input Impedance Equivalency Diagram MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 40 Freescale Semiconductor Table 24. 12-bit ADC Characteristics (VREFH = VDDASSA, VREFL = VSSA) Symb Min Typ1 Max Supply Current ADLPC=1 ADLSMP=1 ADCO=1 IDDA — 120 — Supply Current ADLPC=1 ADLSMP=0 ADCO=1 IDDA Supply Current ADLPC=0 ADLSMP=1 ADCO=1 IDDA Supply Current ADLPC=0 ADLSMP=0 ADCO=1 IDDA Characteristic Conditions — 202 — A — 288 — A — 0.532 1 mA Stop, Reset, Module Off IDDA — 0.007 0.8 ADC Asynchronous Clock Source High Speed (ADLPC=0) fADACK 2 3.3 5 Low Power (ADLPC=1) 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — 2.0 4.5 — 2.0 4.5 10 bit mode — 1 2.5 8 bit mode — 0.5 ±1.0 — 0.7 –1.5 to +1.9 — 0.5 1.0 — 0.3 0.5 — 1.4 2.5 10 bit mode — 0.5 1.0 8 bit mode — 0.3 0.5 — 0.5 0.5 10 bit mode — 0.5 1.5 8 bit mode — 0.5 0.5 Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) tADC Sample Time tADS Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted 12-bit mode, 3.6> VDDA > 2.7 Error 12-bit mode, 2.7> VDDA > 1.8V 12 bit mode ETUE DNL 10 bit mode3 8 bit mode Integral Non-Linearity Comment A Supply Current Differential Non-Linearity Unit 3 12 bit mode Zero-Scale Error 12 bit mode INL EZS A tADACK = 1/fADACK MHz ADCK cycles ADCK cycles LSB2 Includes Quantization LSB2 LSB2 LSB2 VADIN = VSSA MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 41 Table 24. 12-bit ADC Characteristics (VREFH = VDDASSA, VREFL = VSSA) (continued) Symb Min Typ1 Max Unit Comment EFS — 1.0 –3.5 to 1.0 LSB2 VADIN = VDDA 10 bit mode — 0.5 1 8 bit mode — 0.5 0.5 — –1 to 0 — 10 bit mode — — 0.5 8 bit mode — — 0.5 — 2 — 10 bit mode — 0.2 4 8 bit mode — 0.1 1.2 — 1.646 — — 1.769 — VTEMP25 — 701.2 — mV ENOB 10.66 11.2 — Bits 71 81 — dB Characteristic Full-Scale Error Quantization Error Conditions 12 bit mode 12 bit mode Input Leakage Error 12 bit mode Temp Sensor Slope –40C to 25C Temp Sensor Voltage 25C EQ EIL m 25C to 85C Effective Number Of Bits5 Spurious Free Dynamic Range 12 bit mode LSB2 LSB2 Pad leakage4 * RAS mV/C 1 Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. 5 Dynamic performance of the ADC @ V DDA = 3.0 V, Temp = 25C, fADCK=1.0 MHz and typical sampling rate values with 1 kHz sinewave applied @ the selected channel. ENOB = (SINAD -1.76) / 6.02 where SINAD is Signal-to-Noise plus distortion. SINAD(dB) = 20 x log [SignalRMS / (Noise + Distortion)RMS] 12 Applications Information NOTE Freescale provides a complete suite of design support material including development hardware and software, reference manuals, and hardware references designs for the MC13234/MC13237. The applications material presented here is primarily for illustrative purposes. Figure 11 and Figure 12 illustrate a basic applications circuit based on the MC13234 and MC13237 MRB development boards. Features of the circuit include: MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 42 Freescale Semiconductor • • • • 32 MHz reference oscillator crystal (Y1) is required, and must meet defined specifications Pulldown resistor on signal PTA2 assures that devices does not enter factory test mode on power-up Power supply voltage (V_IC) can range from 1.8 Vdc to 3.6 Vdc (see Table 9 for usage notes) RF Interface circuitry — 50/50 (unbal/bal) balun converts device differential, bidirectional RF port to single-ended 50-ohm antenna port — Control signal RF_Bias switches RF reference voltage to the balun as required for TX or RX — L1 provides impedance matching for MC1323x RF port — C4 and L2 network provides a harmonic trap for out-of-band harmonics and spurs on TX — A low-cost, copper pcb “F” antenna is shown. This is a common option, although other antennas such as a chip antenna or antenna module may also be used • • NOTE RF circuitry at 2.4 GHz is very dependent on board layout and component usage. Figure 11 shows a typical RF configuration, however component value and use can vary based on customer application. Mechanical design information for the MC1323x package and assembly recommendations can be found in the Freescale IEEE 802.15.4 / ZigBee Package and Hardware Layout Considerations Reference Manual, Doc No. ZHDCRM.pdf MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 43 44 Y1 1 EXTAL_32M V_IC C1 12PF 2 U1 2 5 3 1 6 4 2 3 MC13237 Advance Information Data Sheet, Rev. 0.0 4 5 6 HDR 2X3 BDM 7 8 9 R2 10K 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 PTA0/XTAL_32K PTA1/EXTAL_32K PTD0/TPM0 PTD1/TPM1 PTD2/TPM2 PTD3/TPM3 RESET PTD4/CMT PTA2 PTA3/IRQ PTA4/XTAL_32K_OUT PTA5/SDA PTA6/SCL XTAL_32M PTD5/TXD PTD6/RXD PTD7 XTAL_32M EXTAL_32M PTA7/BKGD/MS RF_P PTB0/KBI1P0 PTB1/KBI1P1 PTB2/KBI1P2 PTB3/KBI1P3 PTB4/KBI1P4 PTB5/KBI1P5 PTB6/KBI1P6 PTB7/KBI1P7 RF_BIAS/TINJ_P NC/TINJ_N PTC0/KBI2P0 PTC1/KBI2P1 PTC2/KBI2P2 PTC3/KBI2P3 VBATT_4 VBATT_3 VBATT_2 VBATT_1 PTC4/SPICLK PTC5/SS PTC6/MISO PTC7/MOSI VREG_LO2 VREG_VCO VDD_ANA VREG_ANA RF_N NC PAD C2 12PF 27 28 29 30 32MHz XTAL 31 L1 32 33 34 35 36 RF_P 1 2 Z1 0.0033UH XTAL_32M EXTAL_32M 42 3 1 2 5 Z_RF_N 4 L3 41 RF_N 1 50/50 OHMS C5 10PF 0.0033UH C6 10PF DNP 40 49 V_IC RF_50 RF_ANT V_IC 10PF L2 3.9nH 6 2 RF_BIAS 43 45 C3 Z_RF_P C16 0.8PF RF_BIAS 1 1 J1 3 32MHZ C4 2PF ANT1 F_Antenna 2 R1 10K 4 V_IC 19 37 44 48 HARMONIC TRAP 46 38 39 47 C7 0.1UF C8 10UF C9 0.01UF MC1323X C10 0.22UF C11 8.2PF C8 & C28 PLACE CLOSE TO U1.39 C12 8.2PF C13 0.22UF C14 0.22UF C15 0.22UF C18 & C26 PLACE CLOSE TO U1.47 Figure 11. MC13234 Basic Applications Circuit (Note: Refer to the reference manual for the latest MRB schematic) Freescale Semiconductor Freescale Semiconductor MC13237 Advance Information Data Sheet, Rev. 0.0 45 Figure 12. MC13237 Basic Applications Circuit (Note: Refer to the reference manual for the latest MRB schematic) 13 Mechanical Diagrams (Case 2124-02, Non-JEDEC) Figure 13. Mechanical Diagram (1 of 2) MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 46 Freescale Semiconductor Figure 14. Mechanical Diagram (2 of 2) MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3 Freescale Semiconductor 47 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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