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ST8024L
Smartcard interface
Datasheet − production data
Features
■
Designed to be compatible with the NDS
conditional access system (except
ST8024LTR)
■
ISO 7816, GSM11.11 and EMV 4.2 (payment
systems) compatible
■
IC card interface
■
3 V or 5 V supply for the ST8024L device (VDD)
■
Three specifically protected half-duplex
bi-directional buffered I/O lines to card contacts
C4, C7 and C8
SO-28
TSSOP-20
TSSOP-28
■
Enhanced ESD protection on card side (>6 kV)
■
26 MHz integrated crystal oscillator
■
Built-in debounce on card presence contacts
■
One multiplexed status signal OFF
■
Non-inverted control of RST via pin RSTIN
1.8 V ± 6.5%, 3 V or 5 V ± 5% regulated card
supply voltage (VCC) with appropriate
decoupling has the following capabilities:
– ICC < 80 mA at VDDP = 4.75 to 6.5 V
– Handles current spikes of 40 nA up
to 20 MHz
– Controls rise and fall times
– Filtered overload detection at ~120 mA
■
Clock generation for cards up to 20 MHz
(divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency
changes
■
Supply supervisor for spike-killing during
power-on and power-off and power-on reset
(threshold fixed internally or externally by
a resistor divider)
■
Thermal and short-circuit protection on all card
contacts
Applications
■
Automatic activation and deactivation
sequences; initiated by software or by
hardware in the event of a short-circuit, card
take-off, overheating, VDD or VDDP dropout
■
Smartcard readers for set-top boxes
■
IC card readers for banking
■
Identification, pay TV
■
■
Step-up converter for VCC generation
separately powered by a 5 V ± 20% supply
(VDDP and PGND)
Table 1.
Device summary
PORADJ/
1.8 V function
Temperature
range
Package
Packaging
Package
top mark
ST8024LCDR(1)
PORADJ
–25 to 85 °C
SO-28 (tape and reel)
1000 parts per reel
ST8024LC
(1)
PORADJ
–25 to 85 °C
TSSOP-28 (tape and reel) 2500 parts per reel
ST8024LC
1.8 V
–25 to 85 °C
Order code
ST8024LCTR
ST8024LACDR(1)
SO-28 (tape and reel)
1000 parts per reel ST8024LAC
ST8024LTR
1.8 V
–25 to 85 °C
TSSOP-20 (tape and reel) 2500 parts per reel
ST8024LACTR(1)
1.8 V
–25 to 85 °C
TSSOP-28 (tape and reel) 2500 parts per reel ST8024LAC
ST8024L
1. Certified by NDS.
May 2012
This is information on a product in full production.
Doc ID 17709 Rev 5
1/35
www.st.com
1
Contents
ST8024L
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.1
Without external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.2
With an external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.3
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Clock circuitry (only on SO-28 and TSSOP-28 packages) . . . . . . . . . . . . 20
6.4
I/O transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6
Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.7
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.8
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.9
VCC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.10
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.11
VCC selection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35
Doc ID 17709 Rev 5
ST8024L
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics over recommended operating condition . . . . . . . . . . . . . . . . . . . 10
Step-up converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Card supply voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crystal connection (pins XTAL1 and XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC, and AUX2UC) . . . . . . . . . . . . . . . . . 12
Data lines to card reader (pins I/O, AUX1, and AUX2 with integrated 11 kΩ
pull-up resistor to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data lines to microcontroller (pins I/OUC, AUX1UC, and AUX2UC with integrated
11 kΩ pull-up resistor to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset output to card reader (pin RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock output to card reader (pin CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V
and PORADJ/1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Card presence inputs (pins PRES and PRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD) . . . . 16
Protection and limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Card presence indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VCC selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-28 small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TSSOP-20 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP-28 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TSSOP-20 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TSSOP-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 17709 Rev 5
3/35
List of figures
ST8024L
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
4/35
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Definition of output and input transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Activation sequence using RSTIN and CMDVCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Activation sequence at t3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Behavior of OFF, CMDVCC, PRES, and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SO-28 small outline, package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TSSOP-20 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP-28 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TSSOP-20 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TSSOP-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 17709 Rev 5
ST8024L
1
Description
Description
The ST8024L is a complete low-cost analog interface for asynchronous Class A, B, and C
smartcards. It can be placed between the card and the microcontroller with few external
components to perform all supply protection and control functions. The ST8024LCDR and
ST8024LCTR are compatible with the ST8024 (with the exception of Vth(ext)rise/fall value).
Doc ID 17709 Rev 5
5/35
Diagram
ST8024L
2
Diagram
Figure 1.
Block diagram
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#36
1. To be used with the PORADJ pin if needed.
2. Not available in the TSSOP-20L package.
3. ST8024LCDR, ST8024LCTR.
4. ST8024LACDR, ST8024LACTR, ST8024LTR.
6/35
Doc ID 17709 Rev 5
ST8024L
Pin configuration
3
Pin configuration
Figure 2.
Pin connections
Table 2.
Pin description
Symbol
Name and function
SO-28/
TSSOP-28
TSSOP-20
CLKDIV1
Control of CLK frequency
(internal 11 kΩ pull-up resistor connected to VDD)
1
N. A.
CLKDIV2
Control of CLK frequency
(internal 11 kΩ pull-down resistor connected to GND)
2
N. A.
5V/3V
5 V or 3 V VCC selection for communication with the smartcard. Logic high
selects 5 V operation and logic low selects 3 V operation (for ST8024LACDR,
ST8024LACTR, and ST8024LTR: if the 1.8V pin is logic high, the 5V/3V pin is
a “don't care”). See Table 23 for a description of the VCC selection settings.
3
1
PGND
Power ground for step-up converter
4
2
C1+
External capacitor step-up converter
5
3
VDDP
Power supply for step-up converter
6
4
C1–
External capacitor step-up converter
7
5
VUP
Output of step-up converter
8
6
PRES
Card presence input (active low) - bonding option
9
N. A.
PRES
Card presence input (active high)
10
7
Data line to and from card (C7)
(internal 11 kΩ pull-up resistor connected to VCC)
11
8
I/O
Doc ID 17709 Rev 5
7/35
Pin configuration
Table 2.
ST8024L
Pin description (continued)
Symbol
Name and function
SO-28/
TSSOP-28
TSSOP-20
AUX2
Auxiliary line to and from card (C8)
(internal 11 kΩ pull-up resistor connected to VCC)
12
N. A.
AUX1
Auxiliary line to and from card (C4) (internal 11 kΩ pull-up resistor to VCC)
13
N. A
CGND
Ground for card signal (C5)
14
9
CLK
Clock to card (C3)
15
10
RST
Card reset (C2)
16
11
VCC
Supply voltage for the card (C1)
17
12
PORADJ Power-on reset threshold adjustment input (ST8024LCDR, ST8024LCTR)
1.8V
1.8 V VCC operation selection. Logic high selects 1.8 V operation and
overrides any setting on the 5V/3V pin. With an internal 11 kΩ pull-down
resistor to GND. (ST8024LACDR, ST8024LACTR and ST8024LTR)
CMDVCC Start activation sequence input (active low)
N. A.
18
13
19
14
Card reset input from MCU
20
15
VDD
Supply voltage
21
16
GND
Ground
22
17
OFF
Interrupt to MCU (active low)
23
18
XTAL1
Crystal or external clock input
24
19
XTAL2
Crystal connection (leave this pin open if external clock is used)
25
N.A
I/OUC
MCU data I/O line (internal 11 kΩ pull-up resistor connected to VDD)
26
20
AUX1UC Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to VDD)
27
N. A.
AUX2UC Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to VDD)
28
N. A.
RSTIN
8/35
Doc ID 17709 Rev 5
ST8024L
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings(1)
Symbol
Parameter
Min.
Max.
Unit
-0.3
7
V
VDD, VDDP Supply voltage
Vn1
Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC,
I/OUC, CLKDIV1, CLKDIV2, PORADJ/1.8V, CMDVCC, PRES,
PRES, and OFF
-0.3
VDD + 0.3
V
Vn2
Voltage on card contact pins I/O, RST, AUX1, AUX2, and CLK
-0.3
VCC + 0.3
V
Vn3
Voltage on pins VUP, C1+, and C1–
7
V
-6
6
kV
-2
2
kV
150
°C
150
°C
ESD1
MIL-STD-883 class 3 on card contact pins, PRES and PRES
ESD2
MIL-STD-883 class 2 on µC contact pins and RSTIN (2), (3)
TJ(MAX)
TSTG
(2) (3)
,
Maximum operating junction temperature
Storage temperature range
-40
1. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under
these conditions is not implied.
2. All card contacts are protected against any short with any other card contact.
3.
Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Table 4.
Symbol
RthJA
Table 5.
Symbol
TA
Thermal data
Parameter
Thermal resistance junction-ambient
temperature
Condition
SO-28
Multilayer test board
(JEDEC standard)
56
TSSOP-20
TSSOP-28
50
Unit
°C/W
Recommended operating conditions
Parameter
Test conditions
Temperature range
Min.
–25
Doc ID 17709 Rev 5
Typ.
Max.
Unit
85
°C
9/35
Electrical characteristics
ST8024L
5
Electrical characteristics
Table 6.
Electrical characteristics over recommended operating condition
Symbol
VDD
VDDP
IDD
IDDP
Parameter(1)
Test conditions
Supply voltage
Supply voltage for the
step-up converter
Min.
Typ.
2.7
Max.
Unit
6.5
V
VCC = 5 V; |ICC| < 80 mA
4.0
5
6.5
VCC = 3 V; |ICC| < 65 mA
4.0
5
6.5
VCC = 5 V; |ICC| < 20 mA
3.0
6.5
VCC = 3 V; |ICC| < 20 mA
2.7
6.5
VCC = 1.8 V; |ICC| < 20 mA
2.7
6.5
Card inactive
1.2
Card active; fCLK = fXTAL; CL = 30 pF
1.5
Inactive mode
0.1
Active mode; fCLK = fXTAL; CL = 30 pF;
|ICC| = 0
10
Supply current
V
mA
Step-up converter supply
current
VCC = 5 V; |ICC| = 80 mA
50
200
VCC = 3 V; |ICC| = 65 mA
50
100
VCC = 1.8 V; |ICC| = 45 mA
30
60
mA
Vth2
Falling threshold voltage
on VDD
No external resistors at pin PORADJ;
VDD level falling. See Figure 4.
2.35
2.45
2.55
V
VHYS2
Hysteresis of threshold
voltage Vth2
No external resistors at pin PORADJ.
See Figure 4.
50
100
150
mV
Vth(ext)rise
External rising threshold
voltage at pin PORADJ
External resistor divider at pin PORADJ;
VDD level rising. See Section 6.2.2.
1.17
1.20
1.23
V
Vth(ext)fall
External falling threshold External resistor divider at pin PORADJ;
voltage at pin PORADJ
VDD level falling. See Section 6.2.2.
1.11
1.14
1.17
V
VHYS(ext)
Hysteresis of threshold
voltage Vth(ext)
External resistor divider at pin PORADJ.
See Section 6.2.2.
30
60
90
mV
Hysteresis of threshold
ΔVHYS(ext) voltage Vth(ext) variation
with temperature
External resistor divider at pin PORADJ
0.25
mV/K
tW
Width of internal poweron reset pulse
No external resistor divider at pin
PORADJ
4
8
12
External resistor divider at pin PORADJ
8
16
24
4
10
ms
Leakage current on pin
PORADJ
VPORADJ < 0.5 V
–0.1
IL
VPORADJ > 1.0 V
–1
PTOT
Total power dissipation
Continuous operation; TA = –25 to 85 °C
µA
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
10/35
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0.56
W
ST8024L
Table 7.
Symbol
fCLK
Vth(vd-vf)
VUP
Electrical characteristics
Step-up converter
Parameter(1)
Test conditions
Min.
Typ.
Max.
Unit
3.2
MHz
Clock frequency
Card active
2.2
Threshold voltage for
step-up converter to
change to voltage
follower
5 V card
5.2
5.8
6.2
3 V card
3.8
4.1
4.4
1.8 V card
3.8
4.1
4.4
5 V card
5.2
5.7
6.2
3 V card
3.5
3.9
4.3
1.8 V card
3.5
3.9
4.3
Typ.
Max.
Unit
400
nF
Output voltage on pin
VUP (average value)
V
V
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Table 8.
Symbol
CVCC
VCC
Card supply voltage characteristics
Parameter(1)
Test conditions
External capacitance
See(2)
on pin VCC
Card supply voltage
(including ripple
voltage)
80
Card inactive; |ICC| = 0 mA
5 V, 3 V and
1.8 V card
-0.1
0
0.1
Card inactive; |ICC| = 1 mA
5 V, 3 V and
1.8 V card
-0.1
0
0.3
Card active; |ICC| < 80 mA
5 V card
4.75
5
5.25
Card active; |ICC| < 65 mA
3 V card
2.85
3
3.15
Card active; |ICC| < 45 mA
1.8 V card
1.68
1.8
1.92
Card active; single current
5 V card
pulse IP = –100 mA; tp = 2 µs
4.65
5
5.25
Card active; single current
3 V card
pulse IP = –100 mA; tp = 2 µs
2.76
3
3.20
Card active; single current
1.8 V card
pulse IP = –100 mA; tp = 2 µs
1.62
1.8
1.98
5 V card
4.65
5
5.25
3 V card
2.76
3
3.20
1.8 V card
1.62
1.8
1.98
5 V card
4.65
5
5.25
3 V card
2.76
3
3.20
1.8 V card
1.62
1.8
1.98
Card active; current pulses,
QP = 40 nAs
Card active; current pulses
QP = 40 nAs with
|ICC| < 200 mA, tp < 400 ns
VCC
(RIPPLE)
(P-P)
Ripple voltage on
VCC (peak-to-peak
value)
Min.
fRIPPLE = 20 kHz to 200 MHz
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V
mV
11/35
Electrical characteristics
Table 8.
Symbol
|ICC|
ST8024L
Card supply voltage characteristics (continued)
Parameter(1)
Card supply current
Test conditions
Slew rate
Typ.
Max.
VCC = 0 to 5 V
80
VCC = 0 to 3 V
65
VCC = 0 to 1.8 V
45
Unit
mA
VCC short-circuit to GND
SR
Min.
Slew up or down, VCC = 5 V; 3 V; 1.8 V;
|ICC| < 30 mA
90
0.08
120
0.15
0.22
V/µs
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C. (All parameters remain
within limits but are tested only statistically for the temperature range. When a parameter is specified as a function of VDD or
VCC it means their actual value at the moment of measurement.)
2. To meet these specifications, pin VCC should be decoupled to CGND using two 100 nF ceramic multilayer capacitors of
max. 350 mΩ ESR. If VCC slew rate is not critical, the capacitance value can be up to 400 nF. (See Figure 10).
Table 9.
Crystal connection (pins XTAL1 and XTAL2)
Symbol
Parameter(1)
Test conditions
CXTAL1,2
External capacitance
on pins XTAL1,
XTAL2
Depends on type of crystal or resonator used
Min.
Typ.
Max.
Unit
-
15
pF
fXTAL
Crystal frequency
2
-
26
MHz
fXTAL1
Frequency applied on
pin XTAL1
0
-
26
MHz
VIH
High level input
voltage on pin XTAL1
0.7
VDD
-
VDD
+0.3
V
VIL
Low level input
voltage on pin XTAL1
-0.3
-
+0.3
VDD
V
Min.
Typ.
Max.
Unit
I/O to I/OUC, I/OUC
tD(I/O-I/OUC),
to I/O falling edge
tD(I/OUC-I/O)
delay
-
-
200
ns
tPU
Active pull-up pulse
width
-
-
100
ns
fI/O(MAX)
Maximum frequency
on data lines
-
-
1
MHz
CI
Input capacitance on
data lines
-
-
10
pF
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Table 10.
Symbol
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC, and AUX2UC)
Parameter(1)
Test conditions
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
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ST8024L
Table 11.
Symbol
Electrical characteristics
Data lines to card reader (pins I/O, AUX1, and AUX2 with integrated 11 kΩ pull-up
resistor to VCC)
Parameter(1)
Test conditions
No load
VO(inactive) Output voltage
Inactive mode
IO(inactive) Output current
Inactive mode; pin grounded
High level output voltage
Typ.
0
Max.
Unit
0.1
V
IO(inactive) = 1 mA
No DC load
VOH
Min.
0.3
-1
0.9 VCC
VCC +0.1
5 V and 3 V cards; IOH < –40 µA
0.75 VCC
VCC +0.1
1.8 V card IOH < –40 µA
0.75 VCC
|IOH| ≥ 10 mA
0
0.4
IOL = 1 mA
0
0.2
IOL ≥ 15 mA
VCC–0.4
VCC
1.5
VCC +0.3
mA
V
VOL
Low level output voltage
VIH
High level input voltage
VIL
Low level input voltage
|ILIH|
High level input leakage
current
VIH = VCC
10
µA
|IIL|
Low level input current
VIL = 0 V
600
µA
RPU
Integrated pull-up resistor Pull-up resistor to VCC
13
kΩ
tT(DI)
Data input transition time
VIL max. to VIH min.
1.2
µs
tT(DO)
Data output transition
time
VO = 0 to VCC; CL ≤ 80 pF; 10% to
90%
0.1
µs
IPU
Current when pull-up
active
VOH = 0.9 VCC; CL = 80 pF
5 V and 3 V cards
1.8 V card
5 V and 3 V cards
V
V
0.6 VCC
0.3
1.0
0
0.2
V
1.8 V card
9
11
-2
mA
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
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Electrical characteristics
Table 12.
Symbol
VOH
ST8024L
Data lines to microcontroller (pins I/OUC, AUX1UC, and AUX2UC with integrated
11 kΩ pull-up resistor to VDD)
Parameter(1)
High level output voltage
Test conditions
Min.
Typ.
Max.
Unit
5 V, 3 V and 1.8 V cards;
IOH < –40 µA
0.75 VDD
VDD +0.1
No DC load
0.9 VDD
VDD +0.1
IOL = 1 mA
0
0.3
V
V
VOL
Low level output voltage
VIH
High level input voltage
0.7 VDD
VDD +0.3
V
VIL
Low level input voltage
-0.3
0.3 VDD
V
|ILIH|
High level input leakage
current
VIH = VDD
10
µA
|IL|
Low level input current
VIL = 0 V
600
µA
RPU
Internal pull-up resistance to
Pull-up resistor to VDD
VDD
13
kΩ
tT(DI)
Data input transition time
VIL max. to VIH min.
1.2
µs
tT(DO)
Data output transition time
VO = 0 to VDD; C L < 30 pF;
10% to 90%
0.1
µs
IPU
Current when pull-up active
VOH = 0.9 VDD; CL = 30 pF
9
11
-1
mA
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Table 13.
Internal oscillator
Symbol
Parameter(1)
fOSC(INT)
Frequency of internal
oscillator
Test conditions
Min.
Typ.
Max.
Unit
Inactive mode
55
140
200
kHz
Active mode
2.2
2.7
3.2
MHz
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted.Typical values are at TA = 25 °C.
Table 14.
Symbol
Reset output to card reader (pin RST)
Parameter(1)
Test conditions
Min.
Typ.
Max.
Unit
Output voltage in inactive
mode
IO(inactive) = 1 mA
0
-
0.3
VO(inactive)
No load
0
-
0.1
IO(inactive)
Output current
Inactive mode; pin grounded
0
-
-1
mA
tD(RSTIN-
RSTIN to RST delay
RST enable
-
2
µs
0
-
0.2
IOL = 20 mA (current limit)
VCC -0.4
-
VCC
IOH = –200 µA
0.9 VCC
-
VCC
0
-
0.4
-
0.1
V
RST)
VOL
Low level output voltage
VOH
High level output voltage
tR, tF
Rise and fall time
IOL = 200 µA
IOH = –20 mA (current limit)
V
CL = 100 pF
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
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V
µs
ST8024L
Table 15.
Symbol
VO(inactive)
Electrical characteristics
Clock output to card reader (pin CLK)
Parameter(1)
Output voltage in inactive
mode
IO(inactive) Output current
VOL
Low level output voltage
VOH
High level output voltage
tR, tF
Rise and fall time
δ
SR
Test conditions
Min.
Typ.
Max.
IO(inactive) = 1 mA
0
-
0.3
No load
0
-
0.1
CLK inactive mode;
pin grounded
0
-
–1
IOL = 200 µA
0
-
0.3
IOL = 70 mA (current limit)
VCC -0.4
-
VCC
IOH = –200 µA
0.9 VCC
-
VCC
0
-
0.4
-
16
ns
55
%
IOH = –70 mA (current limit)
V
mA
V
CL = 30 pF(2)
Duty factor (except for fXTAL) CL = 30 pF(2)
45
-
Slew rate
0.2
-
Slew up or down; CL = 30 pF
Unit
V
V/ns
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
2. Transition time and duty factor definitions are shown in Figure 3; d = t1/(t1+ t2).
Table 16.
Symbol
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V and PORADJ/1.8V)
Parameter(1)
Test conditions
Min.
Typ.
Max.
Unit
VIL
Low level input voltage
–0.3
0.3 VDD
V
VIH
High level input voltage
0.7 VDD
VDD
V
1
µA
|ILIH|
High level input leakage
current
800
µA
|ILIL|
Low level input leakage
current
RPD
Internal pull-down resistor to Pull-down resistor to GND (1.8V
GND
and CLKDIV2 pins)
RPU
Internal pull-up resistor to
VDD
VIH = VDD
VIH = VDD, 1.8V and CLKDIV2
pins with internal 11 kΩ pulldown resistor
VIL = 0
VIL = 0, CLKDIV1 pin with
internal 11 kΩ pull-up resistor
Pull-up resistor to VDD
(CLKDIV1 pin)
-1
µA
-800
µA
9
11
13
kΩ
9
11
13
kΩ
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Pin CMDVCC is active low; pin RSTIN is active high; for CLKDIV1 and CLKDIV2 functions (see Table 21).
Doc ID 17709 Rev 5
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Electrical characteristics
Table 17.
Symbol
ST8024L
Card presence inputs (pins PRES and PRES)
Parameter(1)
Test conditions
Min.
Typ.
Max.
Unit
VIL
Low level input voltage
-0.3
-
0.3 VDD
V
VIH
High level input voltage
0.7 VDD
-
VDD +0.3
V
|ILIH|
High level input leakage
current
VIH = VDD
-
5
µA
|ILIL|
Low level input leakage
current
VIL = 0
-
5
µA
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C
Pin PRES is active low; pin PRES is active high, see Figure 8 and Figure 9; PRES has an integrated 1.25 µA current source
to GND. (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
Table 18.
Symbol
Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD)
Parameter(1)
Test conditions
VOL
Low level output voltage
IOL = 2 mA
VOH
High level output voltage
IOH = –15 µA
RPU
Integrated pull-up resistor
20 kΩ pull-up resistor to VDD
Min.
Typ.
0
Max.
Unit
0.3
V
0.75 VDD
16
V
20
24
kΩ
Max.
Unit
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Table 19.
Protection and limitation
Parameter(1)
Symbol
|ICC(SD)|
Test conditions
Min.
Typ.
Shutdown and limitation current pin VCC
90
120
mA
II/O(lim)
Limitation current pins I/O, AUX1 and AUX2
–15
15
mA
ICLK(lim)
Limitation current pin CLK
–70
70
mA
IRST(lim)
Limitation current pin RST
–20
20
mA
TSD
Shutdown temperature
150
°C
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Table 20.
Timing
Parameter(1)
Symbol
Test conditions
Min.
tACT
Activation time
For VCC = 5 V
(See Figure 5)
50
tDE
Deactivation time
(See Figure 7)
50
t3
Start of the window for sending CLK to card (See Figure 6)
t5
End of the window for sending CLK to card
(See Figure 6)
140
Debounce time pins PRES and PRES
(See Figure 8)
5
tdebounce
Typ.
80
Doc ID 17709 Rev 5
Unit
220
µs
100
µs
130
µs
µs
8
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
16/35
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11
ms
ST8024L
Figure 3.
Electrical characteristics
Definition of output and input transition times
CS13450
Doc ID 17709 Rev 5
17/35
Functional description
6
ST8024L
Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
6.1
Power supply
The supply pins for the ST8024L are VDD and GND. VDD should be in the range of 2.7 to
6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader contacts remain inactive during
power-on or power-off.
The internal circuits are kept in the reset state until VDD reaches Vth2 +VHYS2 and for the
duration of the internal power-on reset pulse, tW (see Figure 4). When VDD falls below Vth2,
an automatic deactivation of the contacts is performed.
A step-up converter is incorporated to generate the 1.8 V (for those devices with the
1.8V pin), 3 V, or 5 V card supply voltage (VCC). The step-up converter should be supplied
separately by VDDP and PGND. Due to the possibility of large transient currents, the two
100 nF capacitors of the step-up converter should be located as near as possible to the
ST8024L and have an ESR less than 350 mΩ .
During power-up, the VDD supply voltage must be applied prior to the VDDP supply voltage
or at the same time
After powering the device, OFF remains low until CMDVCC is set high.
During power-off, OFF falls low when VDD is below the falling threshold voltage.
6.2
Voltage supervisor
6.2.1
Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms
(tW) is used internally to keep the ST8024L inactive during power-on or power-off of the VDD
supply (see Figure 4).
As long as VDD is less than Vth2 + VHYS2, the ST8024L remains inactive regardless of the
levels on the command lines. This state also lasts for the duration of tW after VDD has
reached a level higher than Vth2 + VHYS2. When VDD falls below Vth2, a deactivation
sequence of the contacts is performed.
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ST8024L
Functional description
Figure 4.
6.2.2
Voltage supervisor
With an external divider on pin PORADJ
In this case, a resistor divider is connected to the PORADJ pin (see Figure 1). Vth(ext) rise
and Vth(ext) fall are the external rising threshold voltage and the external falling threshold
voltages on pin PORADJ that switch the device on and off. By knowing these values and
using the formula:
VDD UVLO threshold (falling) = (R1+R2)/R2 x Vth(ext)fall
VDD UVLO threshold (rising) = (R1+R2)/R2 x Vth(ext)rise
it is possible to set R 1 and R2 in order to get suitable values for VDD undervoltage (UVLO)
thresholds, in order to turn the device on and off (R 1 + R 2 = 100 kΩ typ.).
In particular, R1 and R2 must be set so that, when VDD is getting low, before turning the
microcontroller off, the smartcard must also be switched off properly. The same is true for
the microcontroller startup - in such case the smartcard must be turned on after the
microcontroller. The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed
when the voltage on pin PORADJ exceeds 1 V.
This ensures that after detection of the external divider by the ST8024L during power-on,
the input current on pin PORADJ does not cause inaccuracy of the divider voltage.
Note:
The Vth(ext) threshold of the ST8024L is slightly lower (by 80 mV typ.) than it was in the case
of the ST8024 device. If, for example, the microcontroller is shut down at 2.5 V, the
appropriate external resistor values must be chosen to ensure proper deactivation of the
ST8024L device.
6.2.3
Application examples
The voltage supervisor is used as power-on reset and as supply dropout detection during
a card session. Supply dropout detection is to ensure that a proper deactivation sequence is
followed before the voltage is too low. For the internal voltage supervisor to function, the
system microcontroller should operate down to 2.35 V to ensure a proper deactivation
sequence. If this is not possible, external resistor values can be chosen to overcome the
problem.
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Functional description
6.3
ST8024L
Clock circuitry (only on SO-28 and TSSOP-28 packages)
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from
a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1/2 x fXTAL, 1/4 x fXTAL, or 1/8 x fXTAL. Frequency selection
is made via inputs CLKDIV1 and CLKDIV2 (see Table 21).
Table 21.
Clock frequency selection(1)
CLKDIV1
CLKDIV2
fCLK
0
0
fXTAL/8
0
1
fXTAL/4
1
1
fXTAL/2
1
0
fXTAL
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed. The minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45% of the smallest period, and that the first and last clock pulses regarding the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command. The duty factor of fXTAL depends on the signal present at pin
XTAL1. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit
layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin
CLK is guaranteed between 45 and 55% of the clock period.
The crystal oscillator runs as soon as the ST8024L is powered up. If the crystal oscillator is
used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card
as shown in the activation sequences in Figure 5 and Figure 6.
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse is
applied to the card when it is sent by the system microcontroller (after completion of the
activation sequence).
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ST8024L
6.4
Functional description
I/O transceivers
The three data lines I/O, AUX1, and AUX2 are identical. The idle state is realized by both I/O
and I/OUC lines being pulled high via an 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin
I/O is referenced to VCC, and pin I/OUC to VDD, therefore allowing operation when VCC is not
equal to VDD. The first side of the transceiver to receive a falling edge becomes the master.
An anti-latch circuit disables the detection of falling edges on the line of the other side, which
then becomes a slave. After a time delay td(edge), an N transistor on the slave side is turned
on, therefore transmitting the logic 0 present on the master side. When the master side
returns to logic 1, a P transistor on the slave side is turned on during the time delay tPU and
then both sides return to their idle states. This active pull-up feature ensures fast low to high
transitions; it is able to deliver more than 1 mA, at an output voltage of up to 0.9 VCC, into an
80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the
internal pull-up resistor and the load current. The current to and from the card I/O lines is
limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
6.5
Inactive mode
After a power-on reset, the circuit enters inactive mode. A minimum number of circuits are
active while waiting for the microcontroller to start a session:
– All card contacts are inactive (approximately 200 Ω to GND)
– Pins I/OUC, AUX1UC, and AUX2UC are in the high impedance state (11 kΩ pull-up
resistor to VDD). Applies only to SO-28 and TSSOP-28 packages.
– Voltage generators are stopped
– XTAL oscillator is running
– Voltage supervisor is active
– The internal oscillator is running at its low frequency.
6.6
Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF and CMDVCC, as shown in Table 22.
If the card is in the reader (this is the case if PRES or PRES is active), the system
microcontroller can start a card session by pulling CMDVCC low. The following sequence
then occurs (see Figure 6):
1. CMDVCC is pulled low and the internal oscillator changes to its high frequency (t0).
2. The step-up converter is started (between t0 and t1).
3. VCC rises from 0 to 5 V (or 1.8 V, 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where
T is 64 times the period of the internal oscillator (approximately 25 µs).
4. I/O, AUX1, and AUX2 are enabled (t3 = t1 + 4T) (these were pulled low until this
moment).
5. CLK is applied to the C3 contact of the card reader (t4).
6. RST is enabled (t5 = t1 + 7T).
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Functional description
ST8024L
The clock may be applied to the card using the following sequence (see Figure 5):
1. Set RSTIN high.
2. Set CMDVCC low.
3. Reset RSTIN low between t3 and t5; CLK starts at this moment.
4. RST remains low until t5, when RST is enabled to be the copy of RSTIN.
5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK
pulses before toggling RST.
If the applied clock is not needed, then CMDVCC may be set low with RSTIN low. In this
case, CLK starts at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN may
be set high in order to obtain an “answer to request” (ATR) from the card.
Activation should not be performed with RSTIN held permanently high.
Note:
It is recommended that no control smartcard signals are to be shared with any other
devices. Sharing may result in inadvertent activation or deactivation of the smartcard.
Table 22.
Card presence indicator
Figure 5.
22/35
OFF
CMDVCC
Indication
H
H
Card present
L
H
Card not present
Activation sequence using RSTIN and CMDVCC
Doc ID 17709 Rev 5
ST8024L
Functional description
Figure 6.
Activation sequence at t3
6.7
Active mode
When the activation sequence is completed, the ST8024L is in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024L is designed for cards without VPP (the voltage required to program or erase
the internal non-volatile memory).
6.8
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1.
2.
RST goes low (t10).
CLK is held low (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal
oscillator (approximately 25 µs).
3.
I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).
4.
VCC starts to fall towards zero (t14 = t10 + 1.5 x T).
5.
The deactivation sequence is complete at tDE, when VCC reaches its inactive state.
6.
All card contacts become low impedance to GND; I/OUC, AUX1UC, and AUX2UC
remain at VDD (pulled-up via an 11 kΩ resistor).
7.
The internal oscillator returns to its lower frequency.
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Functional description
Figure 7.
Deactivation sequence
6.9
VCC generator
ST8024L
The VCC generator has a capacity to supply up to 80 mA (max.) continuously at 5 V,
65 mA (max.) at 3 V, and 45 mA (max.) at 1.8 V. An internal overload detector operates at
approximately 120 mA. Current samples to the detector are internally filtered, allowing
spurious current pulses up to 200 mA with a duration in the order of µs to be drawn by the
card without causing deactivation. The average current must stay below the specified
maximum current value. For reasons of VCC voltage accuracy, a 100 nF capacitor with an
ESR < 350 mΩ should be tied to CGND near to pin VCC, and a 100 nF capacitor with the
same ESR should be tied to CGND near card reader contact C1.
24/35
Doc ID 17709 Rev 5
ST8024L
6.10
Functional description
Fault detection
The following fault conditions are monitored:
●
Short-circuit or high current on VCC
●
Removal of a card during a transaction
●
VDD dropping
●
Step-up converter operating out of the specified values (VDDP too low or current from
VUP too high)
●
Overheating
●
There are two different cases (see Figure 8):
–
CMDVCC high outside a card session. Output OFF is low if a card is not in the
card reader, and high if a card is in the reader. A voltage drop on the VDD supply is
detected by the supply supervisor, this generates an internal power-on reset pulse
but does not act upon OFF. No short-circuit or overheating is detected because the
card is not powered-up.
–
CMDVCC low within a card session. Output OFF goes low when a fault condition
is detected. As soon as this occurs, an emergency deactivation is performed
automatically (see Figure 9). When the system controller resets CMDVCC to high,
it may sense the OFF level again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card extraction (OFF goes high
again if a card is present).
Depending on the type of card-present switch within the connector (normally closed or
normally open) and on the mechanical characteristics of the switch, bouncing may occur on
the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 8).
When a card is inserted, output OFF goes high only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed on
the first true/false transition on PRES or PRES and output OFF goes low.
Figure 8.
Behavior of OFF, CMDVCC, PRES, and VCC
Doc ID 17709 Rev 5
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Functional description
Figure 9.
6.11
ST8024L
Emergency deactivation sequence (card extraction)
VCC selection settings
The ST8024L supports three smartcard VCC voltages: 1.8 V, 3 V, and 5 V. The VCC selection
is controlled by the 1.8V and 5V/3V signals as shown in Table 23. The 1.8V signal has
priority over the 5V/3V. When the 1.8 V pin is taken high, VCC is 1.8 V and it overrides any
setting on the 5V/3V pin.
When the 1.8V pin is taken low, the 5V/3V pin selects the 5 V or 3 V VCC. If the 5V/3V pin is
taken high, then VCC is 5 V, and if the 5V/3V pin is taken low then VCC is 3 V.
Table 23.
26/35
VCC selection settings
5V/3V pin
1.8V pin
VCC output
0
0
3V
1
0
5V
x
1
1.8 V
Doc ID 17709 Rev 5
ST8024L
7
Applications
Applications
Figure 10. Hardware hookup
1. These capacitors must be < 350 mΩ ESR and be placed near the IC (within 10 mm).
2. ST8024L and the microcontroller must use the same VDD supply.
3. Make short, straight connections between CGND, C5, and the ground connection to the capacitor.
4. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to pin VCC.
5. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to C1 contact.
6. The connection to C3 should be routed as far as possible from C2, C7, C4, and C8 and, if possible, surrounded by
grounded tracks.
7. This is the optional resistor divider for changing the threshold of VDD when using the PORADJ function. If this divider is not
required, pin 18 should be connected to ground.
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Package mechanical data
8
ST8024L
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Figure 11. SO-28 small outline, package mechanical drawing
0016572_F
Table 24.
SO-28 small outline, package mechanical data
Dimensions
Symbol
mm.
Min.
Typ.
A
Max.
Min.
Typ.
2.65
Max.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
c1
0.020
45° (typ.)
D
17.70
18.10
0.697
0.713
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
16.51
0.650
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
S
28/35
inches
8° (max.)
Doc ID 17709 Rev 5
ST8024L
Package mechanical data
Figure 12. TSSOP-20 package mechanical drawing
A
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
Table 25.
0087225_D
TSSOP-20 package mechanical data
Dimensions
Symbol
mm.
Min.
Typ.
A
inches
Max.
Min.
Typ.
1.2
A1
0.05
A2
0.8
b
Max.
0.047
0.15
0.002
1.05
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
1
0.65 BSC
K
0°
L
0.45
0.60
0.006
0.039
0.041
0.0256 BSC
8°
0°
0.75
0.018
Doc ID 17709 Rev 5
8°
0.024
0.030
29/35
Package mechanical data
ST8024L
Figure 13. TSSOP-28 package mechanical drawing
0128292_D
Table 26.
TSSOP-28 package mechanical data
Dimensions
Symbol
mm.
Min.
Typ.
A
Max.
Min.
Typ.
1.2
A1
0.05
A2
0.8
b
Max.
0.047
0.15
0.002
1.05
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
9.6
9.7
9.8
0.378
0.382
0.386
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
30/35
inches
1
0.65 BSC
K
0°
L
0.45
0.60
0.006
0.039
0.041
0.0256 BSC
8°
0°
0.75
0.018
Doc ID 17709 Rev 5
8°
0.024
0.030
ST8024L
Package mechanical data
Figure 14. SO-28 tape and reel schematic
Note: Drawing is not to scale.
Table 27.
SO-28 tape and reel mechanical data
Dimensions
Symbol
mm.
Min.
A
Typ.
inches
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
30.4
0.519
1.197
AO
10.8
11.0
0.425
0.433
BO
18.2
18.4
0.716
0.724
KO
2.9
3.1
0.114
0.122
PO
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
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Package mechanical data
ST8024L
Figure 15. TSSOP-20 tape and reel schematic
Note: Drawing is not to scale.
Table 28.
TSSOP-20 tape and reel mechanical data
Dimensions
Symbol
mm.
Min.
A
Max.
Min.
330
13.2
Typ.
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
32/35
Typ.
inches
0.504
22.4
0.519
0.882
AO
6.8
7
0.268
0.276
BO
6.9
7.1
0.272
0.280
KO
1.7
1.9
0.067
0.075
PO
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Doc ID 17709 Rev 5
ST8024L
Package mechanical data
Figure 16. TSSOP-28 tape and reel schematic
Note: Drawing is not to scale.
Table 29.
TSSOP-28 tape and reel mechanical data
Dimensions
Symbol
mm.
Min.
A
Typ.
inches
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
22.4
0.519
0.882
AO
6.8
7
0.268
0.276
BO
10.1
10.3
0.398
0.406
KO
1.7
1.9
0.067
0.075
PO
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
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Revision history
ST8024L
9
Revision history
Table 30.
Document revision history
Date
Revision
19-Jul-2010
1
Initial release.
30-Jul-2010
2
Updated Description, Table 6.
27-Sep-2010
3
Updated Features, Table 1, 6, 8, 19, 20, Section 6.1,
Section 6.2.2, Section 6.6, Section 6.9, footnotes of Figure 10.
4
Added ST8024LACTR device, updated Features, Table 1,
Section 1: Description (moved to page 5), Figure 1,Figure 2,
Table 2, Table 6,Table 8, Section 6.1 to Section 6.3, Figure 10
and Disclaimer, minor text corrections throughout document.
5
Updated Figure 1, Table 2, Table 3, Table 6, Table 8, Table 14,
Table 16, Table 17, Section 6.1, moved notes from Section 5
below Table 3, Table 8, Table 15, Table 16, Table 17, minor
text corrections throughout document.
09-Feb-2012
04-May-2012
34/35
Changes
Doc ID 17709 Rev 5
ST8024L
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