cd00285343

AN3275
Application note
Improving the performance of smartcard interfaces
using the ST8024L
Introduction
The ST8024L is a smartcard interface offered as a drop-in replacement for the ST8024
device. Enhancements and changes to the ST8024L device include:
●
Improved performance by reducing the noise sensitivity in the charge pump
●
Incorporated 1.8 V VCC output
●
Lower VTH threshold voltage
This application note provides information and suggestions for the optimal use and
performance of the ST8024L smartcard interface, including PCB layout, external component
placement, and connections (see ST8024L application hardware guidelines on page 18).
The implementation of all the blocks and procedures for card activation and deactivation
(see Figure 1) of the smartcard are also explained.
The ST8024L is a smartcard interface designed to minimize microprocessor hardware and
software complexity in all applications that require a smartcard (e.g., set-top box, electronic
payment, pay TV, and identification cards). The electrical characteristics of the ST8024L are
in accordance with New Digital Systems (NDS) and compliant with ISO7816-3, GSM11.11,
and EMV 4.0. Two devices (ST8024LCDR and ST8024LCTR) in the ST8024L family have
been certified by NDS.
Figure 1.
ST8024L internal block diagram
VDD
VDDP
100nF
100nF
21
6
SUPPLY
VDD
Vref
(1)
R1
18
OFF
5
8
VUP
100nF
POWER_ON
EN2
23
VCC
PVCC GENERATOR
20
EN5
3
CLKDIV2(1)
1
CLKDIV2(2)
2
HORSEQ
SEQUENCER
14
RST
BUFFER
EN4
CLOCK
BUFFER
CLOCK
CIRCUITRY
17
16
15
10
CLK
XTAL1
PGND
EN1 CLKUP
ALARM
CMDVCC
XTAL2(2)
4
INTERNAL OSCILLATOR
2.5 MHz
19
5V/3V
C1+
7
VOLTAGE SENSE
R2(1)
RSTIN
C1–
STEP-UP CONVERTER
INTERNAL
REFERENCE
PORADJ/1.8V
100nF
9
VCC
100nF
CGND
RST
CLK
PRES
PRES(2)
24
25
OSCILLATOR
EN3
THERMAL
PROTECTION
ST8024L
AUX1UC(2)
27
I/O
TRANSCEIVER
13
AUX1(2)
AUX2UC(2)
28
I/O
TRANSCEIVER
12
AUX2(2)
26
I/O
TRANSCEIVER
11
I/OUC
I/O
22
GND
October 2010
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www.st.com
Contents
AN3275
Contents
1
Activation/deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Card clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Emergency deactivation/fault detection . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
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3.1
PORADJ VDD undervoltage without external resistor bridge . . . . . . . . . . . 9
3.2
PORADJ VDD undervoltage with external divider . . . . . . . . . . . . . . . . . . . 11
3.3
Fault on card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
VCC short-circuit fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
VDDP drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Overtemperature fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST8024L application hardware guidelines . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Power supply optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Clock section optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3
Smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4
Input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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AN3275
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
CLK division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resistor values for VTH(ext)fall trip point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPORADJ trip point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of figures
AN3275
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
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ST8024L internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ST8024L activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Card activation/deactivation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CLKDIV change clock duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ST8024L automatic deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External resistor bridge applied to PORADJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VTH(ext) rise (external rising threshold voltage on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VTH(ext) fall (external falling threshold on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ST8024L activation sequence (after tdebounce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ST8024L current supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ISC short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Deactivation caused by VDDP drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST8024L application PCB top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ST8024L application PCB bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Step-up converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ST8024L application PCB storage and pumping capacitors . . . . . . . . . . . . . . . . . . . . . . . 22
ST8024L application PCB crystal (XTAL) connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ST8024L application PCB smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ripple on VCC output voltage, 80 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ripple on VCC output voltage, 65 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ripple on VCC output voltage, 50 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST8024L application PCB schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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1
Activation/deactivation sequence
Activation/deactivation sequence
The core of the ST8024L is the sequencer (shown in Figure 1 on page 1) that must
coordinate the Enable signals for the activation and deactivation sequence as well as check
for possible fault conditions. The smart card is basically a microcontroller and needs to be
activated/deactivated by a correct sequence as required by the ISO/IEC7816 standard. The
ST8024L activation and deactivation sequences are shown in Figure 2 and Figure 3 on
page 6, respectively. Please refer to the ST8024L datasheet for details.
Figure 2 shows the activation sequence (the card is active) and CMDVcc taken from high to
low. The activation sequence starts and the first block to be enabled is the step-up converter
(VUP), linked to En1 (see Figure 1), while the last enabled signal is RST that allows the card
software to start.
Figure 3 shows the deactivation sequence (when CMDVcc goes high). The circuit executes
an automatic deactivation sequence, finishing in the inactive state after tde (deactivation
time).
Figure 2.
ST8024L activation sequence
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Activation/deactivation sequence
Figure 3.
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Deactivation sequence
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AN3275
Activation/deactivation sequence
Figure 4.
Card activation/deactivation flowchart
Start
No
OFF pin = VDD
Error message
“No Card”
Set CMDVcc
from high to low
End
Initiate activation
Charge pump is ON
Regulator is ON
I/O is enabled
CLK is active
Fault detection
OFF pin = GND
Set RSTIN
from low to high
Start card
communication
No
Yes
Alarm error message
“Error during
communication”
No alarm
Completed
Set CMDVcc
from low to high
Initiate deactivation
RST goes low
CLK is disabled
I/O is disabled
Regulator is OFF
Charge pump is OFF
Initiate deactivation
RST goes high
CLK is disabled
I/O is disabled
Regulator is OFF
Charge pump is OFF
Set CMDVcc
from low to high
End
End
AM04943v1
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Card clock
2
AN3275
Card clock
The card clock signal (CLK) is present on the CLK pin when the ST8024L is activated. It is
linked to the internal En4 signal (see Figure 1 on page 1) and its frequency is obtained
according to the settings in Table 1.
According to the ISO/IEC7816 specifications, the CLK duty cycle must be guaranteed
between 45% and 55%, even when the status of CLKDIV1 or CLKDIV2 changes. Figure 5
shows how the ST8024L ensures duty cycle accuracy by waiting for completion of a whole
clock cycle before changing the frequency (CLKDIV1 change, rising edge of CH2). The
output duty cycle is 50% ±5%, even if the clock division changes.
The card clock signal (CLK) can be established by connecting a crystal (“XTAL”) between
the XTAL1 and XTAL2 pins, or by an external signal applied to the XTAL1 pin. In this case,
the XTAL2 pin must be left floating. The external signal voltage level must be limited
between GND and VDD voltage.
Table 1.
Figure 5.
CLK division factor
CLKDIV1
CLKDIV2
fclk
0
0
1/8 fXTAL
0
1
1/4 fXTAL
1
1
1/2 fXTAL
1
0
fXTAL
CLKDIV change clock duty cycle
CH1 = output CLK waveform
CH2 = CLKDIV1 pin
Conditions: VDD = 3.3 V; VDDP = 5 V; 5/3V = H
Mode: ACTIVE
fXTAL = 10 MHz; CLKDIV2 = 0 V
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3
Emergency deactivation/fault detection
Emergency deactivation/fault detection
ST8024L is equipped with a fault detection circuitry which monitors the following conditions
(see Figure 1 on page 1):
3.1
●
VDD undervoltage
●
Fault on card removal
●
VCC short-circuit
●
VDDP drop, and
●
Overtemperature
PORADJ VDD undervoltage without external resistor bridge
The PORADJ pin can be used to provide early detection of power failure on VDD. The
ST8024L logic circuitry is supplied by VDD. In order to avoid voltage spikes that could cause
damage or malfunction of the device and/or card, a voltage supervisor block is embedded
(see Figure 1). This block monitors VDD and when it gets lower than VTH2 (falling threshold
voltage on VDD, 2.45 V, typ), the supervisor immediately starts the deactivation sequence
and VCC goes low.
As VDD goes higher than VTH2 + VHYS2, (VHYS2 is the hysteresis of threshold voltage,
100 mV, typ), after a certain amount of time (tw + tdebounce, where tw is the internal power-on
reset pulse width, 8 ms typ, see Figure 6 on page 10), CMDVcc goes low. The activation
sequence starts and VCC goes high. The PORADJ pin can be left floating, but connecting it
to GND to avoid capturing noise is recommended.
Note:
See Fault on card removal on page 14 for tdebounce feature details.
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Emergency deactivation/fault detection
Figure 6.
AN3275
ST8024L automatic deactivation sequence
CH1 = CMDVcc
CH2 = VCC
CH3 = OFF
CH4 = VDD
Conditions: VDD = 3.3 V; VDDP = 5 V; 5/3V = H
Mode: ACTIVE
fXTAL = 10 MHz; CLKDIV2 = 0 V
Note:
Deactivation: VTH2 ≈2.393 V.
Activation: As VDD ≥ VTH2 + VHYS2 (≈2.498 V) and CMDVcc goes low, VCC goes high.
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3.2
Emergency deactivation/fault detection
PORADJ VDD undervoltage with external divider
In this case, a resistor bridge is applied to the PORADJ pin (see Figure 7). VTH(ext) rise and
VTH(ext) fall are the external rising threshold voltage and the external falling threshold voltage
on VDD, respectively. They are the voltages on pin PORADJ that switch the device on and
off. By knowing these values and using the formula:
VPORADJ =(R2/R1 + R2) x VDD
it is possible to set R1 and R2 such that the device powers on and off at the values of VDD
desired by the user (R1 + R2 = 100 kΩ typ).
In particular, R1 and R2 have to be set so that, when VDD is getting low, before turning the
microcontroller off, the smartcard has to be switched off properly as well. The same is true
for the microcontroller startup in that the smartcard has to be turned on after the
microcontroller. Figure 8 and Figure 9 on page 13 show the VTH(ext) rise and VTH(ext) fall on
the PORADJ pin (1.196 V and 1.155 V, respectively).
The VTH(ext)fall threshold of the ST8024L is slightly lower (80 mV typ.) than the ST8024
device. If for example, the microcontroller is shut down at 2.5 V, appropriate resistor values
must be chosen to ensure proper deactivation of the ST8024L device.
Table 2 shows an example of the resistor values between the ST8024 and ST8024L devices
if the microcontroller is shut down at 2.5 V.
Table 2.
Resistor values for VTH(ext)fall trip point
ST8024
ST8024L
R1
50 kΩ
55.5 kΩ
R2
50 kΩ
44.5 kΩ
VTH(ext)fall
1.25 V
1.14 V
Table 3.
VPORADJ trip point
VPORADJ
VDD
ST8024
ST8024L
5.0
2.500
2.275
4.5
2.250
2.048
4.0
2.000
1.820
3.5
1.750
1.593
3.0
1.500
1.365
2.5
1.250
1.138
2.0
1.000
0.910
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Emergency deactivation/fault detection
AN3275
As long as VDD gets the proper startup value (so that VTH(ext) rise = 1.196 V), OFF goes low
for tw + tdebounce (tw ≈16 ms, in this case). During this time, the device cannot be turned on
by CMDVcc. To turn the device on, CMDVcc must go low for at least approximately 16 ms
(while OFF is high).
Figure 7.
External resistor bridge applied to PORADJ
VDD
R1
To PORADJ
R2
GND
AI11885
Figure 8.
VTH(ext) rise (external rising threshold voltage on VDD)
CH1 = CMDVcc
CH2 = VCC
CH3 = OFF
CH4 = VTH(ext) rise
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Emergency deactivation/fault detection
Figure 9.
VTH(ext) fall (external falling threshold on VDD)
CH1 = CMDVcc
CH2 = VCC
CH3 = OFF
CH4 = VTH(ext) fall
Note:
When VTH(ext) fall = 1.155 V, the device starts switching off and VCC goes low.
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Emergency deactivation/fault detection
3.3
AN3275
Fault on card removal
If the smartcard is pulled out from its socket (PRES goes high or PRES goes low), the
deactivation sequence starts. The OFF pin goes low and the device switches off (see
Figure 10). In order to avoid bouncing on the PRES (or PRES) signal at card insertion or
extraction, as the card is inserted again, OFF goes high just after a period tdebounce (≈8 ms).
If CMDVcc goes low before this time, after card insertion, it will not initiate the activation.
CMDVcc must wait for tdebounce before toggling from high to low to initiate the activation.
Figure 11 on page 14 shows the start of the activation sequence after tdebounce has elapsed.
Figure 10. Card extraction
Figure 11. ST8024L activation sequence (after tdebounce)
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3.4
Emergency deactivation/fault detection
VCC short-circuit fault protection
The ST8024L is able to supply the card with current pulses of about 140 mA for no longer
than 5.5 µs, typical (see Figure 12 and Figure 13 on page 16).
Short-circuit protection is an important interface feature that warns the sequencer block if
the output current is higher than the short-circuit current limit (≈120 mA) for too long. This
characteristic allows the device to supply the card with current pulses higher than the
maximum allowed, if their duration is not too long. If the current pulses last for more than
5.5 µs, the deactivation sequence starts to protect the card. The OFF pin goes low so as to
warn the microcontroller about the overcurrent fault. The sequence in Figure 13 on page 16
shows how the current pulse becomes long enough to activate the short-circuit protection.
Figure 12. ST8024L current supply sequence
CH1 = CMDVcc
CH2 = ISC pulse
CH3 = VCC
CH4 = OFF
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Emergency deactivation/fault detection
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Figure 13. ISC short-circuit protection
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3.5
Emergency deactivation/fault detection
VDDP drop
The voltage supervisor also monitors the drop in VDDP. When VDDP falls below the minimum
threshold (see Figure 14), the deactivation sequence starts. The OFF pin goes low and VCC
goes off.
Figure 14. Deactivation caused by VDDP drop
CH1 = VDDP
CH2 = CMDVcc
CH3 = VCC
CH4 = OFF
3.6
Overtemperature fault protection
Overtemperature protection is another important interface feature that warns the sequencer
block of fault events. If the temperature is higher than the shutdown temperature (150 °C,
typ), the deactivation sequence starts to protect the card. The OFF pin goes low so as to
warn the microcontroller about the overtemperature fault.
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ST8024L application hardware guidelines
4
AN3275
ST8024L application hardware guidelines
This section contains some optimization guidelines concerning PCB layout as well as
external component placement and connections. The referenced application board in
Figure 15 and Figure 16 on page 19 has two layers and uses these guidelines to meet NDS
application requirements (refer to Figure 24 on page 29).
The PCB layout provides completely separate supply and GND copper planes, which allow
each plan to act as a shield for each group of noise-sensitive device pins. The PGND, and
CGND and GND planes share a common point on the bottom layer of the PCB (see top,
Figure 16 on page 19).
Figure 15. ST8024L application PCB top layer
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ST8024L application hardware guidelines
Figure 16. ST8024L application PCB bottom layer
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ST8024L application hardware guidelines
4.1
AN3275
Power supply optimization
The ST8024L devices support three smartcard VCC voltages: 1.8 V, 3.0 V and
5.0 V. The ST8024LCDR and ST8024LCTR only support 3.0 V and 5.0 V VCC. The VCC
selection is controlled by the supply voltage selector pin 5V/3V (pin 3) as shown in Figure 1
on page 1. If the 5V/3V pin is connected to VDD, the VCC voltage is 5 V and VCC is 3 V if
5V/3V pin is connected to GND.
The ST8024LACDR and ST8024LTR support all 3 supply card voltages and are available in
the SO-28 and TSSOP-20 packages. The VCC selection is controlled by the supply voltage
selector pins 5V/3V (pin 3) and 1.8V (pin 18). The 1.8 V signal has priority over the 5V/3V
pin. When the 1.8V pin is connected to VDD, the VCC voltage is 1.8 V and it overrides any
setting on the 5V/3V pin. When the 1.8V pin is connected to GND, the 5V/3V pin selects the
5 V or 3 V VCC.
Table 4.
VCC selection settings
5V/3V
1.8V pin
VCC output
0
0
3V
1
0
5V
x
1
1.8 V
A step-up converter supplied by VDDP is used for the VCC voltage generation. It doubles the
input voltage VDDP or follows it, depending on the 5/3V and VDDP values:
●
5/3V = H and VDDP > 5.8 V; voltage follower
●
5/3V = H and VDDP < 5.7 V; voltage doubler
●
5/3V = L and VDDP > 4.1 V; voltage follower
●
5/3V = L and VDDP < 4.0 V; voltage doubler
The C1– and C1+ pins are used for duplicating the supply voltage VDDP by using the 100 nF
pumping capacitor (C4). The charge pump output pin (VUP) has to be connected to a 100 nF
storage capacitor (C5) to stabilize the voltage.
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ST8024L application hardware guidelines
Figure 17. Step-up converter block diagram
100nF
100nF
C1+
C1–
6
7
5
PGND
ON/OFF
OUTPUT
100nF
VUP
Step-up
Mode
Selector
L
ST8024L
EN2
VCC
Regulator
17
VCC
PVCC
AM04942v1
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ST8024L application hardware guidelines
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A small amount of noise is introduced into the design because of the switching circuitry. In
order to reduce it and improve the efficiency of the step-up converter, the capacitors must be
connected as closely as possible to the pins (see Figure 18). An Equivalent Series
Resistance (ESR) < 350 mΩ at 100 kHz is recommended.
The evaluation board is equipped with MURATA GRM31M7U1H104JA01B capacitors.
However, other capacitors with an ESR of up to 350 mΩ at 100 kHz are sufficient to work
within the specifications.
Figure 18. ST8024L application PCB storage and pumping capacitors
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4.2
ST8024L application hardware guidelines
Clock section optimization
Recommendations for the PCB design clock area include:
●
The XTAL should be connected as closely as possible to the XTAL pins to reduce signal
reflections, especially for high frequency applications (see Figure 19).
●
Two compensation capacitors (C9 and C10), each 15 pF (typ) can improve the
oscillator startup performance. Even without these additional capacitors the CLK duty
cycle is guaranteed between 45% and 55% (according to the NDS specifications), with
frequencies up to 26 MHz.
Figure 19. ST8024L application PCB crystal (XTAL) connection
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ST8024L application hardware guidelines
4.3
AN3275
Smartcard connections
In typical applications, a 100 nF filter capacitor (C3) is connected to the VCC output towards
GND/CGND, near the ST8024L pins. A second 100 nF capacitor (C8) is connected between
the card socket pins C1 (VCC) and C5 (CGND), near the card slot (see Figure 20). In order
to reduce noise and avoid coupling effects, the wire length between the ST8024L and card
should be as short as possible.
Another recommendation is to keep the CLK track far away from the other signal tracks to
limit coupling with the transceiver lines. Further decoupling is gained if the clock track is
shielded by a GND/CGND plane or track on the PCB.
Keeping the PGND and GND/CGND planes as large as possible improves power supply
noise rejection. With this in mind, the board design should connect these planes with a large
number of vias between the top and bottom board layers (3-4 vias per cm2).
The ST8024L has been enhanced to reduce the noise sensitivity in the charge pump and to
improve the performance of the device. The VCC spikes are much lower than 350 mVPP
even when a pulsed load of up to 80 mA is applied with VCC = 5 V, up to 65 mA with
VCC = 3 V and up to 50 mA with VCC = 1.8 V. Figure 21 on page 26 shows a typical VCC
output waveform where an 80 mA pulsed load is applied and the measured ripple is lower
than 95 mV. With a 65 mA pulsed load applied, the measured ripple is less than 65 mV, and
when a 50mA pulsed load is applied, the measured ripple is less than 55 mV.
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ST8024L application hardware guidelines
Figure 20. ST8024L application PCB smartcard connections
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ST8024L application hardware guidelines
Figure 21. Ripple on VCC output voltage, 80 mA pulsed load
VDD = 3.3 V
VDDP = 5.5 V
CH1 = Ripple on VCC output voltage
CH2 = 80 mA pulsed current ICC
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ST8024L application hardware guidelines
Figure 22. Ripple on VCC output voltage, 65 mA pulsed load
VDD = 3.3 V
VDDP = 5.5 V
CH1 = Ripple on VCC output voltage
CH2 = 65 mA pulsed current ICC
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ST8024L application hardware guidelines
Figure 23. Ripple on VCC output voltage, 50 mA pulsed load
VDD = 3.3 V
VDDP = 5.5 V
CH1 = Ripple on VCC output voltage
CH2 = 50 mA pulsed current ICC
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1
2
3
4
5
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1
PRES
JP17
J8
GND-PRES
100nF
C5
J2 pins
2-3
1-4
J1 pins
1-5
2-5
Pin 2 of JP17 to J8
PRES conf.
and SW kind
+PRES (SW N.C.)
–PRES (SW N.O.)
No Switch
2
U2
9
10
5
6
7
8
C8
C3
100nF
100nF
VCC
RST
CLK
AUX1
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
GND
VDD
RSTIN
CMDVCC
PORADJ
VCC
RST
CLK
SMARTCARD CONNECTOR
K1
K2
GND
NC
I/O
AUX2
U1
ST8024L
CLKDIV1
CLKDIV2
5V/3V
GNDP
S2
VDDP
S1
VUP
PRES
PRES
I/O
AUX2
AUX1
CGND
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3
4
N.C. or N.O. switch is included in the Smartcard connector.
Please select JP17 as specified in the PRES configuration.
1
2
3
4
C4
5
6
100nF 7
8
9
10
11
12
13
14
AUX1UC
AUX2UC
CLKDIV1
CLKDIV2
1
2
3
PRES config (JP17)
Please connect the 2 jumpers as follows:
100nF
C2
1
2
3
I/OUC
VCC
10pF
C10
10pF
J7
T.P. card K
Y1
10MHz
C9
5
J3
VDD
100nF
C1
47µF
C6
+
A
B
C
R6
10KΩ
330nF
C12
5/3V
1
2
3
+
47µF
1
2
3
C7
J2
GND
1
2
3
4V ÷ 6.5V
1
2
3
5
RSTIN
2.7V - 6.5V
1
2
3
4
VTHSEL
CMDVCC
1
2
3
J1
VDDP
3
1
2
3
2
6
6
–OFF
1
2
3
D
1
A
B
C
D
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ST8024L application hardware guidelines
Figure 24. ST8024L application PCB schematic
AI11898
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ST8024L application hardware guidelines
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Input and output connections
The three data lines of the smartcard signals are pulled high via an 11 kΩ resistor through
VCC and the three data lines of the microcontroller signals I/OUC, AUX1UC and AUX2UC
are pulled high via an 11 kΩ resistor through VDD, thus allowing operation when VCC is not
equal to VDD.
The device and the microcontroller must use the same VDD supply. Pins CLKDIV1,
CLKDIV2, RSTIN, PRES, I/OUC, AUX1UC, AUX2UC, 5V/3V, 1.8V, CMDVcc and OFF are
referenced to VDD. If the XTAL1 pin is to be driven by an external clock, also reference this
pin to VDD.
It is recommended that no control smartcard signals are to be shared with any other
devices. Sharing could result in inadvertent activation or deactivation of the smartcard.
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5
Revision history
Revision history
Table 5.
Document revision history
Date
Revision
04-Oct-2010
1
Changes
Initial release.
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