AN636: Si5214x and Si5315x Signal Integrity Tuning to Improve Connectivity

AN636
Si5214 X A N D Si5315 X S IGNAL I N T E G R I T Y TUNING T O
I MPROVE C ONNECTIVITY
1. Introduction
In today's high-speed semiconductor technology, interfacing the high-speed components poses a major challenge.
The output driver is one of the crucial components for determining device performance and successful interfacing.
High-speed systems with tighter timing budgets require high rise and fall times (i.e., faster slew rates, specific skew
requirements, and excellent signal quality).
In many high-speed integrated circuit environments, interfacing issues are faced across input-output buffers. In
addition, the circuit board layout or traces are likely to add to the interfacing problems. For better performance in
the end application, Silicon Labs products offers flexibility in adjusting slew rate (Tr, Tf), skew adjustments, and
output impedance selections to improve connectivity on the application board.
Silicon Labs' high-speed clocks come with an option to adjust these ac parameters through I2C/SMBus
connectivity. By using the factory programming methodology of OTP programming, the specific user requirements
can be made the default performance at power on. This application note discusses how to fine tune the ac
parameters through I2C/SMBus for better performance.
2. Programming AC Performance Registers
To alter the ac performance of an output, certain registers corresponding to the output need to be altered.
Depending on the signaling type, there are two sets of control registers: single ended control registers and
differential control registers. Differential signals have two sets of registers: Register A and Register B. Currently the
PCIe products support single ended outputs at default 3.3 V and LVCMOS differential outputs only.
2.1. Slew Rate
Silicon Labs' PCIe clocks allow the user the option of programmable rise/fall times (slew rate) by varying the drive
strength of the output buffers. It is possible to control rise times and fall times differently to suit board indiscretions
or as per receiving unit's timing budget, which may be a CPU, GPU, PCI-Express controller, chipset or any other
device requiring clocking input. For the differential outputs, the slew rate can be adjusted in coarse and fine
regulation using Register A[bit 1].
2.2. Skew (for Differential Outputs)
The PCIe family clocks allow the user to customize the skew on the differential signal to adjust the skew with
respect to other clocking signals. Also, the skew parameter on true and complement can be controlled individually
to assist with cross point optimization. Unstable or unmatched cross point causes data loss and high common
mode energy which induces EMI. The cross point can be balanced using this feature to minimize these
imperfections by programming 0 skew between true and complement signals.
Rev. 0.1 1/12
Copyright © 2012 by Silicon Laboratories
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2.3. Output Impedance
The output impedance of load along with the trace may vary from what is expected and result in overshoots and
undershoots or ripples in the clock output waveform. These ripples can be minimized by adjusting the output
impedance of the particular clock output under consideration. Each clock output has individual impedance and
other parameters control independent of other outputs.
2
Rev. 0.1
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3. Parameter Control Registers
3.1. Single Ended Control Register
Bit
Name
Type
D7
D6
OP_IMP[1] OP_IMP[0]
R/W
Bit
Name
7:6
OP_IMP[1:0]
R/W
D5
D4
D3
INV
SLEW[1]
SLEW[0]
R/W
R/W
R/W
D2
D1
D0
R/W
R/W
R/W
Function
Output Impedance Control.
00: High-Z
01: 50 
10: 25  (default)
11: 17 
5
INV
Inverts clock output.
4:3
SLEW[1:0]
Slew Rate Control.
Byte18[7:6] = 11 Byte18[7:6] = 10 Byte18[7:6] = 01
2:0
Reserved
17 
25 
50 
Byte18[4:3]
Setting
Slew Rate (ns)
Slew Rate (ns)
Slew Rate (ns)
00
Slowest
0.868
1.004
1.531
01
Slow
0.775
0.917
1.449
10
Fast
0.548
0.667
1.212
11
Fastest
0.475
0.579
1.109
Note: Do not change these bits while re-writing the register values.
Rev. 0.1
3
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3.2. Differential Control Registers
Register A
Bit
D7
Name
DIFF_IMP[1]
Type
R/W
D6
R/W
D5
D4
D3
D2
FALL_INC[1]
FALL_INC[0]
RISE_INC[1]
R/W
R/W
R/W
D1
D0
RISE_INC[0] COARSE_ SKEW_SEL_
FINE
COMP
R/W
R/W
R/W
Register B
Bit
D7
D6
D5
D4
Name DIFF_IMP[0]
Type
R/W
R/W
R/W
Bit
Bit Name
Description
7
DIFF_IMP
Configure differential
output impedance
6
4
R/W
Reserved
D3
D2
D1
D0
SKEW_INC[2]
SKEW_INC[1]
COARSE_
FINE
SKEW_SEL_
TRUE
R/W
R/W
R/W
R/W
Function
Register A
Bit 7
Register B
Bit 7
DIFF_IMP
0
0
High-Z
0
1
50  (default)
1
0
33 
1
1
20 
Register A
Bit 6
Register B
Bit 6
Reserved
Reserved
Reserved
Rev. 0.1
Note: Do not change
these bits while rewriting the register
values.
AN636
Bit
Bit Name
Description
5:4
FALL_INC[1:0]
Fall Time Increment
Function
Register A
Bit[5:4]
Fall time (ps) with
Register A
Bit 1 = 0
Fall time (ps) with
Register A
Bit 1 = 1
00
Nominal [default]
Nominal
01
+40 ps
+80 ps
10
+50 ps
+140 ps
11
+70 ps
+210 ps
Register B
Bit[5:4]
Reserved
3:2
RISE_INC[1:0]
Note: Do not change these bits while rewriting the register values.
Rise Time Increment
Register A
Bit[3:2]
00
01
10
11
SKEW_INC[1:0] Skew Time Increment
Register B
Bit[3:2]
00
01
10
11
Rev. 0.1
Rise time (ps) with Rise time (ps) with
Register A
Register A
Bit 1 = 1
Bit 1 = 0
Nominal [default]
Nominal
+40 ps
+80 ps
+50 ps
+140 ps
+70 ps
+210 ps
Skew (ps)
with Register B
Bit 1 = 0
Nominal
+ 20 ps
+ 50 ps
+ 70 ps
Skew (ps)
with Register B
Bit 1 = 1
+ 355 ps
+ 415 ps
+ 510 ps
+ 575 ps
5
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Bit
Bit Name
Description
1
COARSE_FINE
Set slew rate setting
to be coarse or fine
setting
Function
Register A
Bit[5:4]
0
1
Register B
Bit 1
0
1
0
SKEW_SEL
Set skew setting as
per Register B[3:2]
on True and Complement outputs
Register A
Bit 0
0
1
Register B
Bit 0
0
1
6
Rev. 0.1
Slew Rate Setting
Coarse slew rate adjust
Fine slew rate adjust
Skew Rate Setting
Fine skew adjust
Coarse skew adjust
SKEW_SEL_COMP
No skew added on Complement output
Add skew on Complement output as per
setting in Register B[3:2]
SKEW_SEL_TRUE
No skew added on True output
Add skew on True output as per setting in
Register B[3:2]
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4. Procedure to Vary AC Performance through I2C Bus
1. Power on the device and connect the output under test and I2C communication through appropriate
software like iPort Commlink.
2. Set the communication address to device address (usually D2'h). Make sure I2C connections are
communicating by reading back the registers starting from Register 0 and compare with data sheet
defaults.
3. Increase Register count to access beyond register 8 (for block read/write operation) by writing Register 4 to
80H.
4. Write Byte 63 (Byte 3F'h) to 01'h to access AC Performance Control page of the respective outputs through
I2C.
5. Select appropriate output or byte number to access from “Output-to-Register mapping” table. Read back
the content of selected register/registers. Note that the Single ended outputs have single control register
and Differential outputs have two control registers.
6. Modify only the bits for altering the ac performance of the output from Control Registers. Write back the
new register value to the same register number without altering the reserved bits in the register.
7. Monitor the change in parameter.
8. Note that power cycling the device in between from steps a to g will reset the parameter to default state and
the procedure needs to be started from step 1.
9. Finally, the user must write Byte 63 (Byte 3F'h) to 00'h to return to “Core” segment page of the Control
Registers. Otherwise, the addressed location remains in AC Performance Control block and for further
updates the changes do not take affect.
Rev. 0.1
7
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5. Output to Register Mapping Tables
5.1. Si52142 Output-to-Register Mapping
Si52143 Pin#
Output Description
Differential Output Control
Register A
Register B
Single Ended
Output Control
2
REF
—
—
18
13
DIFF0
51
52
—
14
DIFF0
15
DIFF1
16
DIFF1
—
53
54
—
—
5.2. Si52143 Output-to-Register Mapping
Si52143 Pin#
8
Output Description
Differential Output Control
Register A
Register B
Single Ended
Output Control
2
REF
—
—
18
8
DIFF0
43
44
—
9
DIFF0
10
DIFF1
11
DIFF1
13
DIFF2
14
DIFF2
15
DIFF3
16
DIFF3
—
49
50
—
—
51
52
—
—
53
54
—
—
Rev. 0.1
AN636
5.3. Si52144 & Si53154 Output-to-Register Mapping
Si52144/ Si53154
Pin#
Output Description
8
DIFF0
9
DIFF0
10
DIFF1
11
DIFF1
13
DIFF2
14
DIFF2
15
DIFF3
16
DIFF3
Differential Output Control
Register A
Register B
43
44
49
50
51
52
53
54
5.4. Si52146 & Si53156 Output-to-Register Mapping
Si52147/Si53159
Pin#
Output Description
9
DIFF0
10
DIFF0
11
DIFF1
12
DIFF1
14
DIFF2
15
DIFF2
17
DIFF3
18
DIFF3
19
DIFF4
20
DIFF4
22
DIFF5
23
DIFF5
Rev. 0.1
Differential Output Control
Register A
Register B
37
38
43
44
49
50
51
52
53
54
59
60
9
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5.5. Si52147 & Si53159 Output-to-Register Mapping
Si52147/Si53159
Pin#
10
Output Description
14
DIFF0
15
DIFF0
17
DIFF1
18
DIFF1
19
DIFF2
20
DIFF2
21
DIFF3
22
DIFF3
25
DIFF4
26
DIFF4
27
DIFF5
28
DIFF5
30
DIFF6
31
DIFF6
32
DIFF7
33
DIFF7
35
DIFF8
36
DIFF8
Rev. 0.1
Differential Output Control
Register A
Register B
37
38
43
44
45
46
49
50
51
52
53
54
59
60
61
62
67
68
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NOTES:
Rev. 0.1
11
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