AN699: FPGA Reference Clock Phase Jitter Specifications

AN699
FPGA R EFERENCE C LOCK P HASE J I T T E R S PECIFICATIONS
1. Introduction
Driven by market demand for ever-increasing network bandwidth, high-speed digital communications equipment
manufacturers look to communication semiconductor suppliers for the latest in high-speed standards-based digital
communications protocol building blocks. Several Field Programmable Gate Array (FPGA) vendors have taken up
this challenge and produced products specifically targeted to various segments of high-speed serial digital
communications designs. As a result, communications and embedded computing product designs are increasingly
utilizing FPGAs with embedded serializer-deserializers (SerDes) for critical high-speed transceiver and serial
protocol processing. Within high-speed serial digital communications, controlling, reducing, and maintaining low
signal path jitter is a paramount concern, especially as bit rates increase into the multi-gigabit realm and beyond.
FPGA vendors and system designers alike have become increasingly aware that low jitter digital communications
absolutely requires low or ultra-low jitter clocks. Silicon Labs timing solutions can easily meet the low jitter clocking
requirements for high-speed serial digital communications.
2. FPGA Clock Jitter Requirements
The vast majority of the FPGA market share is split between two companies, Xilinx and Altera. These two
companies have FPGA products that specifically address various high-speed serial digital communications market
segments. As a result of this market focus, these FPGA companies have published specifications for input
reference clock jitter requirements that allow their FPGA based products to implement spec-compliant serial digital
communications protocols. Although clock jitter can be specified in different forms, the almost universally accepted
format for high-speed serial digital communications links is that of a phase noise (jitter) mask in the frequency
domain. (For an excellent technical explanation of jitter and phase noise, refer to Silicon Labs’ application note
“AN687: A Primer on Jitter, Jitter Measurement and Phase-Locked Loops”.) Tables 1 and 2 provide the input
reference clock jitter specifications published by the two main FPGA vendors for FPGA products targeted for use in
high-speed serial digital communications. In addittion to these jitter requirements,Table 1 and Table 2 also provide
the jitter specifications for a selection of Silicon Labs’ timing devices. The selected devices include the Si51x 0.1–
250 MHz programmable XO, Si53x/Si570 10–1417 MHz programmable XO, the Si5338 any frequency, any-output
clock generator, and the Si5326/68 any-frequency jitter attenuating clock. As shown in the following tables, the
specified Silicon Labs timing devices easily meet or exceed the FPGA’s input reference clock jitter requirements
with substantial margin and are well suited for use in high-speed digital serial communications applications.
Rev. 0.1 7/12
Copyright © 2012 by Silicon Laboratories
AN699
AN699
Table 1. Silicon Labs Phase Jitter Performance vs. Xilinx Phase Jitter Requirements
Xilinx
Family
Ref Clock
Freq
(MHz)
Calculated Silicon Labs Jitter Performance
Phase Jitter over same Jitter Mask Points
(ps RMS)
from Mask
Data
(ps RMS)
1 MHz 10 MHz
Si51x Si5338 Si53x Si5326
Si57x Si5368
Phase Noise (dBc/Hz) @
10 kHz
100 kHz
100
–112
–130
–130
–135
2.22
155.52
–120
–128
–139
–142
Virtex-6
GTX
-CXT, HXT,
LXT, SXT
100
–126
–128
–130
7 Series
GTX
Ring Osc
100
–126
–132
7 Series
GTX
LC Osc
100
–126
–130
Spartan-6
GTP
-LXT
Virtex-6
GTH
-HXT
2
0.38
0.23
0.11
0.67
0.38
0.23
0.11
–135
1.92
0.38
0.23
0.11
–136
N/S
0.52
0.38
0.23
0.11
–134
N/S
0.63
0.38
0.23
0.11
Rev. 0.1
1.1
AN699
Table 2. Silicon Labs Phase Jitter Performance vs. Altera Phase Jitter Requirements
Altera Device Jitter Requirements
Silicon Labs Performance
Device
Transmitter
RefClk
Parameter
RefClk
Freq
(MHz)
Offset /
Conditions
Max
(For all
Speed
Grades)
Units
Si51x
Si5338
Si53x
Si57x
Si5326
Si5368
Stratix V
GX & GS
RMS Phase
Jitter
(based on
Altera jitter
mask*)
100
100 Hz–
1 MHz
3.8
ps
RMS
2.1
1.0
0.3
1.1
10 kHz–20
MHz
3.0
ps
1.0
1.0
0.6
0.4
100 Hz–
1 MHz
3.8
ps
RMS
2.1
1.0
0.3
1.1
10 kHz–
20 MHz
3.0
ps
1.0
1.0
0.6
0.4
100 Hz –
1 MHz
3.8
ps
RMS
2.1
1.0
0.3
1.1
10 kHz–
20 MHz
3.0
ps
1.0
1.0
0.6
0.4
1–8 MHz
–123
dBc/
Hz
–138.9
–137.9
–145.6
–147.9
1–8 MHz
42.3
ps
11
36
14
5.4
REFCLK
Phase Jitter
(rms)
Stratix IV
GT & GX
RMS Phase Jitter
(based on
Altera jitter
mask*)
100
REFCLK
Phase Jitter
(rms)
Arria II GX
RMS Phase
Jitter
(based on
Altera jitter
mask*)
100
REFCLK
Phase Jitter
(rms)
Cyclone IV
GX
REFCLK
Phase Noise
REFCLK Total
Jitter (rms)
100
Table 3. Altera Jitter Mask (100 MHz RefClk)
Frequency Offset
Level
Unit
100 kHz
–80
dBc/Hz
1 kHz
–110
dBc/Hz
10 kHz
–120
dBc/Hz
100 kHz
–120
dBc/Hz
> 1 MHz
–130
dBc/Hz
Rev. 0.1
3
AN699
Altera has also recently released a software phase noise calculation tool to assist developers in assessing system
jitter/phase noise when using Stratix IV or Stratix V FPGAs. This tool is called “Altera Transceiver Reference Clock
Phase Noise Jitter Calculator”. Figure 1 and Figure 2 show screen captures of this tool when data for the Si5338
any frequency, any-output clock generator and the Si5326/68 any-frequency jitter attenuating clock are used. Note
the field “Contribution from Ref Clk” is virtually zero.
Figure 1. Si5326 Phase Noise Data in Altera Phase Noise Tool
Figure 2. Si5338 Phase Noise Data in Altera Phase Noise Tool
4
Rev. 0.1
AN699
3. Conclusion
Silicon Labs timing devices are well suited for use as reference clock sources for FPGAs with embedded SerDes in
high-speed serial digital communications applications. With additional built-in features such as any frequency
flexibility with 0 ppm frequency error, superior PSRR, and jitter attenuation with digitally-programmable loop
bandwidth, Silicon Labs timing products provide real system benefits over simple PLL clock solutions.
Rev. 0.1
5
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
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Support and Community
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