Si 5 0 1 0 - EVB EVALUATION BOARD FOR Si5010 OC-12/3, STM-4/1 S O N E T / S D H C L O C K A N D D ATA R E C O V E R Y I C Description Features The Si5010 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5010 multi-rate OC-12/3 and STM-4/1 clock and data recovery (CDR) device. Single 2.5 V power supply Differential I/Os ac coupled Simple jumper configuration All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment Function Block Diagram Jitter Analyzer Pulse G enerator Z C = 50 + REFCLK Z C = 50 – + CLKO UT – Z C = 50 Z C = 50 Si5010 Pattern G enerator Z C = 50 + DATAIN Z C = 50 – Scope + DATAO UT Z C = 50 – Z C = 50 Pattern Analyzer LOL RATESEL PW RDN/CAL REXT 10 k Jum pers Test Point Si5010-EVB Rev C Rev. 1.0 12/02 Copyright © 2016 by Silicon Laboratories Si5010-EVB-10 Si5010-EVB CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 2.5 V relative to chassis GND. Self-Calibration The Si5010 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLLTM. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. On the Si5010-EVB board, a voltage detector IC is utilized to initiate self-calibration. The voltage detector drives the PWRDN/CAL signal low after the supply voltage has reached a specific voltage level. This circuit is described in Silicon Laboratories application note AN42. On the Si5010-EVB, the PWRDN/CAL signal is also accessible via a jumper located in the lower lefthand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. REFCLK REFCLK is used to center the frequency of the DSPLL™ so that the device can lock to the data. Ideally the REFCLK frequency should be 19.44 77.76, or 155.52 MHz, and must have a frequency accuracy of ±100 PPM. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board. RATESEL RATESEL is used to configure the CDR to recover clock and data at different data rates. RATESEL is a binary input that is controlled via a jumper located in the lower left-hand corner of the evaluation board. RATESEL is wired to the center post (signal post) between 2.5 V and GND. For example, the OC-12 data rate is selected by jumping RATESEL to 0.0 V. The table given on the evaluation board lists approximate data rates for the jumper configurations shown in Figure 1. Device Powerdown The CDR can be powered down via the PWRDN/CAL signal. When asserted the evaluation board will draw minimal current. PWRDN/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. CLKOUT, DATAOUT, DATAIN These high-speed I/Os are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the endlaunch SMA jacks as labeled on the PCB. These I/Os are ac coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential both the positive (+) and negative (–) terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 resistors. 2 2.5 V The evaluation board requires one 2.5 V supply. Supply filtering is placed on the board to filter typical system noise components, however, initial performance testing should use a linear supply capable of supplying 2.5 V ±5% dc. GND Power Supply Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 . 2.5 V The evaluation board simplifies characterization of the Si5010 clock and data recovery (CDR) device by providing access to all of the Si5010 I/Os. Device performance can be evaluated by following the Test Configuration section below. Specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. To improve the DATAOUT eye-diagram, short 100 transmission line segments precede the 50 highspeed traces. These segments increase the interface bandwidth from the chip to the 50 traces and reduce data inter-symbol-interference. Please refer to Silicon Laboratories application note AN43 for more details. GND Functional Description RATESEL RATESEL PW RDN/ CAL PW RDN/ CAL 622 M bps 155 M bps Figure 1. RATESEL Jumper Configurations Loss-of-Lock (LOL) LOL is an indicator of the relative frequency between the data and the REFCLK. LOL will assert when the frequency difference is greater than ±600 PPM. In order to prevent LOL from de-asserting prematurely, there is hysterisis in returning from the out-of-lock condition. LOL will be de-asserted when the frequency difference is less than ±300 PPM. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board. Rev. 1.0 Si5010-EVB Test Configuration The three critical tests that are typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5010 Evaluation Board as shown in Figure 2, all three measurements can be easily made. REFCLK should be within ±100 PPM of 19.44, 77.76, or 155.52 MHz. RATESEL must be configured to match the desired data rate, and PWRDN/CAL must be unjumpered. Jitter Tolerance: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer causes a modulation on the data pattern which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. Jitter Generation: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. Jitter Transfer: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. Rev. 1.0 3 Si5010-EVB Pulse Generator DATAOUT– Scope Pattern Analyzer GPIB 2.5 V + – REFCLK+ + REFCLK – DATAOUT + – CLKOUT + – DATAOUT+ REFCLK– DATAIN+ + DATAIN – DATAIN– CLKOUT+ CLKOUT– Si5010-EVB Pattern Generator Jitter Analyzer Data Clock+ GPIB GPIB Clock Synthesizer Signal Source FM Modulation Source GPIB Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 1.0 POS2 POS1 2 1 MKDSN 2,5/3-5,08 J9 1206 BLM31A601S L1 C13 0603 100pF 2 2 2 SIG SIG SIG 1 JC 142-0701-801 BODY J2 1 JC 142-0701-801 BODY J1 JC 142-0701-801 1 JC 142-0701-801 BODY J8 2 SIG 1 C16 0603 100pF BODY J7 C15 0603 100pF VDD 2 C9 VDD VDD REXT REFCLK- REFCLK+ DIN- DIN+ NC RATESEL PWRDN/CAL R1 0603 10k 1 5 4 10 9 20 19 15 Figure 3. Si5010 Schematic 0603 0.1uF C7 0603 0.1uF C8 0603 0.1uF C6 0603 0.1uF C5 0603 2.5k R2 0805 Do Not Install VDD MAX6376XR23-T OUT V? U4 tantalum 10uF C12 1 GND 3 VCC 2.5V JP2 2 7 11 14 DOUT+ DOUT- LOL VDD Si5010 CLKOUT+ CLKOUT- U5 VDDA VDDB VDDC VDDD GNDA GNDB GNDC Rev. 1.0 3 8 18 JP1 17 16 13 12 6 JP4 0603 0.1uF C1 0603 0.1uF C2 0603 0.1uF C3 0603 0.1uF C4 1 1 2 2 JC 142-0701-801 SIG BODY JC 142-0701-801 2 JC 142-0701-801 SIG SIG J6 2 JC 142-0701-801 BODY J4 SIG BODY BODY J5 1 1 J3 Si5010-EVB 5 Si5010-EVB Bill of Materials Si5010EVB Assy Rev B-02 BOM Reference Part Desc C1,C2,C3,C4,C5, C6,C7,C8 CAP, SM, 0.1uF, 0603 CAP, SM, 10 uF, TANTALUM, C12 3216 C13,C15,C16 CAP, SM, 100 pF, 16V, 0603 JP1,JP4 CONNECTOR, HEADER, 2X1 JP2 CONNECTOR, HEADER, 3X1 J1,J2,J3,J4,J5,J6, CONNECTOR, SMA, SIDE J7,J8 MOUNT CONNECTOR, POW ER, 2 J9 POS L1 R2 U4 U5 PCB RESISTOR, SM, 0 OHM, 1206 RESISTOR, SM, 10K, 1%, 0603 RESISTOR, SM, 2.55K, 1%, 0603 MAX6376XR23-T Si5010 PRINTED CIRCUIT BOARD No Load C9 SPARE,0805 R1 6 Part Number Manufacturer C0603X7R160-104KNE Venkel TA010TCM106KAR C0603C0G500101KNE 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN Venkel Venkel 3M 3M 901-10003 Amphenol 1729018 Phoenix Contact CR1206-8W -000T Venkel CR0603-16W -1002FT Venkel CR0603-16W -2551FT MAX6376XR23-T SI5010-BM Si5010-EVB PCB Rev C Venkel Maxim Silicon Laboratories Silicon Laboratories Rev. 1.0 Si5010-EVB Figure 4. Si5010 Silkscreen Rev. 1.0 7 Si5010-EVB Figure 5. Si5010 Component Side 8 Rev. 1.0 Si5010-EVB Figure 6. Si5010 Solder Side Rev. 1.0 9 Si5010-EVB Document Change List Revision 0.41 to Revision 1.0 “Preliminary” language removed. Evaluation Board Assembly Revision History 10 Assembly Level PCB Si5010 Device Assembly Notes B-01 B B Assemble per BOM rev B-01. B-02 C B Assemble per BOM rev B-02. Rev. 1.0 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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