Siliccon Labs & & Xilinx Tiiming Solu utions Gu uide Ideal for Clocking FPGAs Clock Gennerators (Si53335/38, Si5350//51, Si512xx) Any‐rate frrequency synth hesis Generate up to 8 unique, non n‐integer relateed frequencies G Ultra low jitter G Generates any ccombination o of frequencies eexactly Reprogram mmable via I2C/SPI w/out BOM changes W Wide output freequency rangee: 8 kHz to 710 MHz High powe er supply noise rejection miniimizes impact Loow jitter: <1 pss rms phase jittter of board‐le evel noise on cclock jitter F ree‐run and syynchronous op peration View reference designs aat: www.silabs..com/TimingRD D mat translation (LVPECL, LVDSS, CMOS, Inntegrated form H HCSL, SSTL, HSTTL) XO/V VCXO (Si53x, Sii55x, Si57x, Si5 51x, Si500) Inndependent VD DDO per outpu ut clock (1.8, 2.5, 3.3 V) Single, duaal, quad, and any‐rate freque ency XO/VCXOss PPCI Express Gen n 1/2/3 and Gb bE jitter compliant Any‐freque ency programm mable: 100 kHz to 1.4 GHz Request a custo om clock: www w.silabs.com/ccustom‐timing R Low jitter o 0..3 ps rms (Si53x/7x XOs) 32x, Si536x, Si5 537x) Jitter Atteenuating Clockks (Si531x, Si53 o 0..5 ps rms (Si55x VCXOs) G Generate any frrequency from m 2 kHz to 1.4 G GHz from 2 kHzz o 0..8 ps rms (Si51x XO/VCXOs) too 710 MHz inpput 2 week leaad time for anyy device U Ultra low jitter: 0.3 ps rms phase jitter +/‐20, 50, 100 ppm stability with guaranteed aging Jiitter cleaning w w/integrated aadjustable loop p filter (>4 Hz) Industry‐sttandard 3.2x5m mm and 5x7mm m packaging Iddeal for OTN, 110G/100G and broadcast videeo applications LVPECL, LV VDS, CMOS, CM ML, HCSL F ree‐run, synch hronous, holdo over modes of o operation 1.8, 2.5, 3.3 V Ask your distrib butor about thee FREE Clock TTree service A Request a custom XO/VC CXO: a vailable now! www.silabs.com/custom‐timing Protocol 3G‐SDI SDI SD/HD D ASI CEI‐6G/SR R/LR Data Rate D (Gbp ps per Lane) 2.97 0.27/1.485 0.27 4.976‐6.375 CEI‐11G/SSR 9.95‐11.1 9 CEI‐28GG/VSR 19.9‐28.05 CPRI 0.61 144, 1.2288, 2.4576, 3.072, 4.9152, 6.144, 9.8304 Xilinx FPGA Silico n Labs X XO Silicon Labs VCXO Silicon Laabs Clock Virtex‐7 GTX/GTH Kintex‐7 GTTX Artix‐7 GTP P Virtex‐6 Virtex‐5 Spartan‐6 Virtex‐7 GTX/GTH Kintex‐7 GTTX Artix‐7 GTP P Virtex‐5 Spartan‐3 Artix‐7 Zynq‐7000 0 Kintex‐7 Virtex‐7 Virtex‐7 GTX/GTH Kintex‐7 GTTX Artix‐7 GTP P Virtex‐7 GTX/GTH Virtex‐7 GTX/GTH Virtex‐7 GTX/GTH Kintex‐7 GTTX Artix‐7 GTP P Virtex‐6 Si553x Si551x Si55x Si51x Si5324/6 69 (Genlocck) Si5335/3 38 (clk gen n) Si551x Si51x Si5324/6 69 (Genlocck) Si5335/3 38 (Clk gen n.) Si551x Si51x Si5335/3 38 Si551x Si51x Si5335/3 38 Si553x Si55x Si5319 9 Si553x Si55x Si5319 9 Si553x Si55x Si5380 0 Protocol Data Rate (Gbps per Lane) Display Port 1.62, 2.7 10GbE XAUI 3.125 40G/100G Ethernet Gigabit Ethernet Fibre Channel GPON JESD204B 10.3125 1.25 1.0625, 2.125, 4.25, 8.5, 10.52, 14.025 1.244 (up), 2.488 (down) 12.5, 6.375 OTN OTU‐2 10.709 OTN 10GbE w/FEC 11.1, 11.3 IEEE 802.3ba 10GBASE‐KR 10.3125 Xilinx FPGA Virtex‐5 Spartan‐6 Virtex‐5 Spartan‐6 Artix‐7 GTP Virtex‐6 Virtex‐5 Spartan‐6 Virtex‐7 GTX/GTH/GTZ Kintex‐7 GTX Virtex‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Virtex‐4 Spartan‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Virtex‐7 GTX/GTH Artix‐7 GTP Virtex‐6 Kintex‐7 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Silicon Labs XO Silicon Labs VCXO Silicon Labs Clock Si500 Si500 Si5350/51 Si51x Si51x Si5335/38 Si53x Si55x Si5326/75 Si51x Si51x Si5326/27 Si5335/38 Si51x Si53x Si51x Si55x Si5326/27 Si5326/27 Si5335/38 Si51x Si51x Si5326/27 Si5335/38 Si5380 Si53x Si55x Si5326/75 Si53x Si55x Si5326/75 Si53x Si55x Si5326/75 © 2013 Silicon Laboratories Inc. All rights reserved. Specifications subject to change. Please contact your Silicon Labs representative or distributor and visit our website at www.silabs.com. March 2013. (v4) Protocol Interlaken OBSAI Data Rate (Gbps per Lane) Xilinx FPGA Silicon Labs XO Silicon Labs VCXO Silicon Labs Clock 3.125‐12.5 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Si53x Si51x Si55x Si51x Si5326 Si5335/38 0.768, 1.536, 3.072, 6.144 Kintex‐7 Virtex‐7 GTX/GTH Virtex‐6 Artix‐7 GTP Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Spartan‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Kintex‐7 Virtex‐7 GTX/GTH Artix‐7 GTP Si53x Si55x Si5380 Si51x Si51x Si5335/38 Si5121x Si51x Si51x Si51x Si59x Si51x Si59x Si5335/38 Si5121x Si5335/38 Si51x Si59x Si51x Si59x Si51x Si59x Si51x Si59x Si500 Si51x Si500 Si51x Si51x Si51x Si500 Si51x Si500 Si51x Si51x Si51x PCIe Gen1, Gen2 2.5, 5 PCIe Gen3 8 SGMII/ QSGMII 1.25/4x1.25 RXAUI 6.25 QPI 6.4 SAS 1.5, 3, 6 SAS12G SATA Serial RapidIO 1.5, 3, 6, 12 1.5, 3, 6 1.25, 2.5, 3.125, 5, 6.25 Virtex‐7 GTX/GTH Kintex‐7 GTX Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Virtex‐7 GTX/GTH Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐5 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Spartan‐6 Si5335/38 Si5319 Si5335/38 Si5335/38 Si5350/51 Si5335/38 Si5355/56 Si5335/38 Si5350/51 Si5338/35 Si5350/51 © 2013 Silicon Laboratories Inc. All rights reserved. Specifications subject to change. Please contact your Silicon Labs representative or distributor and visit our website at www.silabs.com. March 2013. (v4) Protocol Data Rate (Gbps per Lane) SFI‐5.1 2.488‐3.125 SFI‐5.2 9.9‐11.3 SONET OC‐ 3/12/48/ 192 0.155, 0.622, 2.488, 9.953 V‐by‐One 3, 3.75 10GbE XFI 10.3125 Xilinx FPGA Silicon Labs XO Silicon Labs VCXO Silicon Labs Clock Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐7 GTX/GTH Kintex‐7 GTX Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐6 Virtex‐7 GTX/GTH Kintex‐7 GTX Artix‐7 GTP Virtex‐7 GTX/GTH Kintex‐7 GTX Virtex‐6 Si51x Si51x Si5335/38 Si53x Si55x Si5319 Si51x Si53x Si51x Si55x Si5326/75 Si5335/38 Si51x Si51x Si5335/38 Si53x Si55x Si5326/75 © 2013 Silicon Laboratories Inc. All rights reserved. Specifications subject to change. Please contact your Silicon Labs representative or distributor and visit our website at www.silabs.com. March 2013. (v4)