Any-Rate Precision Clock ICs

Any-Rate Precision Clocks
Wireline Market Overview
♦ Analog Modems
¾ Large installed base and growth in
embedded applications
Emerging
Player
♦ Voice
¾ Transition to VoIP to reduce service
provider cost-of-ownership
♦ Timing
¾ Large, established, diversified
market
♦ Power
¾ Increasing electronics content
driving higher power density in
power supplies, motor control and
lighting
2
3,000
Power
2,500
2,000
1,500
MarketShare
Leader
Timing
1,000
500
Modem Voice
0
Potential Market Size (in millions)
Wireline End Markets
♦ Common customer base
¾ Telecom customers:
voice, timing and power
¾ Consumer customers:
modem, voice and timing
¾ PC customers:
modem, voice and power
♦ Common technology
¾ SLIC and isolation technologies:
modem and voice
¾ High-voltage technologies:
power and voice
♦ Common market opportunities
¾ Motor control:
power and high-voltage
¾ VoIP and telecom:
high-voltage, voice and timing
¾ Communications: modem, voice,
timing and power
3
Common Technology and
Customer Needs
Core Competency
♦ Mixed-signal innovation in CMOS
♦ Unique phase-locked loop (PLL)
technology
♦ Functional and system integration that
enables first of a kind high-voltage
architectures
4
Wireline Portfolio
♦ Modem
¾ ISOmodem®
¾ Silicon DAA
♦ Voice
¾ ProSLIC®
¾ Voice DAA
♦ Power
¾ Digital Isolators
¾ Power-over-Ethernet (PoE)
♦ Timing
¾ Frequency Control Solutions
¾ Precision Clock ICs
¾ SiPHY® Physical Layer ICs
5
Applications:
Satellite Set-Top Boxes
Voice-over-Broadband DSL Modems
Fax Machines
SONET/SDH Optical Port Cards
Communications Equipment
Enterprise Computing
Test & Measurement
Timing Market Challenges
Traditional Multi-Frequency Design
♦ Timing system complexity increasing in next-generation networking,
wireless infrastructure and broadcast video equipment
♦ Traditional solutions require
¾ Many discrete high-performance components
¾ Complex board layout and noise isolation
¾ Extensive PLL expertise
♦ Clock IC designers must provide high performance, high integration and
simplified design to help OEMs
6
¾ Reduce total design costs
¾ Speed time-to-market
¾ Improve performance in the end product
Introducing Si53xx Any-Rate Precision Clock
♦ Family of nine highly-integrated, ultra-low jitter clock multiplier ICs
♦ DSPLL-based architecture enables any-rate frequency synthesis
♦ Improves performance and simplifies design
7
Si53xx—High-Performance Applications
Next-Generation Networking
Wireless Base Stations
HDTV Video
Test and Measurement
8
High-Speed Data Acquisition
The DSPLL Advantage
Optional Crystal/Reference Clock
(required for jitter attenuation)
DSPLL
Clock
Input
Freq.
N3
D
.
Phase
Detector
A/D
Digital
Signal
Processing
N
DCO
Freq.
N1
D
.
Clock
Output
Freq.
N2
D
.
♦ Patented DSPLL architecture provides frequency agility
¾ Eliminates need for discrete VCXO/VCSOs
♦ Ultra-low jitter generation
¾ 0.3 ps rms: 12 kHz to 20 MHz
♦ User-selectable loop bandwidth allows jitter performance optimization
♦ Integrated loop filter minimizes PLL sensitivity to noise
♦ Simplifies PLL design and layout
9
Si53xx—Any-Rate Frequency Synthesis
♦ DSPLL enables any-rate operation over a wide range of frequencies
¾ Input: 2 kHz to 710 MHz
¾ Output: 2 kHz to 945 MHz; select frequencies to 1.4 GHz
♦ No external component changes required
♦ Frequency flexibility allows design reuse and reduces BOM
10
Si53xx—Ultra Low Jitter/Phase Noise
♦ Jitter and phase noise comparable to best-in-class VCXO/VCSO PLLs
Configuration: CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, 800 Hz Loop Bandwidth
11
Si53xx—Feature Rich and Easy to Use
♦ Selectable loop bandwidths from
60 Hz to 8.4 kHz
¾ Adjustable jitter attenuation
without changing components
¾ Optimizes jitter performance at
the application level
♦ Fault detection for clock inputs
¾ Alarm generation for loss-ofsignal (LOS) and frequency
offset (FOS)
♦ Hitless switching
¾ Enables input clock switching
without causing disturbance on
output
♦ Selectable output formats:
LVPECL, LVDS, CML or CMOS
¾ Eliminates discrete voltage level
translators
12
Si53xx vs. Competition
13
Si53xx Any-Rate Precision Clock Family
14
Part #
Jitter
Attenuation
Clock
µP
Multiplication Control
Si5316
9
Si5323
9
9
Si5326
9
9
Si5366
9
9
Si5368
9
9
Si5322
9
Si5325
9
Si5365
9
Si5367
9
Pin
Control
Clock
Inputs
Clock
Outputs
9
2
1
9
2
2
2
2
4
5
4
5
2
2
2
2
4
5
4
5
9
9
9
9
9
9
9
Si53xx—Summary
♦ Industry’s first low jitter, any-rate clock multiplier/jitter attenuator family
♦ Industry-leading jitter performance
♦ Highly integrated and easy to use
15
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