si530

S i 5 3 0 / 5 31
REVISION D
C R YS TA L O SCILLATOR (XO) (10 M H Z T O 1 . 4 GH Z )
Features

Si5602
Available with any-rate output

frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
 3rd generation DSPLL® with superior 
jitter performance

 3x better frequency stability than

SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
 Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 7.




SONET/SDH
Networking
 SD/HD video
Test and measurement
Clock and data recovery
 FPGA/ASIC clock generation
Pin Assignments:
See page 6.
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
V DD
CLK– CLK+
(Top View)
NC
1
6
VDD
OE
2
5
CLK–
GND
3
4
CLK+
Si530 (LVDS/LVPECL/CML)
OE
1
6
VDD
NC
2
5
NC
GND
3
4
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
OE
1
6
VDD
NC
2
5
CLK–
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
Rev. 1.4 5/13
GND
Copyright © 2013 by Silicon Laboratories
Si530/531
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage1
Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
V
1.8 V option
1.71
1.8
1.89
V
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
111
99
90
81
121
108
98
88
Tristate mode
—
60
75
mA
VIH
0.75 x VDD
—
—
V
VIL
—
—
0.5
V
–40
—
85
ºC
IDD
Output Enable (OE)2
Operating Temperature Range
TA
mA
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE pin includes a 17 k pullup resistor to VDD.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency1,2
Initial Accuracy
Symbol
Test Condition
Min
Typ
Max
Unit
fO
LVPECL/LVDS/CML
10
—
945
MHz
CMOS
10
—
160
MHz
Measured at +25 °C at time of
shipping
—
±1.5
—
ppm
–7
–20
–50
—
—
—
+7
+20
+50
ppm
Frequency drift over first year
—
—
±3
ppm
Frequency drift over 20 year
life
—
—
±10
ppm
fi
Temperature Stability1,3
Aging
fa
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
2
Rev. 1.4
Si530/531
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Total Stability
Powerup Time4
Test Condition
Min
Typ
Max
Unit
Temp stability = ±7 ppm
—
—
±20
ppm
Temp stability = ±20 ppm
—
—
±31.5
ppm
Temp stability = ±50 ppm
—
—
±61.5
ppm
—
—
10
ms
tOSC
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output
Symbol
Test Condition
Min
Typ
Max
Unit
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
2.5/3.3 V option mid-level
—
VDD – 1.30
—
V
1.8 V option mid-level
—
VDD – 0.36
—
V
2.5/3.3 V option swing (diff)
1.10
1.50
1.90
VPP
1.8 V option swing (diff)
0.35
0.425
0.50
VPP
VOH
IOH = 32 mA
0.8 x VDD
—
VDD
V
VOL
IOL = 32 mA
—
—
0.4
V
tR, tF
LVPECL/LVDS/CML
—
—
350
ps
CMOS with CL = 15 pF
—
1
—
ns
45
—
55
%
Option1
LVDS Output Option2
CML Output Option2
VO
VOD
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
SYM
LVPECL:
(diff)
LVDS:
CMOS:
VDD – 1.3 V
1.25 V (diff)
VDD/2
Notes:
1. 50  to VDD – 2.0 V.
2. Rterm = 100  (differential).
3. CL = 15 pF
Rev. 1.4
3
Si530/531
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Phase Jitter (RMS)1
for FOUT > 500 MHz
J
12 kHz to 20 MHz (OC-48)
—
0.25
0.40
ps
50 kHz to 80 MHz (OC-192)
—
0.26
0.37
ps
Phase Jitter (RMS)1
for FOUT of 125 to 500 MHz
J
12 kHz to 20 MHz (OC-48)
—
0.36
0.50
ps
—
0.34
0.42
ps
Phase Jitter (RMS)
for FOUT of 10 to 160 MHz
CMOS Output Only
J
12 kHz to 20 MHz (OC-48)2
—
0.62
—
ps
50 kHz to 20 MHz2
—
0.61
—
ps
50 kHz to 80 MHz (OC-192)
2
Notes:
1. Refer to AN256 for further information.
2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
Min
Typ
Max
Unit
JPER
RMS
—
2
—
ps
Peak-to-Peak
—
14
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
4
120.00 MHz
156.25 MHz
622.08 MHz
LVDS
LVPECL
LVPECL
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
Rev. 1.4
Unit
dBc/Hz
Si530/531
Table 7. Environmental Compliance
The Si530/531 meets the following qualification test requirements.
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross & Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Moisture Sensitivity Level
J-STD-020, MSL1
Gold over Nickel
Contact Pads
Table 8. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance Junction to Ambient
JA
Still Air
—
84.6
—
°C/W
Thermal Resistance Junction to Case
JC
Still Air
—
38.8
—
°C/W
Ambient Temperature
TA
–40
—
85
°C
Junction Temperature
TJ
—
—
125
°C
Table 9. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Unit
TAMAX
85
ºC
Supply Voltage, 1.8 V Option
VDD
–0.5 to +1.9
V
Supply Voltage, 2.5/3.3 V Option
VDD
–0.5 to +3.8
V
Input Voltage (any input pin)
VI
–0.5 to VDD + 0.3
V
Storage Temperature
TS
–55 to +125
ºC
ESD
2500
V
TPEAK
260
ºC
tP
20–40
seconds
Maximum Operating Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)2
Soldering Temperature Time @ TPEAK (Pb-free profile)2
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Rev. 1.4
5
Si530/531
2. Pin Descriptions
(Top View)
NC
1
6
VDD
OE
1
6
VDD
OE
1
6
VDD
OE
2
5
CLK–
NC
2
5
NC
NC
2
5
CLK–
GND
3
4
CLK+
GND
3
4
CLK
GND
3
4
CLK+
Si530
Si530
Si531
LVDS/LVPECL/CML
CMOS
LVDS/LVPECL/CML
Table 10. Pinout for Si530 Series
Pin
Symbol
LVDS/LVPECL/CML Function
CMOS Function
1
OE (CMOS only)*
No connection
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2
OE
(LVPECL,LVDS,
CML)*
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
No connection
3
GND
Electrical and Case Ground
Electrical and Case Ground
4
CLK+
Oscillator Output
Oscillator Output
5
CLK–
Complementary Output
No connection
6
VDD
Power Supply Voltage
Power Supply Voltage
*Note: OE includes a 17 k pullup resistor to VDD.
Table 11. Pinout for Si531 Series
Pin
Symbol
LVDS/LVPECL/CML Function
1
OE (LVPECL, LVDS, CML)*
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2
No connection
No connection
3
GND
Electrical and Case Ground
4
CLK+
Oscillator Output
5
CLK–
Complementary output
6
VDD
Power Supply Voltage
*Note: OE includes a 17 k pullup resistor to VDD.
6
Rev. 1.4
Si530/531
3. Ordering Information
The Si530/531 XO supports a variety of options including frequency, temperature stability, output format, and VDD.
Specific device configurations are programmed into the Si530/531 at time of shipment. Configurations can be
specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based
part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this
tool and for further ordering instructions. The Si530 and Si531 XO series are supplied in an industry-standard,
RoHS compliant, 6-pad, 5 x 7 mm package. The Si531 Series supports an alternate OE pinout (pin #1) for the
LVPECL, LVDS, and CML output formats. See Tables 10 and 11 for the pinout differences between the Si530 and
Si531 series.
53x
X
X
XXXMXXX
D
G
R
Tape & Reel Packaging
Blank = Trays
530 or 531 XO
Product Family
Operating Temp Range (°C)
G
-40 to +85°C
Part Revision Letter
1st Option Code
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
U
V
W
VDD
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
Output Format Output Enable Polarity
LVPECL
High
LVDS
High
CMOS
High
CML
High
LVPECL
High
LVDS
High
CMOS
High
CML
High
CMOS
High
CML
High
LVPECL
Low
LVDS
Low
CMOS
Low
CML
Low
LVPECL
Low
LVDS
Low
CMOS
Low
CML
Low
CMOS
Low
CML
Low
Frequency (e.g., 622M080 is 622.080 MHz)
Available frequency range is 10 to 945 MHz, 970 to 1134 MHz, and
1213 to 1417 MHz. The position of “M” shifts to denote higher or lower
frequencies. If the frequency of interest requires greater than 6 digit
resolution, a six digit code will be assigned for the specific frequency.
2nd Option Code
Code Temperature Stability (ppm, max, ±)
A
50
B
20
C
7
Total Stablility (ppm, max, ±)
61.5
31.5
20
Note:
CMOS available to 160 MHz.
Example P/N: 530AB622M080DGR is a 5 x 7 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply, LVPECL output,
and Output Enable active high polarity. Temperature stability is specifed as ±20 ppm. The part is specified for –40 to +85 °C ambient
temperature range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
Rev. 1.4
7
Si530/531
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si530/531. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si530/531 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension
A
b
c
D
D1
e
E
E1
H
L
L1
p
R
aaa
bbb
ccc
ddd
eee
Min
1.50
1.30
0.50
4.30
6.10
0.55
1.17
0.05
1.80
Nom
1.65
1.40
0.60
5.00 BSC
4.40
2.54 BSC
7.00 BSC
6.20
0.65
1.27
0.10
—
0.70 REF
0.15
0.15
0.10
0.10
0.05
Max
1.80
1.50
0.70
4.50
6.30
0.75
1.37
0.15
2.60
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
8
Rev. 1.4
Si530/531
5. Si530/Si531 Mark Specification
Figure 3 illustrates the mark specification for the Si530/Si531. Table 13 lists the line information.
Figure 3. Mark Specification
Table 13. Si53x Top Mark Description
Line
Position
Description
1
1–10
“SiLabs"+ Part Family Number, 53x (First 3 characters in part number where x = 0
indicates a 530 device and x = 1 indicates a 531 device).
2
1–10
Si530, Si531: Option1 + Option2 + Freq(7) + Temp
Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution:
Option1 + Option2 + ConfigNum(6) + Temp
3
Trace Code
Position 1
Pin 1 orientation mark (dot)
Position 2
Product Revision (D)
Position 3–6
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7
Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)
Position 8–9
Calendar Work Week number (1–53), to be assigned by assembly site
Position 10
“+” to indicate Pb-Free and RoHS-compliant
Rev. 1.4
9
Si530/531
6. 6-Pin PCB Land Pattern
Figure 4 illustrates the 6-pin PCB land pattern for the Si530/531. Table 14 lists the values for the dimensions shown
in the illustration.
Figure 4. Si530/531 PCB Land Pattern
Table 14. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
2.54
X1
1.55
Y1
1.95
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
10
Rev. 1.4
Si530/531
DOCUMENT CHANGE LIST
Revision 1.1 to Revision 1.2

Revision 0.4 to Revision 0.5

Updated Table 1, “Recommended Operating
Conditions,” on page 2.

Added

maximum supply current specifications.
relationship between temperature at startup
and operation temperature.
Specified

Updated Table 4, “CLK± Output Phase Jitter,” on
page 4 to include maximum rms jitter generation
specifications and updated typical rms jitter
specifications.
 Added Table 6, “CLK± Output Phase Noise
(Typical),” on page 4.
 Added Output Enable active polarity as an option in
Figure 1, “Part Number Convention,” on page 7.




Revision 0.5 to Revision 1.0

Updated Note 3 in Table 1, “Recommended
Operating Conditions,” on page 2.
 Updated Figure 1, “Part Number Convention,” on
page 7.
Revision 1.2 to Revision 1.3

Revision 1.0 to Revision 1.1

Updated Table 1, “Recommended Operating
Conditions,” on page 2.

maintains stable operation over –40 to +85 ºC
operating temperature range.
Supply current specifications updated for revision D.
Revised Figure 2 and Table 12 on page 8 to reflect
current package outline diagram.
 Revised Figure 4 and Table 14 on page 10 to reflect
the recommended PCB land pattern.
Updated Table 2, “CLK± Output Frequency
Characteristics,” on page 2.
Added
specification for ±20 ppm lifetime stability
(±7 ppm temperature stability) XO.

Updated Table 3, “CLK± Output Levels and
Symmetry,” on page 3.
Updated
LVDS differential peak-peak swing
specifications.

Updated Table 4, “CLK± Output Phase Jitter,” on
page 4.
 Updated Table 5, “CLK± Output Period Jitter,” on
page 4.
Revised
period jitter specifications.
Updated Table 9, “Absolute Maximum Ratings1,” on
page 5 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
 Updated 3. "Ordering Information" on page 7.

Changed

11
Added Table 8, “Thermal Characteristics,” on
page 5.
Revision 1.3 to Revision 1.4
Device

Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications for Table 3 on page 3.
Added footnotes clarifying max offset frequency test
conditions for Table 4 on page 4.
Added CMOS phase jitter specs to Table 4 on
page 4.
Removed the words "Differential Modes:
LVPECL/LVDS/CML" in the footnote referring to
AN256 in Table 4 on page 4.
Separated 1.8 V, 2.5 V/3.3 V supply voltage
specifications in Table 9 on page 5.
Updated and clarified Table 9 on page 5 to include
the "Moisture Sensitivity Level" and "Contact Pads"
rows.
Updated Figure 3 on page 9 and Table 13 on page 9
to reflect specific marking information. Previously,
Figure 3 was generic.
ordering instructions to revision D.
Added 5. "Si530/Si531 Mark Specification" on page
9.
Rev. 1.4
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