Si516

Si 5 16
D U A L F REQUENCY VOLTAGE - C ON TROLLED
C R YS TA L O SCILLATOR ( V C X O ) 1 0 0 k H Z T O 250 M H Z
Features







Supports any frequency from
100 kHz to 250 MHz
Two selectable output frequencies
Low-jitter operation
Short lead times: <2 weeks
AT-cut fundamental mode crystal
ensures high reliability/low aging
High power supply noise rejection
1% control voltage linearity






Available CMOS, LVPECL,
LVDS, and HCSL outputs
Optional 1:2 CMOS fanout buffer
3.3 and 2.5 V supply options
Industry-standard 3.2 x 5.0 mm
and 5 x 7 mm package/pinouts
Pb-free/RoHS-compliant
Selectable Kv (60, 90, 120,
150 ppm/V)
Si5602
Ordering Information:
See page 14.
Applications
SONET/SDH/OTN
 PON
 Low Jitter PLLs
 xDSL

Broadcast video
 Telecom
 Switches/routers
 FPGA/ASIC clock generation

Description
The Si516 dual frequency VCXO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional VCXO where a different crystal is required for each output
frequency, the Si516 uses one fixed crystal and Silicon Labs’ proprietary
synthesizer to generate any frequency across this range. This IC-based
approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior control voltage linearity and supply noise
rejection, improving PLL stability and simplifying low jitter PLL design in
noisy environments. The Si516 is factory-configurable for a wide variety of
user specifications, including frequency, supply voltage, output format,
tuning slope and stability. Specific configurations are factory-programmed at
time of shipment, eliminating long lead times and non-recurring engineering
charges associated with custom frequency oscillators.
Pin Assignments:
See page 12.
Vc 1
6 V DD
FS
2
5 NC
GND
3
4 CLK
CMOS Dual VCXO
Vc
1
6 V DD
FS
2
5 CLK–
G ND
3
4 CLK+
LVPECL/LVDS/HCSL/Dual CM OS
Dual VCXO
Functional Block Diagram
Rev. 1.0 6/12
Copyright © 2012 by Silicon Laboratories
Si516
Si5 16
2
Rev. 1.0
Si516
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1. Si516 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.0
3
Si5 16
1. Electrical Specifications
Table 1. Recommended Operating Conditions
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Supply Voltage
Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
V
CMOS, 100 kHz,
single-ended
—
24
29
mA
LVDS
(output enabled)
—
22
26
mA
LVPECL
(output enabled)
—
42
46
mA
HCSL
(output enabled)
—
44
47
mA
Tristate
(output disabled)
—
—
22
mA
IDD
FS "1" Setting
VIH
0.80 x VDD
—
—
V
FS "0" Setting
VIL
—
—
0.20 x VDD
V
FS Internal Pull-Up Resistor
RI
—
45
—
k
Operating Temperature
TA
–40
—
85
oC
4
Rev. 1.0
Si516
Table 2. Vc Control Voltage Input
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Control Voltage Range
VC
Control Voltage Tuning Slope
(10 to 90% VDD)
Kv
Kv Variation
Test Condition
Min
Typ
Max
Unit
0.1 x VDD
VDD/2
0.9 x VDD
V
Ordering option
Kv_var
BSL
60, 90, 120, 150
ppm/V
—
—
±10
%
–5
±1
+5
%
Control Voltage Linearity
LVC
Modulation Bandwidth
BW
—
10
—
kHz
Vc Input Impedance
ZVC
—
100
—
k
Table 3. Output Clock Frequency Characteristics
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FO
CMOS, Dual CMOS
0.1
—
212.5
MHz
FO
LVDS/LVPECL/HCSL
0.1
—
250
MHz
Temperature Stability
ST
TA = –40 to +85 oC
–20
—
+20
ppm
Aging
A
Frequency drift over 10-year life
—
—
±8.5
ppm
Minimum Absolute Pull Range
APR
Ordering option
Startup Time
TSU
Minimum VDD until output frequency (FO) within specification
—
—
10
ms
Disable Time
TD
FO > 10 MHz
—
—
5
µs
FO < 10 MHz
—
—
40
µs
FO > 10 MHz
—
—
20
µs
FO < 10 MHz
—
—
60
µs
—
—
10
ms
Nominal Frequency
Enable Time
Settling Time after FS Change
TD
tFRQ
Rev. 1.0
±30, ±50,±80, ±100
ppm
5
Si5 16
Table 4. Output Clock Levels and Symmetry
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CMOS Output Logic High
VOH
0.85 x VDD
—
—
V
CMOS Output Logic Low
VOL
—
—
0.15 x VDD
V
CMOS Output Logic High
Drive
IOH
3.3 V
–8
—
—
mA
2.5 V
–6
—
—
mA
CMOS Output Logic Low
Drive
IOL
3.3 V
8
—
—
mA
2.5 V
6
—
—
mA
0.1 to 125 MHz,
CL = 15 pF
—
0.8
1.2
ns
0.1 to 212.5 MHz,
CL = no load
—
0.6
0.9
ns
CMOS Output Rise/Fall Time
(20 to 80% VDD)
TR/TF
LVPECL/HCSL Output
Rise/Fall Time
(20 to 80% VDD)
TR/TF
—
—
565
ps
LVDS Output Rise/Fall Time
(20 to 80% VDD)
TR/TF
—
—
800
ps
LVPECL Output Common
Mode
VOC
50  to VDD – 2 V,
single-ended
—
VDD –
1.4 V
—
V
LVPECL Output Swing
VO
50  to VDD – 2 V,
single-ended
0.55
0.8
0.90
VPPSE
LVDS Output Common Mode
VOC
100  line-line,
VDD = 3.3/2.5 V
1.13
1.23
1.33
V
LVDS Output Swing
VO
Single-ended 100 
differential termination
0.25
0.38
0.42
VPPSE
HCSL Output Common Mode
VOC
50 to ground
0.35
0.38
0.42
V
HCSL Output Swing
VO
Single-ended
0.58
0.73
0.85
VPPSE
Duty Cycle
DC
48
50
52
%
6
Rev. 1.0
Si516
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter (RMS)
JPRMS
10 k samples1
—
—
1.3
ps
Period Jitter (PK-PK)
JPPKPK
10 k samples1(brickwall)
—
—
11
ps
12 kHz to 20 MHz (brickwall)
—
0.9
1.3
ps
1.875 MHz to 20 MHz2 (brickwall)
—
0.25
0.5
ps
100 Hz offset
—
–71
—
dBc/Hz
1 kHz offset
—
–94
—
dBc/Hz
10 kHz offset
—
–113
—
dBc/Hz
100 kHz offset
—
–124
—
dBc/Hz
1 MHz offset
—
–136
—
dBc/Hz
100 kHz sinusoidal noise
—
4.0
—
ps
200 kHz sinusoidal noise
—
3.5
—
ps
500 kHz sinusoidal noise
—
3.5
—
ps
1 MHz sinusoidal noise
—
3.5
—
ps
FO = 156.25 MHz,
Offset > 10 kHz
—
–75
—
dBc
Phase Jitter (RMS)
Phase Noise, 155.52 MHz
Additive RMS Jitter Due to
External Power Supply
Noise3
Spurious Performance
φJ
φN
JPSRR
SPR
2
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mVPP).
Rev. 1.0
7
Si5 16
Table 6. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples1
—
—
2.1
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples1
—
—
18
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.25
0.55
ps
12 kHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.8
1.1
ps
100 Hz
—
–72
—
dBc/Hz
1 kHz
—
–93
—
dBc/Hz
10 kHz
—
–114
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
Phase Noise,
156.25 MHz
Spurious
φN
SPR
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
8
Rev. 1.0
Si516
Table 7. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples*
—
—
1.2
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples*
—
—
11
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth*(brickwall)
—
0.25
0.30
ps
12 kHz to 20 MHz integration bandwidth* (brickwall)
—
0.8
1.0
ps
100 Hz
—
–75
—
dBc/Hz
1 kHz
—
–98
—
dBc/Hz
10 kHz
—
–117
—
dBc/Hz
100 kHz
—
–127
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
Phase Noise,
156.25 MHz
Spurious
φN
SPR
*Note: Applies to an output frequency of 100 MHz.
Rev. 1.0
9
Si5 16
Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.25
0.35
ps
12 kHz to 20 MHz integration bandwidth2 (brickwall)
—
0.8
1.1
ps
100 Hz
—
–71
—
dBc/Hz
1 kHz
—
–93
—
dBc/Hz
10 kHz
—
–113
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset > 10 kHz
—
–75
—
dBc
Phase Noise,
156.25 MHz
Spurious
φN
SPR
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 9. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Moisture Sensitivity Level
MSL 1
Contact Pads
10
Gold over Nickel
Rev. 1.0
Si516
Table 10. Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
Test Condition
Value
Unit
JA
Still air
110
°C/W
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Rating
TAMAX
85
°
TS
–55 to +125
°
VDD
–0.5 to +3.8
V
VI
–0.5 to VDD + 0.3
V
ESD Sensitivity (HBM, per JESD22-A114)
HBM
2
kV
Soldering Temperature (Pb-free profile)2
TPEAK
260
TP
20–40
Maximum Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage (any input pin)
Soldering Temperature Time at TPEAK (Pb-free profile)2
Unit
C
C
°
C
sec
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Rev. 1.0
11
Si5 16
2. Pin Descriptions
Vc 1
6 V DD
Vc 1
6 VDD
FS
2
5 NC
FS 2
5 CLK–
GND
3
4 CLK
GND 3
4 CLK+
CMOS Dual VCXO
LVPECL/LVDS/HCSL/Dual CMOS
Dual VCXO
Table 12. Si516 Pin Descriptions (CMOS)
Pin
Name
CMOS Function
1
VC
Control Voltage Input.
2
FS
Frequency Select.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4
CLK
Clock Output.
5
NC
No connect. Make no external connection to this pin.
6
VDD
Power Supply Voltage.
Table 13. Si516 Pin Descriptions (LVPECL/LVDS/HCSL/Dual CMOS)
12
Pin
Name
LVPECL/LVDS/HCSL/Dual CMOS Function
1
VC
Control Voltage Input.
2
FS
Frequency Select.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
VDD
Power Supply Voltage.
Rev. 1.0
Si516
2.1. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple VCXOs with a single Si516 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Output
Rev. 1.0
13
Si5 16
3. Ordering Information
The Si516 supports a variety of options including frequency, minimum absolute pull range (APR), tuning slope,
output format, and VDD. Specific device configurations are programmed into the Si516 at time of shipment.
Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web
browser-based
part
number
configuration
utility
to
simplify
this
process.
Refer
to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si516 VCXO
series is supplied in industry-standard, RoHS compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm packages. Tape
and reel packaging is an ordering option.
6-digit Frequency Designator Code
Series
Output Format
Package
516
Dual Frequency VCXO
LVPECL, LVDS, HCSL,
CMOS, Dual CMOS
6-pin
Code
Description
xxxxxx
This 6-digit
g code represents
p
a unique
q
combination of two frequencies. Frequencies
from 100 kHz to 250 MHz (differential) or 212.5
MHz (CMOS) are supported. For more info:
www.silabs.com/VCXOPartNumber.
A = Revision: A
G = Temp Range: -40°C to 85°C
R = Tape & Reel; Blank = Trays
1st Option Code: Output Format
VDD
Output Format
A
3.3V
LVPECL
B
3.3V
LVDS
C
3.3V
CMOS
D
3.3V
HCSL
E
2.5V
LVPECL
F
2.5V
LVDS
G
2.5V
CMOS
H
2.5V
HCSL
M
3.3V
Dual CMOS (In-phase)
N
3.3V
Dual CMOS (Complementary)
P
2.5V
Dual CMOS (In-phase)
Q
2.5V
Dual CMOS (Complementary)
* 3rd Option Code:
Frequency Select Functionality
FS Functionality
516 X X X XXXXXX X AGR
Package
Dimensions
3rd Option Code*
2nd Option Code: Absolute Pull Range (all ± ppm values)
Minimum APR
A
5 x 7 mm
B
3.2 x 5 mm
Minimum APR
Temp
Stability
FS = 0
Kv
33V
3.3
25V
2.5
FS = 1
Kv
33V
3.3
25V
2.5
A
20ppm
150ppm/V
100ppm
80ppm
150ppm/V
100ppm
80ppm
B
20ppm
150ppm/V
100ppm
80ppm
120ppm/V
80ppm
50ppm
C
20ppm
150ppm/V
100ppm
80ppm
90ppm/V
50ppm
30ppm
D
20ppm
150ppm/V
100ppm
80ppm
60ppm/V
30ppm
N/S
E
20ppm
120ppm/V
80ppm
50ppm
120ppm/V
80ppm
50ppm
30ppm
F
20ppm
120ppm/V
80ppm
50ppm
90ppm/V
50ppm
G
20ppm
120ppm/V
80ppm
50ppm
60ppm/V
30ppm
N/S
20ppm
90ppm/V
50ppm
30ppm
90ppm/V
50ppm
30ppm
A
Frequencies in ascending order
(FS = 0 selects lower frequency)
H
Frequencies in descending order
(FS = 0 selects higher frequency)
J
20ppm
90ppm/V
50ppm
30ppm
60ppm/V
30ppm
N/S
B
K
20ppm
60ppm/V
30ppm
N/S
60ppm/V
30ppm
N/S
N/S = not supported
Figure 2. Part Number Convention
Example ordering part number: 516AAB000213AAG.
The series prefix, 516, indicates the device is a dual frequency VCXO.
The 1st option code A specifies the output format is LVPECL and powered from a 3.3 V supply. The Absolute Pull
Range code A indicates a temperature stability of ±20 ppm with a tuning slope of ±150 ppm/V. The 3rd option code
B specifies the frequencies are listed in descending order and FS = 0 selects the higher frequency.
The frequency code is 000213. Per this convention, and as indicated by the part number lookup utility at
www.silabs.com/VCXOpartnumber, the two output frequencies are 156.25 MHz and 125 MHz. The package code
A refers to the 5 x 7 mm footprint with six pins. The last A refers to the product revision, G indicates the
temperature range (–40 to +85 °C), and R specifies the device ships in tape and reel format.
14
Rev. 1.0
Si516
4. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 3 illustrates the package details for the Si516. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 3. Si516 Outline Diagram
Rev. 1.0
15
Si5 16
Table 14. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.50
1.65
1.80
b
1.30
1.40
1.50
c
0.50
0.60
0.70
D
D1
5.00 BSC
4.30
4.40
e
2.54 BSC
E
7.00 BSC
4.50
E1
6.10
6.20
6.30
H
0.55
0.65
0.75
L
1.17
1.27
1.37
L1
0.05
0.10
0.15
p
1.80
—
2.60
R
0.70 REF
aaa
0.15
bbb
0.15
ccc
0.10
ddd
0.10
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
16
Rev. 1.0
Si516
5. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si516. Table 15 lists the values for the dimensions shown
in the illustration.
Figure 4. Si516 PCB Land Pattern
Table 15. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
2.54
X1
1.55
Y1
1.95
Notes:
General
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1.
2.
3.
4.
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.0
17
Si5 16
6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin
Figure 5 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 5. Si510/511 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
A
b
c
D
D1
e
E
E1
H
L
L1
p
R
aaa
bbb
ccc
ddd
eee
Min
1.06
0.54
0.35
2.55
4.35
0.45
0.90
0.05
1.17
Nom
1.17
0.64
0.45
3.20 BSC
2.60
1.27 BSC
5.00 BSC
4.40
0.55
1.00
0.10
1.27
0.32 REF
0.15
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
18
Rev. 1.0
Max
1.28
0.74
0.55
2.65
4.45
0.65
1.10
0.15
1.37
Si516
7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 6 illustrates the recommended 3.2 x 5 mm PCB land pattern for the Si516. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 6. Si516 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
1.27
X1
0.80
Y1
1.70
Notes:
General
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1.
2.
3.
4.
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Rev. 1.0
19
Si5 16
8. Top Marking
Use the part number configuration utility located at: www.silabs.com/VCXOPartNumber to cross-reference the
mark code to a specific device configuration.
8.1. Si516 Top Marking
6 C CC CC
T TTT TT
Y Y WW
8.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
6 = Si516
CCCCC = Mark Code
6CCCCC
Line 2 Marking:
TTTTTT = Assembly Manufacturing Code
TTTTTT
Line 3 Marking:
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
WW = Work week.
Characters correspond to the year and
work week of package assembly.
YYWW
20
Rev. 1.0
Si516
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0

Updated Table 1 on page 4.
Updates
to supply current typical and maximum values
for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.

Updated Table 3 on page 5.
Dual
CMOS nominal frequency maximum added.
time maximum values updated.
Enable time parameter added.
Disable

Updated Table 4 on page 6.
CMOS
output rise / fall time typical and maximum
values updated.
LVPECL/HCSL output rise / fall time maximum value
updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum
values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to
48/52%.

Updated Table 5 on page 7.
Phase
jitter test condition, typical and maximum value
updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise
typical values updated.
Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and
Dual CMOS operations.
 Added note to Figure 2 clarifying CMOS and Dual
CMOS maximum frequency.
 Updated Figure 5 outline diagram to correct pinout.
 Updated “8. Top Marking” section and moved to
page 20.

Rev. 1.0
21
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