S i 3 0 0 0 P P T- E V B E VALUATION B OA RD F OR THE S i3 0 0 0 WITH THE P ARALLEL P ORT I NTERFACE Description Features The Si3000PPT-EVB provides the audio system engineer an easy way to evaluate the functionality of Silicon Laboratories’ Si3000 voice band codec solution. The Si3000 chipset can be easily controlled from a PC using the supplied application software (requires Si30xxPPT software Rev 2.1 or above and FPGA Rev 2.1 or above). The Si3000PPT-EVB includes the following: Ability to read and write registers DAC waveform generation from a series of standard waveforms or from a .wav file ADC data capture and display in either time or frequency domain Recommended layout for key components Daisy-chain support when used with Si30xx (Si3034, Si3035, Si3044, or Si3056) products RJ-11 Interface to Handset RJ-11 Connection to Phone Line and Modem Microphone, Speaker Interfaces Line In, Line out Interfaces Functional Block Diagram 12 V Motherboard Mic In Speaker Out Daughtercard SSI PPT FPGA Handset Select Si3000 Line Out Phone Line Handset Line In Line Level Audio I/O Rev. 0.1 10/03 Copyright © 2003 by Silicon Laboratories Si3000PPT-EVB-01 Si3000PPT-EVB Functional Description Optional Call Progress Speaker The Si3000PPT-EVB provides the audio system engineer an easy way to evaluate the Si3000 voice band codec solution. The Si3000PPT-EVB also supports the connection of multiple devices on an SSI interface. The evaluation board provides a straightforward means of evaluating this feature. The evaluation board consists of the Si30xxPPT-EVB motherboard and the Si3000DC_EVB daughter card. A custom ribbon cable is also provided to connect to the parallel port of a PC. Contact a Silicon Laboratories representative for more information. In this document, the Si3000DC-EVB is occasionally referred to as the “daughter card” and the Si30xxPPTEVB as the “motherboard”. The Si3000PPT-EVB refers to the system which consists of both the “motherboard” and “daughter card”. This feature is not utilized by the Si3000 Reset Circuit The Si3000 requires an active low pulse on RESET following powerup and whenever all registers need to be reset. For development purposes, the Si3000PPTEVB includes a reset push button, SW1, that is used by the FPGA to generate the reset pulse of the Si3000. If multiple boards are cascaded together, the reset signal should be generated by the master board. Using the SW1 pushbutton on slave boards does not reset that slave board. Serial Modes The Si3000 supports several different serial modes for a glueless interface to many standard DSP and ASIC serial ports. The serial mode of the Si3000 can be selected by JP3 and JP4 on the motherboard. Motherboard–Daughter Card Connection Line Connection The Si3000DC-EVB connects to the Si30xxPPT-EVB through two sockets: JP1 and JP2. JP1 is a 3x8 socket connection to the digital signals of the DSP-side chip. In addition, a 3.3 V regulated supply is routed to this socket and supplies the power to the digital-side device. JP1 of the daughter card connects to JP2 of the Si30xxPPT-EVB. JP2 is a 2x5 socket connection from the TIP and RING and chassis ground of the line interface to the line-side device. JP2 of the Si3000DCEVB connects to JP1 of the Si30xx PPT EVB. The Si3000PPT-EVB has a physical interfaces designed to connect to the phone line. It is on the daughter card. These interfaces are equivalent and interchangeable. When using the Si3000PPT-EVB in slave mode, one of the line interfaces is used to connect to the phone line, while the other line interface is used to connect to the Master Board Modem Line Interface. This way, both the Si3000PPT-EVB and Si30xxPPTEVB gain access to the phone line without requiring an external phone splitter. Power Supply Handset Interface Power is supplied to the EVB by means of J3 or J4. J3 is a euroblock header that allows for connection to a bench power supply. J4 is a 2.1 mm power jack that allows the use of a wall transformer. A 9 V supply/ 300 mA is typically used, but the onboard voltage regulator also works with a dc voltage between 7.5 V and 20 V. A diode bridge is used to correct polarity. The on-board regulator, U7, provides 5 V to the call progress circuit, the on-board oscillator, and other boards daisy chained to the Si30xxPPT-EVB. This 5 V is further regulated to 3.3 V to power the daughter card and the input/output ports of the FPGA. A third regulator provides 2.5 V for the core voltage of the FPGA. The Si3000PPT-EVB includes a handset interface. This interface is located on the daughter card J1 connector pins 9 and 10. Clock Generation The Si3000 requires an MCLK input. An on-board oscillator (Y1) is used by the FPGA to clock all the subsystems as well as generate and provide the master clock to the Si3000. The FPGA is designed to use a 18.432 MHz oscillator (included with the board). 2 A handset can connect directly to the phone line or the the Si3000 device. The target system is expected to control the DPDT relay to select the handset connection. When the handset is connected to the Si3000, both the Si3000 and handset are disconnected from the phone line. In this case, the Si3000PPT-EVB supplies dc power to the handset through an external 12 Vdc bench supply. The euroblock header, J6, on the daughter card is provided for this connection. 24.5 mA of DC loop current is supplied to the handset. In a voice modem application, the Si3000PPT-EVB is configured in the slave mode, with an Si30xxPPT-EVB acting as the master board. When this system is in the on-hook state, either the Si30xx or the handset can respond to the phone ring and place the system in the off-hook state. Rev. 0.1 Si3000PPT-EVB If the system software chooses to allow the Si30xx EVB to go off hook, the handset is excluded from the phone loop and is connected directly to the Si3000 EVB. Voice traffic is handled by the Si3000 and system software is responsible for creating a virtual voice connection between the handset and the phone system through the Si3000 and Si30xx devices. Microphone Interface A standard 3.5 mm mini-phono connector located on the daughter card connector J2 is used to provide an interface from an external microphone to the Si3000. The input impedance to MIC input of the Si3000 is at least 10 kW. The Si3000 has a programmable preamplification to support many input line levels. If Jumper JP3 on the daughter card is populated, the microphone can be powered directly from the Si3000 MBIAS output. The MBIAS output provides a typical voltage of 2.5 V and can supply up to 5 mA, programmable through an external resistor. For applications that cannot be met by the Si3000’s MBIAS output, the jumper may be removed and an external biasing voltage can be applied to the microphone. Speaker Interface A standard 3.5 mm mini-phone connector is located on the daughter card connector J3. The Si3000 SPKRR and SPKRL outputs are designed to drive 60 W loads directly. To drive a 32 W headset, an external series resistor (30 W) is needed. Driving a 32 W headset directly may result in reduced THD and Dynamic Range performance. The maximum voltage swing is 1 Vrms for either the left or right speaker drivers. The Si3000 speaker outputs have programmable analog attenuation. PC Parallel Port JP13 connects through the Silicon Labs custom ribbon cable to the parallel port of the PC. The parallel port connection allows the designer to read and write the Si3000 register using the evaluation software included with the Si3000PPT-EVB. Configuring the Si3000PPT-EVB The S3000PPT-EVB is used to interface the Si3000 audio codec to a PC or other audio system for easy evaluation. It uses an FPGA to translate the parallel port interface to the SSI bus to communicate to the Si3000. The audio data and control data are communicated from the controlling PC using the aforementioned software. This mode allows the user to evaluate the Si3000 without any lab equipment other than a PC. When in mode 0, the negative edge of FSYNC indicates the starting of the frame, and FSYNC is low until the end of data transfer. By selecting mode 1 operation, the rising edge of FSYNC indicates the start of the frame but is only high for one cycle. To evaluate the Si3000’s multiple device operation, chain the slave boards with JP3 and JP4 on the moterboard to set to Mode 2. See Table 1 for a description of these operating modes. Table 1. Mode Configuration Mode M1 M2 Description 0 0 0 FSYNC frames data 1 0 1 FSYNC pulse starts data frame 2 1 0 Slave mode 3 1 1 Reserved Line Input Interface A standard RCA jack on the daughter card connector J5 is used to provide the line-level audio inputs to the Si3000. The Si3000 has a programmable pre-amplifier. The input impedance of the LINEI is at least 10 k. The Si3000 supports multiple levels of pre-amplification to support various line-levels. Line Output Interface The evaluation board has the ability to interface in two different modes of the SSI bus: 5-bit address space operation is used for the Si3000/34/35/44, and 7-bit address space operation is used for the Si3056. The onboard FPGA will auto-detect the chip and set the appropreate registers. A standard RCA jack on the daughter card connector J4 is used to provide the line-level audio outputs from the Si3000. The Si3000 line output gain is programmable. The maximum output voltage is 1 Vrms. Rev. 0.1 3 Si3000PPT-EVB Evaluation Software The Si3000PPT-EVB includes an easy-to-use graphical interface for controlling the evaluation platform. The software is called Si30xxPPT evaluation software. This software allows the system designer to characterize the Si3000 voice band codec performance without constructing any custom hardware. The evaluation software includes the following features: Ability to read and write the Si3000 registers using the SSI bus DAC waveform generation from a series of standard waveforms or from a .wav file ADC data capture and display in either time or frequency domain using the SSI bus Daisy-chain support Transmit and receive path attenuation and gain settings Exit: Design Tool Register Map: Displays register map of the device Flow Diagram: Displays signal flow diagram of the device. Transhybrid Loss Calculation: Calculate transhybrid loss over frequency Ringing: Helps user program ring validation registers. Signal Windows98 or Windows2000 Available parallel port EPP or ECP parallel port mode for Windows 98 EPP parallel port mode for Windows 2000 450 MHz Pentium II or greater recommended 64 MB of memory or greater recommended Installation The supplied CD contains the Si30xxPPT-EVB windows driver files as well as a setup utility for installing the evaluation software. To install the Si30xxPPT-EVB software, run the installation program on the “Silicon Laboratories Wireline Software CD.” The path for the installation program is Si30xx Evaluation Software\setup.exe. The installer guides the user through the installation process for Si30xxPPT-EVB.exe and the LabVIEW Run-Time engine. Using the Si3000PPT-EVB Application Software A shortcut for starting the application software that controls the Si3000PPT-EVB is installed in the Windows Start Menu under the Programs folder in the “Si30xx Evaluation Software” folder. Application Menus Three pulldown menus are used to configure the operation of the software: 4 Configure: Configure Device: Display hardware status and user configuration. User can set advanced software options. Reset Device: Resets device and executes basic initialization sequences. The application software for the Si30xxPPT-EVB has the following system requirements: Stops the program Stores the audio waveform into .wav files Save: PC System Requirements Run: Rev. 0.1 Help: Displays information about the evaluation board Si3000PPT-EVB Figure 1. Si30xxPPT-EVB Evaluation Software in the Audio Data Monitoring View Audio Data Monitoring View The audio data monitoring view is discussed in the following sections. Receive Audio Data of Channel# Allows selection of channel to control and view. The Audio Data Monitoring view allows the generation of DAC data and the capture and display of ADC data. Operation of the front panel in Line Monitoring view is detailed in the following list. See Figure 1. TX Control DAC Waveform: Selects the waveform to be generated by the DAC. The waveform types are as follows: dc, Sine, Square, Ramp, and .wav file. TX Gain (dB): Selects the transmit path gain/ Rev. 0.1 attenuation. TX Mute: This function is not availabe on the Si3000PPT-EVB Sampling Rate: This function is not availabe on the Si3000PPT-EVB Amplitude: Sets the amplitude of the DAC waveform in either volts or the units of DAC codes. The units are determined by the Amplitude Units control. Frequency: Selects the frequency (Hz) of the waveform to generate. The actual waveform frequency may vary slightly from the entered value. This variation is due to the requirement to fit an integer number of samples into the transmit buffer. The control is updated to reflect the actual waveform frequency generated. The equation for calculating 5 Si3000PPT-EVB the frequency of the waveform is as follows: Actual Frequency = round ((Waveform Frequency/n DAC Sample Rate) x BufferSize) x (DAC Sample Rate/BufferSize) RX Control Monitor Mode: This function is not availabe on the Si3000PPT-EVB RX Gain/Attn (dB): Selects the receive path gain/ attenuation. RX Mute: This function is not availabe on the Si3000PPT-EVB Ring Detect Mode: This function is not availabe on the Si3000PPT-EVB Xmin: Sets the origin of the X-axis when the X Autoscale is disabled. X Zoom: Used to zoom a portion of the displayed waveform when X Autoscale is disabled. The waveform starts at Xmin and 1/X Zoom of the total waveform is displayed. Yo: Sets the origin of the Y-axis when Y Autoscale is disabled. Half of the waveform is displayed above Yo, and half is displayed below Yo. Dialer Dial Number: This function is not availabe on the Si3000PPT-EVB Dial: This function is not availabe on the Si3000PPTEVB Measurement Loop Current: This function is not availabe on the Si3000PPT-EVB Ring Detect Bits: This function is not availabe on the Si3000PPT-EVB Off-Hook: This function is not availabe on the Si3000PPT-EVB DC Level/SINAD: Displays either the dc level of the time domain waveform or the SINAD of the frequency domain waveform. RMS Level/Frequency: Displays either the RMS level of the time domain waveform or the frequency of the largest peak in the frequency domain waveform. Num Avg for FFT: When in FFT display, the software automatically averages waveforms. This panel selects the number of averages to take. Wave Display Controls 6 Display Type: Selects how the ADC data is displayed on the Waveform Graph (time or frequency domain). Amplitude Units: Sets the amplitude units for the Waveform Graph and Amplitude control to either volts or codes. Acquisition: Used to run or pause the CODEC data stream. Upon pausing the acquisition of the data, it displays measurement values regardless of the status of “display measurement” under the configure menu. X Autoscale: Automatically scales the X-axis of the graph to fit the entire waveform. Y Autoscale: Automatically scales the Y-axis to fit the entire vertical range of the waveform. Rev. 0.1 Si3000PPT-EVB Figure 2. Si30xxPPT-EVB Evaluation software in the Register Monitoring View Register Table Display View The Register view allows the Si3000 registers to be read or written. The user interface for the Si3000 Register view is shown in Figure 2. Operation of the front panel in the Si3000 Register view is detailed in the following list: Table: This table displays the contents of the Si3000 voice band codec registers in realtime. Current Digital Side: Displays the DSP side device on the daughter card. Current Linde Side: Displays the Line side device on the daughter card. Register Num: The Si3000 register number to write (in decimal). Rev. 0.1 Register Val: The contents to write to the register selected by the Register Num control (in hexadecimal). Write Regs: Causes the contents of the Register Val control to be written to the Register Num register. Broadcast: Write to all the devices in the chain. FDT: This function is not availabe on the Si3000PPTEVB Off-Hook: This function is not availabe on the Si3000PPT-EVB DCE: This function is not availabe on the Si3000PPT-EVB 7 Si3000PPT-EVB Figure 3. Configuration Device Panel Advanced Configuration Advanced configuration of the application software is accomplished by using the “Configure Device” selection in the “Configure” menu. The configuration panel is shown in Figure 3. The panel contents are detailed in the following list: FFT Window: The FFT window applied to the time domain data before calculating the FFT. Acquisition Buffer Size: This is the size of the buffer, in samples, that is acquired and displayed on the Line Monitoring mode waveform graph. The buffer size can be set between 1024 and 65536 samples in increments of 512 samples. Display Measurement: Takes realtime measurements of audio waveform. 8 Rev. 0.1 Si3000PPT-EVB Figure 4. Si3000 Signal Flow Diagram Signal Flow Diagrams The signal flow diagrams of the Si30xx evaluation software for the Si3000 device shown in Figure 4 assist users with programming the Si3000. SPD: Turns on/off the SPD bit on Register 1, bit 4. LPD: Turns on/off the LPD bit on Register 1, bit 3. HPD: Turns on/off the HPD bit on Register 1, bit 2. MPD: Turns on/off the MPD bit on Register 1, bit 1. CPD: Turns on/off the CPD bit on Register 1, bit 0. HPFD: Turns on/off the HPFD bit on Register 2, bit 4. DLL1: Turns on/off the DLL1 bit on Register 2, bit 2. DLL2: Turns on/off the DLL2 bit on Register 2, bit 1. Line in Gain: Writes to LIG on Register 2. LIM: Turns on/off the LIM bit on Register 2, bit 5. MIC Input Gain: Writes to MCG on Register 2. MCM: Turns on/off the MCM bit on Register 2, bit 2. HIM: Turns on/off the HIM bit on Register 2, bit 1. Rev. 0.1 IIR: Turns on/off the IIR bit on Register 2, bit 0. ADC Volume: Writes to RXG on Register 6. LOM: Turns on/off the LOM bit on Register 6, bit 1. HOM: Turns on/off the HOM bit on Register 6, bit 0. DAC Volume: Writes to TXG on Register 7. SLM: Turns on/off the SLM bit on Register 7, bit 1. SRM: Truns on/off the SRM bit on Register 7, bit 0. Line Out Attenuation: Writes to LOT on Register 9. Speaker Out Attenuation: Writes to SOT on Register 9. 9 Si3000PPT-EVB Figure 5. Transhybrid Loss Transhybrid Loss Calculation When “Transhybrid Loss Calculation” is selected, the Si30xxPPT-EVB software will drive a signal with different frequencies and measure the transhybrid loss based on the following equation: Transhybrid Loss = 20Log(TXpk-pk/RXpk-pk). Frequencies used to measure this start from 100 Hz to 4000 Hz in 20 Hz steps. Ringing This function is not availabe on the Si3000PPT-EVB. 10 Rev. 0.1 Figure 6. Si3000DC-EVB Schematic (1 of 2) Si3000PPT-EVB Rev. 0.1 11 Figure 7. Si3000DC-EVB Schematic (2 of 2) Si3000PPT-EVB 12 Rev. 0.1 Si3000PPT-EVB Si3000DC-EVB Bill of Materials Reference Part C1,C3,C6,C8,C11,C12 C2,C4,C9 C10 D1 JP1 JP2 JP4,JP3 J1 J2,J3 J5,J4 J6 K1 L1,L2 Q1 R9,R1 R3,R2 R4 R7 R8 U1 U2 0.1 uF, 25 V, +/- 20%, 0805, X7R, C0805X7R250104-MNE, Venkel 10 uF, 16 V, +/- 20%, case A, , TA016TCM106MAR, Venkel 10 uF, 25 V, +/- 10%, case C, , TA025TCM106MCR, Venkel DIODE, , , DO-35, , 1N4148, Rectron CON24, , , 3x8 100 mil, , SSW-108-01-T-T, Samtec HEADER 5X2, , , 5x2 100 mil, , SSW-105-01-T-D, Samtec HEADER 2, , , 2x1 100 mil, , 68000-402, Berg Dual RJ-11 Jack, , , RJ11x2, , MTJG-2-64-2-2-1, Adam Tech Phono Jack, , , Thru-Hole, , 161-3504, Mouser RCA JACK, , , thru-hole, , 16PJ097, Mouser Power Connector, , , thru-hole 2, , TSA-2, Adam Tech RELAY DPDT, 4.5V, , TQ2, , TQ2-4.5V, Aromat Ferrite Bead, , , 1206, , BLM31A601S, MuRata NPN, , , SOT-23, , CMPT2222A, Central Semiconductor 0, , , 0805, , CJ21-000-T, KOA 100 k, 1/10W, +/- 5%, 0805, , CR0805-10W-104JT, Venkel 10 k, 1/4 W, +/- 5%, 1206, , CR1206-4W-103JT, Venkel 51, 1/4 W, +/- 5%, 1206, , CR1206-4W-510JT, Venkel 2.2 k, 1/10 W, +/- 5%, 0805, , CR0805-10W-222JT, Venkel Si3000, , , S016, , Si3000, Silicon Laboratories LM317LZ, , , TO-92, , LM317L, SGS Thompson Rev. 0.1 13 Figure 8. Si3000DC-EVB Silkscreen Si3000PPT-EVB 14 Rev. 0.1 Figure 9. Si3000DC-EVB Component Side Si3000PPT-EVB Rev. 0.1 15 Figure 10. Si3000DC-EVB Solder Side Si3000PPT-EVB 16 Rev. 0.1 1 2 J3 9 8 7 14 17 20 23 16 19 22 J4 D2 D4 D3 CON24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 JP2 D1 2.1 mm Power jack Power Connector Footprint of JP7 Top View 24 21 18 12 15 10 11 13 6 5 4 R4 2.2K R1 2.2K 1.6 R13 Vio + R3 2.2K C17 470 uF M1 Vio 1 C30 .33uF JP3 IN U7 OUT M1 AOUT RESETb SDO FC/RGDT SDI MCLK SCLK FSYNCb Vio Vio M0 VA C18 .1uF JP4 M0 4 3 2 1 U1 OUT(2) OUT(1) FB/NC TPS77601DR IN(2) IN(1) EN GND RESET/PG 8 5 6 7 R6 110k R5 196k HEADER 5X2 2 4 6 8 10 C21 10uF Vio C22 .1uF 3 2 1 4 5 TPS76325DBVR EN OUT NC/FB U2 GND IN RJ-11 1 2 3 4 5 6 J1 C5 0.1 uF C4 10uF C12 10uF C8 0.1 uF C16 0.1 uF C3 10uF C7 0.1 uF C2 10uF C6 0.1 uF C11 10uF C19 4.7uF FB1 Vcore C20 10uF C15 0.1 uF C10 10uF C14 0.1 uF C9 10uF FPGA VCCIO Bypass Caps C1 10uF FPGA VCCINT Bypass Caps C13 0.1 uF Figure 11. Si30xx Motherboard Schematic (1 of 3) 7805 3 JP6 RGDT/FSD OFHKb 1 3 5 7 9 JP1 VCC16 GND15 VCC24 GND25 R2 2.2K VCC50 GND52 VCC61 GND66 3 VCC85 GND84 VCC94 GND93 2 GND Rev. 0.1 2 VCC127 GND129 VCC134 GND139 1 Si3000PPT-EVB 17 D5 Vio RESET_INb C27 1uF 20 k R7 Rev. 0.1 R52 2.2K Vio 100 R8 SCLK_IN SDO RESETb SCLK pbRESETb R53 10K SW1 2 4 6 8 10 2 4 6 8 10 R54 10K VA VA 0.1 uF C24 R10 3k R55 10K SDI OSC 820 pF C26 SDI_IN FSYNC_INb FSD_OUT 47 k R9 51 R12 3 7 2 - + 8 11 LM386M-1 OSC Y1 10 R11 4 7 14 0.1 uF C28 C25 1 TP1 TP2 100 uF Place PC Recepticle for Oscillator Pins Mouser Part #575-066700 .038" Diameter U3 5 Figure 12. Si30xx Motherboard Schematic (2 of 2) From Master HEADER 5X2 1 3 5 7 9 JP8 HEADER 5X2 1 3 5 7 9 JP7 To Slave AOUT C23 0.1 uF 6 1 4 8 18 + VA 2 VA C29 0.1 uF J5 RCA JACK Si3000PPT-EVB TDI TCK TDO TMS R51 1K R39 1K Vio R40 1K GND Slave 2 4 6 8 10 EPC1PC8 DCLK DATA OE nCS nCASC U5 2 1 3 4 6 Vio HEADER 5X2 Master Blaster Header 1 3 5 7 9 JP14 TCK Vio Vio Vio Use Socket for EPC1441_3. Mill-Max 110-99-308-41-001 C31 0.1 uF R56 1K Vio GND GND GND Stand Alone Master w/ slaves mSel1 JP10 mSel1 mSel0 8 7 VCC VCC TDO VCC DATA TMS TCK VPP DCLK NC5 VCCSEL NC4 NC1 NC3 NC2 VPPSEL OE nINIT_CONF nCS nCASC GND TDI U8 0K Install R57 only if U8 is not populated R57 R47 1K R48 1K Vio Vio mSel0 JP9 GND Vio Vio M0 20 19 18 17 16 15 14 13 12 11 R49 1K TDI VA Vio Vio R41 10K C32 0.1 uF R42 10K OSC R44 10K CFG Dev Select R43 10K modeSel0 modeSel1 107 108 35 2 74 77 76 143 122 128 105 34 141 142 144 106 55 125 1 7 54 56 124 126 109 110 111 112 113 114 116 39 38 37 36 33 32 31 30 20 21 22 23 26 27 28 29 8 9 10 12 13 17 18 19 DCLK DATA0 NSTATUS CONF_DONE NCONFIG MSEL0 MSEL1 CS DEV_CLRn DEV_OE TDI TMS NRS NWS NCS NCE CLK(1) CLK(2) TCK CLKUSR INPUT(1) INPUT(2) INPUT(3) INPUT(4) DATA(1) DATA(2) DATA(3) DATA(4) DATA(5) DATA(6) DATA(7) I/O(17) I/O(18) I/O(19) I/O(20) I/O(21) I/O(22) I/O(23) I/O(24) I/O(9) I/O(10) I/O(11) I/O(12) I/O(13) I/O(14) I/O(15) I/O(16) I/O(1) I/O(2) I/O(3) I/O(4) I/O(5) I/O(6) I/O(7) I/O(8) VCC127 Vio U4 EP1K30TC144 NCEO TDO INIT_DONE RDYNBUSY I/O(73) I/O(74) I/O(75) I/O(76) I/O(77) I/O(78) I/O(79) I/O(80) I/O(65) I/O(66) I/O(67) I/O(68) I/O(69) I/O(70) I/O(71) I/O(72) I/O(57) I/O(58) I/O(59) I/O(60) I/O(61) I/O(62) I/O(63) I/O(64) I/O(49) I/O(50) I/O(51) I/O(52) I/O(53) I/O(54) I/O(55) I/O(56) I/O(41) I/O(42) I/O(43) I/O(44) I/O(45) I/O(46) I/O(47) I/O(48) I/O(33) I/O(34) I/O(35) I/O(36) I/O(37) I/O(38) I/O(39) I/O(40) I/O(25) I/O(26) I/O(27) I/O(28) I/O(29) I/O(30) I/O(31) I/O(32) 3 4 14 11 131 132 133 135 136 137 138 140 101 102 117 118 119 120 121 130 91 92 95 96 97 98 99 100 81 82 83 86 87 88 89 90 68 69 70 72 73 78 79 80 51 59 60 62 63 64 65 67 41 42 43 44 46 47 48 49 R26 47K R27 47K R14 47K Vio R28 47K R15 47K 2 4 6 8 10 HEADER 5X2 1 3 5 7 9 JP12 Test Point Connector TDO s4 D3 D4 D5 D6 D7 nIRQ nWAIT s5 nDSTB nWRITE s3 D0 c2 D1 nASTB D2 R25 47K m OH mRGDT m FC mFS mSCLK mRST m C1A mS DI m SDO mM0 mM1 Figure 13. Si30xx Motherboard Schematic (3 of 3) R50 1K TMS M0 M1 RESETb SCLK_IN FSD_OUT pbRESETb RESET_INb FSYNC_INb SDI_IN RGDT/FSD OFHKb MCLK SCLK FSYNCb SDO FC/RGDT SDI EPC2LC20 Use Socket for EPC2LC20. Mill-Max 540-99-020-400000 1 2 3 4 5 6 7 8 9 10 Vio Vio GND GND M1 VCC16 VCC50 GND15 GND25 Board Config. GND52 GND VCC85 GNDINT(1) GNDINT(2) GNDINT(3) GNDINT(4) GNDINT(5) GNDINT(6) 6 15 25 40 52 58 GND66 GND84 GND93 GNDINT(7) GNDINT(8) GNDINT(9) GNDINT(10) GNDINT(11) GNDINT(12) GNDINT(13) 66 84 93 104 123 129 139 GND129 GND139 Rev. 0.1 5 VCC24 16 50 75 85 103 127 VCC134 VCCINT(1) VCCINT(2) VCCINT(3) VCCINT(4) VCCINT(5) VCCINT(6) VCC94 5 24 45 61 71 94 115 134 VCCIO(1) VCCIO(2) VCCIO(3) VCCIO(4) VCCIO(5) VCCIO(6) VCCIO(7) VCCIO(8) VCC61 Vcore R29 47K R16 47K R30 47K R17 47K R31 47K R18 47K R32 47K R19 47K R33 47K R20 47K R35 47K R22 47K 1 3 5 7 9 11 13 15 JP11 2 4 6 8 10 12 14 16 R36 47K R23 47K R37 47K R24 47K mSCLK m C1A DG ND m SDO DG ND mM1 DG ND mRGDT R38 47K JP13 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 2 4 6 8 10 12 14 16 18 20 22 24 26 nDSTB s3 c2 nASTB HEADER 13X2 Parallel Port Connector nWRITE 1 D0 3 D1 5 D2 7 D3 9 D4 11 D5 13 D6 15 D7 17 nIRQ 19 nWAIT 21 s5 23 s4 25 HEADER 8X2 Chip Signal Connector mFS mRST DG ND mS DI mM0 DG ND m OH m FC R34 47K R21 47K Si3000PPT-EVB 19 Si3000PPT-EVB Bill of Materials: Si30xx Motherboard Item Reference 10 2 14 3 1 4 2 5 1 6 1 7 1 8 1 9 1 10 4 11 1 12 1 13 1 14 1 15 4 16 1 17 1 18 1 19 1 20 2 21 1 22 1 23 1 24 1 25 1 26 5 27 1 28 1 29 1 30 1 31 1 32 1 33 34 35 36 20 Qty 1 1 1 1 25 37 38 2 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6 7 1 1 1 1 1 1 1 1 1 6 1 4 4 C1,C2,C3,C4,C9,C10,C11, C12,C20,C21 C5,C6,C7,C8,C13,C14,C15, C16,C23,C24,C28,C29,C31, C32 C17 C18,C22 C19 C25 C26 C27 C30 D1,D2,D3,D4 D5 FB1 JP1 JP2 JP3,JP4,JP9,JP10 JP6 JP7 JP8 JP11 JP14,JP12 JP13 J1 J3 J4 J5 R1,R2,R3,R4,R52 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14,R15,R16,R17,R18,R19, R20,R21,R22,R23,R24,R25, R26,R27,R28,R29,R30,R31, R32,R33,R34,R35,R36,R37, R38 R40,R39 R41,R42,R43,R44,R53,R54, R55 R47,R48,R49,R50,R51,R56 SW1 TP1 TP2 U1 U2 U3 U4 U7 U5 Y1 R57 N/A N/A Part 10uF, 10 V, ±10%, 1206, , C1206X7R100-106KNE, Venkel 0.1 uF, 16 V, ±10%, 0603, , C0603X7R160-104KNE, Venkel 470 uF, 25 V, ±20%, radial 10x16, , UVX1E471MPA, NIC Components .1uF, 25V, , 0805, , C0805X7R250-104KNE, Venkel 4.7uF, 10V, +/-10%, 1206, , TDKC3216X5RA475KT, CLASSIC COMP 100 uF, 16 V, ±10%, radial 6.3x11, , , TTI 820 pF, 50 V, ±5%, 0805, , C0805COG500-821JNE, Venkel 1uF, 10 V, ±10%, 1206, , C1206X7R100-105KNE, Venkel .33uF, 25V, , 0805, , C0805G334Z3NT, CLASSIC COMP DIODE, 30 V, 0.5 A, SOD-123, , MBR0530T1, Motorola DIODE, 400 mA, 75 V, DO-35, , 1N4148, Diodes, Inc. Ferrite Bead on wire, 3x1x4 (mm), , thru-hole 2, , 2743015112, Fair-Rite HEADER 5X2, , , 5x2 100 mil, , TMM-105-01-G-D, Samtec CON24, , , 3x8 100 mil, , TSW-108-07-G-T, Samtec 3X1 Header, , , 3x1 100 mil, , 68000-403, Berg Electronics 2X1 Header, , , 2x1 100 mil, , 517-6111TN, Mouser HEADER 5X2, , , 10 pin thru-hole, , TSW-105-08-T-D-RA, Samtec HEADER 5X2, , , 10 pin thru-hole, , SSW-105-02-T-D-RA, Samtec HEADER 8X2, , , 8x2 100 mil, , , HEADER 5X2, , , 5x2 100 mil, , , HEADER 13X2, , , 13X2 100 mil, , 13x2 pin Header with Shroud, Mouser RJ-11, , , thru-hole 6, , 154-0L6641, Mouser Power Connector, , , thru-hole 2, , TSA-2, Adam Tech 2.1 mm Power jack, , , thru-hole 3, , ADC-002-1, Adam Tech RCA JACK, , , thru-hole, , 16J097, Mouser 2.2K, , , 0805, , CR0805-10W-222JT, Venkel 196k, , , 0805, , MCHRIDEZHFX1963E, Classic Comp 110k, , , 0805, , CR21-114J-T, Classic Comp 20 k, 1/10 W, ±1%, 0805, , NRC10F2002TR, NIC Components 100, 1/4 W, ±1%, 1206, , MCR18EZHMFX1000, Rohm 47 k, 1/10 W, ±5%, 0805, , NRC10J473TR, NIC Components 3 k, 1/10 W, ±5%, 0805, , NRC10J302TR, NIC Components 10, 1/10 W, ±1%, 0805, , NRC10F10R0TR, NIC Components 51, 1/10 W, ±5%, 0805, , CR21-510J-T, AVX 1.6, , +-5%, 1206, , CR1206-8W-1R6JT, Venkel 47K, , , 0603, , CR0603-16W-473JT, Venkel 1K, , , 0603, , CR0603-16W-1002FT, Venkel 10K, , , 0603, , CR0603-16W-1002FT, Venkel 1K, , , 0603, , MCR03FZHJ102, TTI SW PUSHBUTTON, , , thru-hole 4, , 101-0161, Mouser Test Point, , , thru-hole, , 151-207, Mouser Test Point, , , thru-hole, , 151-203, Mouser TPS77601DR, , , 8-Pin SOIC, , , Texas Instruments TPS76325DBVR, , , 5-Pin SOT-23, , , Texas Instruments OP-AMP, , , M, , LM386M-1, National Semi EP1K30TC144, , , TQFP-144, , EP1K30TC144-3, Altera 7805, , , TO-220AB, , uA7805CKC, Texas Instruments Socket, , , DIP-8, ,110-99-308-41-001, Mill-Max PC Recepticle, .038" Diameter, 575-06670, Mouser 0K, , , 0603, , CR0603-16W-000T, Venkel 1/2" Plastic Standoff Plastic Screw Rev. 0.1 Figure 14. Si30xx Motherboard Schematic (1 of 3) Si3000PPT-EVB Rev. 0.1 21 Figure 15. Si30xx Motherboard Component Layer Si3000PPT-EVB 22 Rev. 0.1 Figure 16. Si30xx Motherboard Solder Layer Si3000PPT-EVB Rev. 0.1 23 Smart. Connected. Energy-Friendly Products Quality www.silabs.com/products www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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