AN67: Si3050/52/54/56 Layout Guidelines

AN67
Si3050/52/54/56 L AYOUT G UIDELINES
1. Description
The Si305x chipsets improve upon Silicon Laboratories’
groundbreaking family of silicon direct access
arrangement (DAA) products by providing the highest
integration, lowest cost, and smallest area DAA solution
for modem and voice applications. Silicon Laboratories’
DAA chipsets consist of two devices. These two
integrated circuits are commonly referred to as the
digital-side device and the line-side device. This
nomenclature refers to which portion of the circuit each
chip interfaces: the digital logic of the system or the
telephone line. When designing a board with the
Si305x, there are several layout considerations that will
assist the printed circuit board designer in developing a
product
that
meets
the
target
application’s
requirements. This document provides guidelines for
board design layout, review, and modification using the
Si305x chipsets.
1.1. Form Factor Overview
The layout guidelines for the Si3050/52/54/56 are
similar, but there are some differences depending on
form factor or application. Typically, PCI, CNR, and
AMR designs are larger board area designs and have
more freedom for different component packages (i.e.,
thru-hole versus surface mount) and spacing than other
types of designs. PCI, CNR, and AMR guidelines have
been grouped together except where there are form
factor specific requirements. MiniPCI and MDC form
factors are much smaller and typically have limited
options for component packages and restrictive spacing
requirements. Finally, the Si3050 is typically used in
applications where channel density is at a premium.
Therefore, the Si3050 layout has been optimized to
allow for multiple channels to be placed adjacent to
each other in a customer design. The Si3050 digitalside device is available in the TSSOP-20 or QFN-24
package, and the associated line-side device is
available in the TSSOP-16, SOIC-16, or QFN-20
Rev. 0.5 5/14
package. The Si3050 schematic diagrams and layout
examples included in this document refer to the TSSOP
packages for both the system-side and the line-side
devices. Although the pin numbers for specific signals
do change between packages, the relative ordering of
the signals is the same for the different package
options, and the layout guidelines presented herein are
generally applicable regardless of which package option
is selected.
1.2. Placement Guidelines
Figure 27 on page 25 shows the typical application
circuit for the line-side circuit of the DAA. Note that, for
Si3050 designs, it is recommended that zero-ohm
resistors R15 and R16 be replaced with ferrite beads in
order to decrease emissions (see Si3050+Si3011/18/19
data sheet). Figures 1–4 depict typical placement of the
chipset, discrete components, and the RJ11 connector
for the Si3050, Si3052 PCI, Si3054 CNR, and Si3054
MDC. Note the placement of U1 (the Si305x digital-side
chip) and U2 (the Si3018/Si3019 line-side chip). U1, U2,
C1, and C2 should be placed so that the distance from
U1 to U2 through the C1, C2 capacitors is less than 2
inches. Place R12 and R13 near the C1A, C2A pins on
the Si305x. Use a minimum of 15 mil thick traces for this
connection. Aligning the Si3050/54/56 digital-side chip
so that the C1A/C2A pins face pins 1–8 of the line-side
chip makes some of the other specific layout guidelines
easier to implement.
With the Si3052 digital-side chip, the C1A/C2A pins are
typically not aligned with the C1B/C2B pins on the lineside device. This alignment is a result of having to route
the large number of PCI lines to the PCI edge
connector. Figure 6 on page 4 shows a typical routing of
the C1A/C2A lines for the Si3052.
Utilizing this placement also allows the design to closely
resemble the Silicon Laboratories’ example layouts,
enabling the designer to directly follow these guidelines.
Copyright © 2014 by Silicon Laboratories
AN67
AN67
Figure 1. Si3050 Placement
R16
R10
Q3
C7
R9
C1
U2
C80
C50
C51
R1
C89 C40
C53
Z1
C4
R3
D10
C81
D11 D12
C55
C56
C54
C84
C85
R50
C41
R52
C52
C82
C60
U1
C86
Figure 2. Si3052 PCI Placement
Figure 3. Si3054 CNR Placement
2
R51Y1
Rev. 0.5
C57
C58
C59
R58
R57
R55
U3
R56
R62
C100
LS1
Q10
C90
C10
R6
C9
R15
R2
Q2
C2
C6
R90
C3
Q1 R5
FB1FB2RV1
C8
Q4
Q5
R14
D1
RJ1
R7
C5
R8
R59
R60
R12
R13
R11
R4
C83
C88
C87
AN67
Figure 4. Si3054 MDC Side 1 Placement
R9 C10
Q2
Z1
Q3
C4
D1
Y2 Y1
C3
D2
Q1
U2
JP1
Q6
U1
C1
C2
Q5
RV1
Q4
C8
C9
C52
JP2
Figure 5. Si3054 MDC Side 2 Placement
Rev. 0.5
3
AN67
1.3. Isolation Barrier Creepage Spacing
Considerations
A device that connects to the telephone network
interfaces to an environment where high-voltage ring
events, transients, and even lightning-induced surges
can occur. One of the principal purposes of a DAA is to
provide isolation of a higher voltage interface, in this
case the telephone line, from a lower voltage interface,
or ground-referenced integrated circuitry. In the telecom
industry, these areas of the circuit are commonly
referred to as telephone network voltage (TNV) for the
high-voltage interface, and safety extra-low voltage
(SELV) for the low-voltage interface. The spacing
between high-voltage components and traces and lowvoltage components and traces is commonly referred to
as the isolation barrier.
The highlighted area of the modem in Figure 6 is the
isolation barrier.
The Silicon Laboratories DAA utilizes high-voltage
capacitors to maintain isolation while providing a means
of communication across the isolation barrier. In
addition, spacing is required between the high-voltage
components to the low-voltage components in order to
meet several telecom, EMC, and safety specifications.
For more details on the various safety requirements,
consult the Silicon Laboratories application note "AN17:
Designing for International Safety Compliance" as well
as your own safety experts and consultants.
Silicon Laboratories recommends the following spacing
guidelines and capacitor selection for the TNV to SELV
isolation barrier, grouped by application.
PCI/CNR/AMR/ACR Modem: Use through-hole Y2
class capacitors for the C1, C2, C8, and C9
components, and ensure a 5 mm wide isolation barrier
from TNV to SELV. A properly implemented design
using these guidelines should provide a minimum of
5 kV of longitudinal surge immunity.
Isolation Barrier
Figure 6. Si3052 Isolation Barrier
4
Rev. 0.5
AN67
Modem-on-Motherboard
or
Custom
PC
Motherboard Riser: If possible, use through-hole Y2
class capacitors for the C1, C2, C8, and C9
components, and ensure a minimum of a 5 mm wide
isolation barrier from TNV to SELV. A properly
implemented design using these guidelines should
provide a minimum of 5 kV of longitudinal surge
immunity.
If surface mount components are required, use Y2
class, 22xx package, surface mount capacitors for
isolation. Maintain an isolation barrier at least as wide
as the spacing between the metal terminals of the
capacitors. If possible, a 5 mm wide isolation barrier
from TNV to SELV should be implemented in this case
as well. A properly implemented design using these
guidelines should provide a minimum of 5 kV of
longitudinal surge immunity.
MDC/MiniPCI Modem: Use surface mount Y2 class
capacitors for the C1, C2, C8, and C9 components,
maintaining an isolation barrier at least as wide as the
spacing between the metal terminals of the capacitors.
To ensure a minimum of 3 kV longitudinal surge
immunity, this spacing should be 3.5 mm or greater.
VIO pins. The Si3052 has several bypass capacitors
that must be placed in close proximity to the VIO pins
with short loops to GND. These capacitors use C53/
C54, C55/C56, C57/C58, and C59/C60. In addition, the
C50 capacitor on the VA pin, and the C50/C51 capacitor
on the VD pin should be placed in close proximity to U1
with short loops to ground.
The Si3052 is connected to ground through the
exposed paddle at the bottom of the package. To
ensure the Si3052 package attaches reliably to the
exposed paddle, a 5 mm square pad should be used.
The solder paste should be laid out in a 4x4 matrix of
1 mm square pads on a 1.2 mm pitch (see Figure 8). It
is recommended that a power pad be placed on the
back of the Si3052 board directly behind the exposed
die paddle pad. The combination of these two pads
creates an additional bypass capacitor that assists with
high-frequency bypassing of the Si3052 power supply.
Note: Consult your safety expert for further information about
the supplementary insulation requirements of your
design.
Other Small Form-Factor Applications: Use surface
mount Y2 class capacitors for the C1, C2, C8, and C9
components, maintaining an isolation barrier at least as
wide as the spacing between the metal terminals of the
capacitors. To ensure a minimum of 3 kV longitudinal
surge immunity, this spacing should be 3.5 mm or
greater. Customers may wish to build designs that can
support different levels of surge immunity based on
different customer requirements.
Note: Consult your safety expert for further information about
the supplementary insulation requirements of your
design in advance.
Figure 7. Si3050/54/56 Placement and Routing
of C50–C52
To ensure a minimum of 5 kV of surge immunity, use Y2
class, 22xx package, surface mount capacitors.
1 mm
.2 mm
1 mm
1.4. Si305x Power Supply Bypass Capacitor Layout Requirements
On the Si3050/54/56, one of the main layout
considerations for the digital-side chip (U1) is the
placement of the bypass capacitors (C50, C51, and, if
required, C52). Capacitors C50 and C51 are the bypass
capacitors for VA and VD, respectively. Figure 7 shows a
typical placement of C50 and C51. The designer should
focus on minimizing the length of the C50 connection
between the VA and GND pins and the length of the C51
connection between the VD and GND pins on U1.
Figure 9 shows the bypass configuration of the Si3052
Rev. 0.5
Figure 8. Si3052 Ground Pad Solder Paste
Matrix on a 5x5 mm Pad
5
AN67
C40
C41
R51
R52
Y1
XOUT
XIN
Figure 10. Crystal Circuit
Figure 9. Si3052 Power Supply Bypassing
1.5. Si3052/54 Crystal Layout
Requirements
The Si3052/54 incorporates a crystal interface for
generation of a clock reference. For designs that use a
crystal as shown in Figure 10, the following layout
guidelines should be followed:

The loop formed by XIN, Y1, and XOUT should be
minimized and routed on one layer of the PCB.
 The loop formed by Y1, C40, and C41 should be
minimized and routed on one layer of the PCB.
 The route from the GND pin to C40 and C41 should
be as direct as possible and, if possible, on one layer
of the PCB.
These guidelines also help minimize issues with
emissions. An example layout is shown in Figures 11–
13.
Figure 11. Si3052 PCI Y1 to U1 Routing
Figure 12. Si3054 CNR Y1 to U1 Routing
6
Rev. 0.5
AN67
Figure 13. Si3054 MDC Y1 to U1 Routing
1.6. Si3018 Layout Recommendations
FB1, FB2, RV1, R15, R16, C8, and C9 should be placed
as close as possible to the RJ11 as shown in Figures
14–16. Note that, for Si3050 designs, it is
recommended that zero-ohm resistors R15 and R16 be
replaced with ferrite beads in order to decrease
emissions (see Si3050+Si3011/18/19 data sheet). The
metallic surge protection device (RV1) should be
located close to the RJ11 connector. It is important for
the routing from the RJ11 connector through the ferrite
beads FB1 and FB2 and the resistors R15 and R16 to
be well matched. C8 and C9 should be placed so there
is minimal distance between the nodes where they
connect to chassis ground. The traces from the TIP and
RING connections on the RJ11 through the EMC
capacitors C8 and C9 to chassis ground should be kept
as short as possible and should be well matched.
Figure 15. Si3052/54 PCI/CNR Placement and
Routing of FB1, FB2, RV1, C8, C9, R15, and R16
Figure 14. Si3050 Placement and Routing of
FB1, FB2, RV1, C8, C9, R15, and R16
Rev. 0.5
7
AN67
Once these components have been placed, the
designer can continue with the layout by adding Q4, Q5,
R2, and R9. All traces connecting these components
should be 15 mil in thickness. Place Q4 so that the area
of the loop formed from U2 pin 13 to the base of Q4 and
from U2 pin 12 to the emitter of Q4 is minimized. Place
Q5 so that the loop from pin 16 through R2 to the base
of Q5 and through the emitter to pin 14 is short. The
loop formed from U2 pin 4 to R9 to U2 pin 15 should
also be made as small as possible.
The IGND traces are those traces that connect directly
from a capacitor or resistor to pin 15 of the line-side
device. They should be routed on the PCB using 15 mil
width traces.
Example layouts of these critical traces and
components around the line-side device are shown in
Figures 17–19:
Figure 16. Si3054 MDC Placement and Routing
of FB1, FB2, RV1, C8, C9, R15, and R16
After the Si305x system-side device, Si3018/19 lineside device, C1, and C2 have been placed, and the
isolation barrier has been defined according to the
recommendations described previously in this
document, the designer should place the diode bridge
and route the accompanying traces from the Si3018/19
device pin 11 through C3 to the Si3018/19 device and to
the IGND pin. C3 should be placed across the diode
bridge, and the area of the loop formed from Si3018/19
pin 11 through C3 to the diode bridge and back to
Si3018/19 pin 15 should be minimized. An example of
this routing for a variety of applications is shown in
Figures 17–19.
Capacitors C5 and C6 provide regulation of the supplies
powering U2. The loop formed by C5 to pins 15 and 7
and the loop formed by C6 to pins 15 and 10 should be
made as small as possible. The trace back to pin 15 is
thicker because multiple loops use this path.
8
Figure 17. Si3050 Placement and Routing of
C3, Diode Bridge, Q4, Q5, R9, R2, C5, and C6
Figure 18. Si3052/54 PCI/CNR Placement and
Routing of C3, Diode Bridge, Q4, Q5, R9, R2,
C5, and C6
Rev. 0.5
AN67
Figure 19. Si3054 MDC Placement and Routing
of C3, Diode Bridge, Q4, Q5, R9, R2, C5, and C6
Finally, the layout can be completed by the addition of
the remainder of the components in the line-side region
and routing of the remainder of the signals. Although the
layout considerations for these traces are not as
stringent as the previous components and traces, it is
recommended that the PCB designer follow these
example placements and layouts as closely as possible.
Example layouts in a variety of form factors are shown
in Figures 20–22.
Rev. 0.5
9
AN67
Figure 20. Si3050 Finished Layout Line-Side Portion
Figure 21. Si3052/54 PCI/CNR Finished Layout Line-Side Portion
10
Rev. 0.5
AN67
1.8. PCI Layout Considerations
The PCI Specification Revision 2.3 contains a section
covering PCI board mechanical requirements. All PCI
board
designs
should
incorporate
these
recommendations. They can be found in the Revision
2.3 PCI Specification Section 4.4.3. The PCI
Specification may be obtained from the PCI SIG at
http://www.pcisig.com/home.
1.9. Small Form Factor Considerations
In small form factor applications, there are a number of
considerations separate from other applications. An
important consideration in small form factor designs is
the heat dissipation under worst case conditions. Small
form factor designs have less board mass to dissipate
heat, so special precautions should be taken:

Figure 22. Si3054 MDC Finished Layout
Line-Side Portion
1.7. Assembly Considerations
There are several steps that can be taken in layout to
ensure that the assembly process is successful. An
example of an assembly-related error is the installation
of a polarized capacitor with the polarity backwards.
Stenciling the board with a plus sign on the correct side
of C4 if a polarized capacitor is used to indicate the
proper orientation for that capacitor can prevent this.
Also, indicating pin 1 on the board with a stencil marking
improves the chances that the integrated circuits will be
installed correctly. The silkscreen for Z1 should also
have a marking to indicate the cathode placement.
The designer should use several footprints for a given
component to allow for multiple vendor choices. Popular
components using multiple footprints are C1, C2, C8,
C9, and Z1.
Finally, all 3-pin devices’ orientation should be carefully
checked to ensure that it matches the schematic symbol
and routing implementation.
The Silicon Labs DAA uses multiple components to
distribute the power that every DAA must dissipate.
This distribution of power among multiple
components allows the layout designer the flexibility
to space these components apart for a more
thermally robust design.
 U2, Q3, Q4, Q5, R1, R3, R4, R10, and R11 should
be spaced as far away from each other in the lineside section of the layout as possible. When
designing a double-sided board, optimal thermal
performance is achieved by ensuring that these
high-power components are not placed directly
underneath each other when placing them.
 Increase the size of the collector pads for Q3, Q4,
and Q5 to improve the heat transfer from the die of
these devices into the board.
 Fill the open area underneath the U2 package with
IGND trace. An IGND pad should be placed on the
back side directly underneath the body of the U2
package. Multiple vias should be used to stitch
between the two pads to improve thermal transfer.
This improves the heat transfer from the U2 die into
the board.
Adding additional copper layers within the layers of the
PCB can significantly improve the thermal performance
of the design. A 4-layer board, with the inner layers
underneath the line-side circuitry connected to IGND, is
recommended.
The Silicon Labs' next generation DAA uses multiple
components to distribute the power that every DAA,
including other silicon DAAs and transformer-based
architectures, must dissipate under certain line
conditions.
Taking these steps will assist in the assembly process
and ease future troubleshooting and substitutions.
Rev. 0.5
11
AN67
The Silicon Labs architecture allows space to be
designed between components and ensures the
temperature of some components does not become too
high. Temperature measurements on other DAA
architectures that use only one or two components to
dissipate the majority of the power have shown
excessive temperature levels on some components.
This can lead to performance and reliability issues. The
Silicon Laboratories architecture does not exhibit this
issue as long as careful component, layout, and
placement considerations are made. Care should be
taken, especially in MDC designs, due to the small form
factor.
The higher power devices dissipate various amounts of
power in different modes and under different loop
conditions. In the worst case, the power dissipation for
R1, R3, R4, R10, and R11 can be between 253 mW and
approximately
450 mW,
depending
on
which
component is measured, what mode the DAA is in, and
the line condition.
Silicon Laboratories’ reference design recommends
2010 package resistors for R1, R3, R4, R10, and R11,
which are usually rated as 1/2 W, depending on the
supplier. In some cases, 1210 package devices have a
1/2 W rating, so they would be acceptable as well for 0–
70 ºC operation. Another option is to use two 1206
resistors (1/4 W rating each) in parallel with the correct
parallel resistance combination to match the original
value. These would have to be 1% tolerance, 1/4 W
devices. R10 should be a minimum of 1/4 W rated
device.
In some cases, 2010 package resistors are more widely
available than 1210 package devices. That is the
reason they are used in the Silicon Laboratories MDC
reference design.
Q3, Q4, and Q5 also dissipate significant amounts of
power in various modes under different line conditions,
up to 180 mW (but not all at the same time). Those
devices' maximum rated junction temperature is 150 ºC.
Calculations of the junction temperature can be made
using the JA values that the data sheets provide, but
these are usually not very accurate due to variable
testing conditions and different methods of
measurement. Direct temperature measurements for
these components provide a closer estimate of the
junction temperature. Using this data along with the JC
or JC variables from the SOT-23 or SOT-89 transistor
vendors, the junction temperature may be estimated. To
obtain more thermal margin, use SOT-89 transistors for
any of these three components.
12
Every board layout has different thermal performance.
The design variables that affect thermal performance
are as follows:

Component package selection—Q3, Q4, Q5 SOT-23
or SOT 89, and R1, R3, R4, R10, R11.
 Component placement—Spacing these components
far apart, with none of them directly underneath each
other or the Si3018 if a double-sided design is
implemented.
 Layout of traces—Using thick traces, with additional
node-connected copper on the trace and inner
layers improves the thermal performance of the Q3,
Q4, Q5 components.
 Number of board layers—Using four layers has
demonstrated improved performance over two
layers, with IGND-connected fill on the inner layers
of the line-side portion.
1.9.1. Small Form Factor TNV-SELV Isolation Barrier
Creepage
Another difference in small form factor DAAs is the
creepage distance from TNV to SELV. For applications
that are targeted for global telecom regulatory
compliance, Y2 class surface mount capacitors should
be implemented for C1, C2, C8, and C9. These
capacitors may be available in a variety of packages,
including 1808, 2211, and 2220. Silicon Laboratories
recommends that the minimum spacing from TNV to
SELV for the isolation barrier on the rest of the board be
derived from the spacing between the terminals of the
isolation capacitors. For example, if 1808 Y2 class
capacitors that have spacing between the terminals of
4.0 mm are used for C1, C2, C8, and C9, then the width
of the isolation barrier between TNV and SELV circuitry
everywhere else on the board should be a minimum of
4.0 mm.
Note: Consult your safety expert for further information about
the supplementary insulation requirements of your
design.
Rev. 0.5
AN67
1.10. Si3050 Layout Check List
Table 1 is a checklist that the designer can use during the layout process to ensure all the recommendations in this
application note have been implemented. Note that, for Si3050 designs, it is recommended that zero-ohm resistors
R15 and R16 be replaced with ferrite beads in order to decrease emissions (see Si3050+Si3011/18/19 data sheet).
Table 1. Si3050 Layout Check List

#
Layout Items
Required
1
U1 and U2 are placed so that pins 11–20 of U1 are facing pins 1–8 of U2. C1 and C2 are
placed directly between U1 and U2. Keep R12 and R13 close to U1.
2
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. See the section entitled 1.3."Isolation Barrier Creepage Spacing Considerations" on page 4.
3
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3019 is not close to the trace from R31 to the RNG1 pin on
the Si3019 (pin 8).
4
Place R30–R33, and C30–C31 as close as possible to the RNG1 and RNG2 pins (pins 8
and 9), ensuring a minimum trace length from the RNG1 or RNG2 pin to the R31 or R33
resistor. In order to space the R31 component further from the trace from C2 to the C2B
pin, it is acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
5
The area of the loop from C50 to U1 pin 17 and from C51 to pin 16 back to pin 18
(DGND) should be minimized. The return traces to U1 pin 18 (DGND) should be on the
component side.
6
The digital ground plane is made as small as possible, and the ground plane has
rounded corners.
7
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND.
8
C3 should be placed across the diode bridge, and the area of the loop formed from
Si3019 pin 11 through C3 to the diode bridge and back to Si3019 pin 15 should be minimized.
9
FB1, FB2, R15, R16, and RV1 should be placed as close as possible to the RJ11.
10
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
11
Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, R15, R16, RV1, C8, C9, and
F1.
12
The routing from TIP and RING of the RJ11 through the ferrite beads should be well
matched.
13
The traces from the RJ11 through the Ringer Network to U2 pin 8 and pin 9 should be
well matched. These traces may be up to 10 cm long.
14
Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is
short.
Rev. 0.5
13
AN67
Table 1. Si3050 Layout Check List (Continued)

#
Layout Items
Required
15
There should be no digital ground plane in the DAA Section.
16
Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
17
R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be
less than 20 mm.
18
Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
19
The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the
emitter of Q4 should be minimized.
20
The trace from C7 to U2 pin 15 should be short and direct.
21
The trace from C3 to the D1/D2 node should be short and direct.
22
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to
any SELV component, pad or trace.
23
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
24
Cathode marking for Z1.
25
Pin 1 marking for U1 and U2.
26
Space and mounting holes to accommodate for fire enclosure if necessary.
Small Form Factor Specific Guidelines
14
27
Space U2, Q4, Q5, R1, R3, R4, R10, and R11 far away from each other in the line-side
section of the layout.
28
Make the size of the collector pads for Q3–Q5 larger to improve heat dissipation. Implement collector pads on the back side of the board and connect the two with multiple vias
to improve heat transfer.
29
TNV to SELV creepage matches the spacing between the surface mount capacitor terminals.
30
The area underneath the body of U2 should be filled with IGND trace, and an IGND pad
should be placed on the back side directly underneath the body of the U2 package. Multiple vias should be used to stitch between the two pads to improve thermal transfer.
31
Using IGND planes on inner layers is useful in attaining uniform heat transfer and dissipation.
Rev. 0.5
RGDT
DRX
DTX
PCLK
FSYNC
19
18
C2A 14
TGD 11
RESET 13
TGDE 12
Si3050
9 AOUT/INT
10 RG
8
7
5
6
GND
20
17
VD
16
VA
15
C1A
SCLK
CS
SDI_Thru
U1
SDI
SDO
Rev. 0.5
R13
R12
C2
C1
20
C5
C4
IB
RX
8
7
RNG1
VREG
C2B
5
C1B
6
4
QE
2
DCT
3
VREG2 10
RNG2 9
SC 11
C6
R31
C30
R30
R14
19
Q5
Make the size of the collector pads for Q4 and Q5 larger
to improve heat dissipation. Implement collector pads on
the back side of the board and connect the two with
multiple vias to improve heat transfer.
22,29
C3
Q4
FB1
FB2
C9
C8
14
Figure 23. Si3050 Layout Guidelines
TNV to SELV creepage matches the spacing between the
surface mount capacitor terminals.
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. See the section entitled "Isolation Barrier Creepage
Spacing Considerations" on page 3.
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a gui deline
for small form factor applications) from any TNV component, pad or trace to any SELV component,
pad or trace.
TIP
FB1, FB2, R15, R16, and RV1 should be
placed as close as possible to the RJ11.
C8 and C9 should be placed so that there
is a minimal distance between the nodes
where they connect to chassis ground.
RV1
trace from RJ11 to FB1, FB2,
R15, R16, RV1, C8, C9, and F1.
11Use a minimum of 20 mil wide
RING
RV1 should be placed as close as
possible to the RJ11.
9,10
R15
R16
9
Distance from TIP and RING through EMC
capacitors C8 and C9 to chassis ground is short.
The trace from C3 to the D1/D2 node should be short and direct.
C3 should be placed across the diode bridge, and the area
of the loop formed from Si3019 pin 11 through C3 to the
diode bridge and back to Si3019 pin 15 should be minimized.
Use a minimum of 15 mil width traces in DAA section, use a
minimum of 20 mil width traces for IGND.
21
8
7
The area of the loop formed from U2 pin 13 to the base of Q4 a nd from
U2 pin 12 to the emitter of Q4 should be minimize d.
28
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating
spacing as a guideline for small form factor applications) from any TNV
component, pad or trace to any SELV component, pad or trace.
TNV to SELV creepage matches the spacing
between the surface mount capacitor terminals.
16
Si3019
16
QE2 12
IGND
15
DCT3 14
QB 13
DCT2
C7
R2
17 trace from R2 to U2 pin16 should be less than 20 mm.
R2 should be placed next to the base of Q5, and the
use a minimum of 20 mil width traces for IGND.
7 Use a minimum of 15 mil width traces in DAA section,
30
The area underneath the body of U2 should be filled with IGND
trace, and an IGND pad should be placed on the back side directly
underneath the body of the U2 package. Multiple vias should be
used to stitch between the two pads to improve thermal transfer.
Minimize the area of the loop from U2 pin 7
R33 R32
and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
C31
R9
1 U2
The trace from C7 to U2 pin 15
should be short and direct.
DAA Section
2, 22, 29
C50
Vcc
4,13
5
C51
Notes:
A loop is minimized by reducing trace lengths and enclosed
loop area.
To expedite layout reviews, it is suggested that reference
designators for components on the DAA Section match those
of the reference design.
Place R30–R33, and C30–C31 as close as possible to the RNG1 a nd RNG2
pins (pins 8 and 9), ensuring a minimum trace length from the RNG1 or RNG2
pin to the R31 or R33 resistor. In order to space the R31 component further
from the trace from C2 to the C2B pin, it is acceptable to orient it 90 degrees
relative to the RNG1 pin (pin 8).
The traces from the RJ11 through the Ringer Network to U2 pin 8 and pin 9
should be well matched. These traces may be up to 10 cm long.
The area of the loop from C50 to U1 pin 17 and from C51 to
pin 16 back to pin 18 (DGND) should be minimized. The return
traces to U2 pin 18 (DGND) should be on the component side.
3
C1 and C2 should be placed directly between
U1 and U2. Short, direct traces should be used
to connect C1 and C2 to U1 and U2. These
traces should never be longer than two inches
and should be minimized in length. Place C2
such that its accompanying trace to the C2B pin
(pin 6) on the Si3019 is not close to the trace
from R7 to the RNG1 pin on the Si3019 (pin 8).
4
2
3
1
U1 and U2 are placed so that pins 11–20 of U1 are facing pins 1–8 of
U2. C1 and C2 are placed directly between U1 and U2.
1
23
Minimize the area of the loop formed
from U2 pin 4 to R9 to U2 pin 15.
Place C4 close to U2 and connect
18 C4 to U2 using a short, direct trace.
AN67
15
AN67
1.11. Si3052 PCI Layout Check List
Table 2 is a checklist that the designer can use during the layout process to ensure all the recommendations in this
application note have been implemented.
Table 2. Si3052 PCI Layout Check List

16
#
Layout Items
Required
1
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. Keep R12 and R13 close to U1. See the section entitled 1.3."Isolation Barrier Creepage Spacing Considerations" on page 4.
2
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the RNG1 pin on
the Si3018 (pin 8). R12 and R13 should be placed close to U1. R12 and R13 should be
placed close to U1.
3
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In
order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
4
The area of the loop from C50 to U1 pin 43 and from C51/C52 to pin 44 back to DGND
should be minimized. The return traces to U1 DGND should be on the component side.
5
The loop formed by XIN, Y1, and XOUT should be minimized and routed on one layer.
The loop formed by Y1, C40, and C41 should be minimized and routed on one layer.
7
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND.
8
C3 should be placed across the diode bridge, and the area of the loop formed from
Si3018/19 pin 11 through C3 to the diode bridge and back to Si3018/19 pin 15 should be
minimized.
9
FB1, FB2, R15, R16, and RV1 should be placed as close as possible to the RJ11.
10
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
11
Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9.
12
The routing from TIP and RING of the RJ11 to the ferrite beads should be well matched.
13
The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well
matched. These traces may be up to 10 cm long.
14
Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is
short.
15
There should be no digital ground plane in the DAA Section.
16
Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
Rev. 0.5
AN67
Table 2. Si3052 PCI Layout Check List (Continued)

#
Layout Items
Required
17
R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be
less than 20 mm.
18
Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
19
The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the
emitter of Q4 should be minimized.
20
The trace from C7 to U2 pin 15 should be short and direct.
21
The trace from C3 to the D1/D2 node should be short and direct.
22
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to
any SELV component, pad or trace.
23
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
24
Cathode marking for Z1.
25
Pin 1 marking for U1 and U2.
26
Space and mounting holes to accommodate for fire enclosure if necessary.
27
Create a power pad on the back side of the board beneath U1 to increase noise
immunity on the power supply.
28
Place Si3052 VA, VD, and VIO coupling caps close to U1.
29
Make the size of the collector pads for Q3, Q4, and Q5 larger to improve heat dissipation.
31
Solder mask for the exposed paddle on U1 should be as shown in Figure 8 on page 5.
32
Place a power supply pad directly underneath the exposed paddle to create a high-frequency bypass capacitor for U1.
Rev. 0.5
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VIO
AD[17]
AD[16]
C/BE[2]
FRAME\
IRDY\
TRDY\
DEVSEL\
STOP\
PERR\
SERR\
PAR
C/BE[1]
AD[15]
AD[14]
VIO
U1
Rev. 0.5
2
C40
C41
Y1
C50
C51 C52
R13
R12
Vcc
C2
C1
1, 22
4
R9
The area of the loop from C50 to U1
pin 43 and from C51/C52 to pin 44
back to DGND should be minimized.
The return traces to U1 DGND
should be on the component side.
AD[31] 48
47
REQ\ 46
GNT\ 45
CLK 44
VDD 43
VA 42
C1A 41
C2A 40
PME\ 39
PIN_B 38
PIN_A 37
RST\ 36
XIN 35
XOUT 34
VAUX 33
INTA\
23
18
16
4
5
6
7
8
16
15
14
13
12
11
10
9
2,3,13
RNG2
Si3018
VREG2
RNG1
SC
QE2
QB
DCT3
IGND
DCT2
VREG
C2B
C1B
IB
RX
2
DCT
3
QE
1 U2
C3
Q4
Q5
22
14
C9
C8
10
TIP
FB1, FB2, RV1, C8, C9.
Use a minimum of 20 mil
11wide trace from RJ11 to
FB1, FB2, R15, R16, and RV1 should be placed
as close as possible to the RJ11.
C8 and C9 should be placed so that there is a
minimal distance between the nodes where they
connect to chassis ground.
R15
RV1
9
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to any
SELV component, pad or trace.
FB1
21
8
7
Use a minimum of 15 mil width traces in DAA
section, use a minimum of 20 mil width traces for
IGND.
C3 should be placed across the diode bridge, and the area of
the loop formed from Si3018/19 pin 11 through C3 to the
diode bridge and back to Si3018/19 pin 15 should be
minimized.
The trace from C3 to the D1/D2 node should be short and direct.
Distance from TIP and RING
through EMC capacitors C8 and
FB2
R16
RING
C9 to chassis ground is short.
20
The trace from C7 to U2 pin 15
should be short and direct.
minimized.
The area of the loop formed from U2 pin
13 to the base of Q4 and from U2 pin 12
Make the size of the collector pads for Q4
and Q5 larger to improve heat dissipation.
19 to the emitter of Q4 should be
29
R2 should be placed next to the base of Q5, and the
trace from R2 to U2 pin16 should be less than 20 mm.
The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well matched.
These traces may be up to 10 cm long.
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8
and 9), ensuring a minimum trace length from the RNG1 or RNG2 pin to
the R7 or R8 resistor. In order to space the R7 component further from the
trace from C2 to the C2B pin, it is acceptable to orient it 90 degrees relative
to the RNG1 pin (pin 8).
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be used to connect
C1 and C2 to U1 and U2. These traces should never be longer than two inches and should be
minimized in length. Place C2 such that its accompanying trace to the C2B pin (pin 6) on the Si3018 is
not close to the trace from R7 to the RNG1 pin on the Si3018 (pin 8).
R7
R8
C6
R14
C7
R2
17
a minimum of 15 mil width traces in DAA section,
7 Use
use a minimum of 20 mil width traces for IGND.
Figure 24. Si3052 PCI Layout Guidelines
Minimize the area of the loop from U2 pin 7 and pin 10 to
C5 and C6 and from those components to U2 pin 15
(IGND).
C5
C4
DAA Section
Notes:
A loop is minimized by reducing trace lengths and enclosed
loop area.
To expedite layout reviews, it is suggested that reference
designators for components on the DAA Section match those
of the reference design.
C1 and C2 should be placed directly between U1 and U2.
Short, direct traces should be used to connect C1 and C2 to U1
and U2. These traces should never be longer than two inches
and should be minimized in length. Place C2 such that its
accompanying trace to the C2B pin (pin 6) on the Si3018 is not
close to the trace from R7 to the RNG1 pin on the Si3018
(pin 8). R12 and R13 should be placed close to U1.
5
The loop formed by XIN, Y1, and XOUT Si3052
should be minimized and routed on one
layer. The loop formed by Y1, C40, and C41
should be minimized and routed on one
layer.
Place a power supply pad directly underneath
the exposed paddle to create a high-frequency
bypass capacitor for U1.
Solder mask for the exposed paddle
on U1 should be ???
31,32
Minimize the area of the loop formed
from U2 pin 4 to R9 to U2 pin 15.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
IDSEL
C/BE[3]
AD[24]
VIO
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[13]
AD[12]
AD[11]
AD[10]
AD[09]
AD[08]
C/BE[0]
AD[07]
VIO
AD[06]
AD[05]
AD[04]
AD[03]
AD[02]
AD[01]
AD[00]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
18
Place C4 close to U2 and connect
C4 to U2 using a short, direct
trace.
Place U1, U2, C1, and C2 so that the recommended minimum
creepage spacing for the target application is implemented. See the
section entitled "Isolation Barrier Creepage Spacing Considerations" on
page 3.
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating
spacing as a guideline for small form factor applications) from any TNV
component, pad or trace to any SELV component, pad or trace.
AN67
AN67
1.12. Si3054 CNR/ACR/AMR Layout Check List
Table 3 is a checklist that the designer can use during the layout process to ensure all the recommendations in this
application note have been implemented. Additionally, Figure 25 provides an annotated diagram of all of the
relevant layout guidelines for the SI3054 CNR/AMR/ACR applications.
Table 3. Si3054 CNR/ACR/AMR Layout Check List

#
Layout Items
Required
1
U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2 are
placed directly between U1 and U2.
2
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. See the section entitled 1.3."Isolation Barrier Creepage Spacing Considerations" on page 4. R12 and R13 should be close to U1.
3
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the RNG1 pin on
the Si3018 (pin 8).
4
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In
order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
5
The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12 (DGND)
should be minimized. The return traces to U2 pin 12 (DGND) should be on the component side.
6
The loop formed by XIN, Y1, and XOUT should be minimized and routed on one layer.
The loop formed by Y1, C40, and C41 should be minimized and routed on one layer.
7
The digital ground plane is made as small as possible, and the ground plane has
rounded corners.
8
Series resistors on clock signals are placed near source.
9
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND.
10
C3 should be placed across the diode bridge, and the area of the loop formed from
Si3018/19 pin 11 through C3 to the diode bridge and back to Si3018/19 pin 15 should be
minimized.
11
FB1, FB2, and RV1 should be placed as close as possible to the RJ11.
12
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
13
Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9, and F1.
14
The routing from TIP and RING of the RJ11 through F1 to the ferrite beads should be
well matched.
Rev. 0.5
19
AN67
Table 3. Si3054 CNR/ACR/AMR Layout Check List (Continued)

20
#
Layout Items
Required
15
The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well
matched. These traces may be up to 10 cm long.
16
Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is
short.
17
There should be no digital ground plane in the DAA Section.
18
Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
19
R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be
less than 20 mm.
20
Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
21
The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the
emitter of Q4 should be minimized.
22
The trace from C7 to U2 pin 15 should be short and direct.
23
The trace from C3 to the D1/D2 node should be short and direct.
24
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to
any SELV component, pad or trace.
25
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
26
Cathode marking for Z1.
27
Pin 1 marking for U1 and U2.
28
Space and mounting holes to accommodate for fire enclosure if necessary.
Rev. 0.5
C40
Y1
Rev. 0.5
4
5
6
7
8
2
3
1
GPIO_A/
EE_SC/ID0
XOUT GPIO_B/EE_SD
U1
Si3054
RESET
SYNC
SDATA_OUT
SDATA_IN0
VD
C2A
GND
AOUT/
ID1
C1A
VA
BIT_CLK SDATA_IN1
MCLK/XIN
9
16
15
14
13
12
11
10
C51
R13 C2
R12 C1
17
R7
C5
C4
4,14
RNG1
7
VREG
8
C2B
4
IB
5
C1B
6
RX
2
DCT
3
QE
1 U2
Si3018
16
15
14
13
12
11
R8
C6
R14
C7
R2
5,11
R15
RV1
TIP
RING
13
The routing from TIP and RING of the
RJ11 through the ferrite beads should
be well matched.
FB2, and RV1 should be placed as
10 FB1,
close as possible to the RJ11.
a minimum of 20 mil wide trace from
12 Use
RJ11 to FB1, FB2, RV1, C8, C9, and F1.
Provide a minimum of 5 mm creepage (or use the
capacitor terminal plating spacing as a guideline for small
form factor applications) from any TNV component, pad or
trace to any SELV component, pad or trace.
TNV to SELV creepage matches the spacing
between the surface mount capacitor terminals.
C8 and C9 should be placed so that there is a minimal distance
between the nodes where they connect to chassis ground.
The loop formed by XIN, Y1, and XOUT should be minimized
and routed on one layer. The loop formed by Y1, C40, and
C41 should be minimized and routed on one layer.
C9
C8
R16
trace from C3 to the D1/D2
22 The
node should be short and direct.
section, use a minimum of 20 mil width traces for
IGND. IGND must not be implemented as a plane.
C3 should be placed across the diode bridge, and the area of the
loop formed from Si3018/19 pin 11 through C3 to the diode
bridge and back to Si3018/19 pin 15 should be minimized.
8 Use a minimum of 15 mil width traces in DAA
9
FB1
FB2
20
28
pin16 should be less than 20 mm.
Make the size of the collector pads for Q4 and
Q5 larger to improve heat dissipation.
Implement collector pads on the back side of
the board and connect the two with multiple
The area of the loop formed from U2 pin
vias to improve heat transfer.
13 to the base of Q4 and from U2 pin 12
to the emitter of Q4 should be minimized.
Figure 25. Si3054 CNR/ACR/AMR Layout Guidelines
23,29
C3
Q4
Q5
18 of Q5, and the trace from R2 to U2
R2 should be placed next to the base
21The trace from C7 to U2 pin 15 should be short and direct.
Use a minimum of 15 mil width traces in DAA section, use a minimum of
20 mil width traces for IGND. IGND must not be implemented as a plane.
VREG2 10
RNG2 9
SC
QE2
QB
DCT3
IGND
DCT2
8
Place R7 and R8 as close as possible to the RNG1 and
RNG2 pins (pins 8 and 9), ensuring a minimum trace
length from the RNG1 or RNG2 pin to the R7 or R8
resistor. In order to space the R7 component further
from the trace from C2 to the C2B pin, it is acceptable to
orient it 90 degrees relative to the RNG1 pin (pin 8).
The traces from the RJ11 through R7 and R8
to U2 pin 8 and pin 9 should be well matched.
These traces may be up to 10 cm long.
R9
DAA Section
24 Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
19 Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
The area underneath the body of U2 should be filled with IGND trace, and an IGND pad
be placed on the back side directly underneath the body of the U2 package.
30 should
Multiple vias should be used to stitch between the two pads to improve thermal transfer.
C1 and C2 should be placed directly between U1 and U2. Short, direct traces
should be used to connect C1 and C2 to U1 and U2. These traces should
never be longer than two inches and should be minimized in length. Place C2
such that its accompanying trace to the C2B pin (pin 6) on the Si3018 is not
close to the trace from R7 to the RNG1 pin on the Si3018 (pin 8).
Minimize the area of the loop from U2
pin 7 and pin 10 to C5 and C6 and from
those components to U2 pin 15 (IGND).
Notes:
A loop is minimized by reducing trace lengths and enclosed
loop area.
To expedite layout reviews, it is suggested that reference
designators for components on the DAA Section match those
of the reference design.
2, 23, 29
C50
C41
3
Place U1, U2, C1, C2, C8, and C9 so that the recommended
minimum creepage spacing for the target application is implemented.
See the section entitled "Isolation Barrier Creepage Spacing
Considerations" on page 4. R12 and R13 should be close to U1.
Provide a minimum of 5 mm creepage (or use the
capacitor terminal plating spacing as a guideline for small
form factor applications) from any TNV component, pad or
trace to any SELV component, pad or trace.
TNV to SELV creepage matches the spacing
between the surface mount capacitor terminals.
5
The area of the loop from
Vcc
C50 to U1 pin 4 and from
C51 to pin 13 back to pin 12
(DGND) should be minimized.
The return traces to U2 pin
12 (DGND) should be on the
component side.
6
The loop formed by XIN, Y1, and XOUT should
be minimized and routed on one layer. The
loop formed by Y1, C40, and C41 should be
minimized and routed on one layer.
1
U1 and U2 are placed so that pins 9–16 of
U1 are facing pins 1–8 of U2. C1 and C2
are placed directly between U1 and U2.
AN67
21
AN67
1.13. Si3054 MDC/miniPCI Layout Check List
Table 4 is a checklist that the designer can use during the layout process to ensure all the recommendations in this
application note have been implemented.
Table 4. Si3054 MDC/miniPCI Layout Check List

22
#
Layout Items
Required
1
U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2 are
placed directly between U1 and U2. R12 and R13 should be placed close to U1.
2
Place U1, U2, C1, C2, C8, and C9 so that the recommended minimum creepage spacing
for the target application is implemented. See the section entitled 1.3."Isolation Barrier
Creepage Spacing Considerations" on page 4.
3
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the RNG1 pin on
the Si3018 (pin 8).
4
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In
order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
5
The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12 (DGND)
should be minimized. The return traces to U2 pin 12 (DGND) should be on the component side.
6
The loop formed by XIN, Y1, and XOUT should be minimized and routed on one layer.
The loop formed by Y1, C40, and C41 should be minimized and routed on one layer.
7
Series resistors on clock signals are placed near source.
8
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND. IGND must not be implemented as a plane.
9
C3 should be placed across the diode bridge, and the area of the loop formed from
Si3018/19 pin 11 through C3 to the diode bridge and back to Si3018/19 pin 15 should be
minimized.
10
FB1, FB2, and RV1 should be placed as close as possible to the RJ11.
11
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
12
Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9, and F1.
13
The routing from TIP and RING of the RJ11 through the ferrite beads should be well
matched.
14
The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well
matched. These traces may be up to 10 cm long.
15
Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is
short.
Rev. 0.5
AN67
Table 4. Si3054 MDC/miniPCI Layout Check List (Continued)

#
Layout Items
Required
16
There should be no digital ground plane in the DAA Section.
17
Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
18
R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be
less than 20 mm.
19
Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
20
The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the
emitter of Q4 should be minimized.
21
The trace from C7 to U2 pin 15 should be short and direct.
22
The trace from C3 to the D1/D2 node should be short and direct.
23
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to
any SELV component, pad or trace.
24
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
25
Cathode marking for Z1.
26
Pin 1 marking for U1 and U2.
Small Form Factor Specific Guidelines
27
Space U2, Q4, Q5, R1, R3, R4, R10, and R11 far away from each other in the line-side
section of the layout.
28
Make the size of the collector pads for Q4 and Q5 larger to improve heat dissipation.
Implement collector pads on the back side of the board and connect the two with multiple
vias to improve heat transfer.
29
TNV to SELV creepage matches the spacing between the surface mount capacitor terminals.
30
The area underneath the body of U2 should be filled with IGND trace, and an IGND pad
should be placed on the back side directly underneath the body of the U2 package. Multiple vias should be used to stitch between the two pads to improve thermal transfer.
Rev. 0.5
23
24
6
Rev. 0.5
4
5
6
7
8
2
3
1
GPIO_A/
EE_SC/ID0
XOUT GPIO_B/EE_SD
U1
Si3054
RESET
SYNC
SDATA_OUT
SDATA_IN0
VD
C2A
GND
AOUT/
ID1
C1A
VA
BIT_CLK SDATA_IN1
MCLK/XIN
16
15
14
13
12
11
10
9
3
C2
C1
C51
R13
R12
17
4
5
6
7
8
4,14
RNG2
Si3018
VREG2
RNG1
SC
QE2
QB
DCT3
IGND
DCT2
VREG
C2B
C1B
IB
RX
2
DCT
3
QE
1 U2
16
15
14
13
12
11
10
9
R8
C6
C3
TIP
13
The routing from TIP and RING of the
RJ11 through the ferrite beads should
be well matched.
FB2, and RV1 should be placed as
10 FB1,
close as possible to the RJ11.
C8 and C9 should be placed so that there is a minimal distance
between the nodes where they connect to chassis ground.
The loop formed by XIN, Y1, and XOUT should be minimized
and routed on one layer. The loop formed by Y1, C40, and
C41 should be minimized and routed on one layer.
5,11
R15
RV1
RING
Provide a minimum of 5 mm creepage (or use the
capacitor terminal plating spacing as a guideline for small
form factor applications) from any TNV component, pad or
trace to any SELV component, pad or trace.
TNV to SELV creepage matches the spacing
between the surface mount capacitor terminals.
FB1
C9
C8
R16
a minimum of 20 mil wide trace from
12 Use
RJ11 to FB1, FB2, RV1, C8, C9, and F1.
C3 should be placed across the diode bridge, and the area of the
loop formed from Si3018/19 pin 11 through C3 to the diode
bridge and back to Si3018/19 pin 15 should be minimized.
trace from C3 to the D1/D2
22 The
node should be short and direct.
9
8
28
pin16 should be less than 20 mm.
Make the size of the collector pads for Q4 and
Q5 larger to improve heat dissipation.
Implement collector pads on the back side of
the board and connect the two with multiple
The area of the loop formed from U2 pin
vias to improve heat transfer.
13 to the base of Q4 and from U2 pin 12
to the emitter of Q4 should be minimized.
Use a minimum of 15 mil width traces in DAA
section, use a minimum of 20 mil width traces for
IGND. IGND must not be implemented as a plane.
FB2
20
Q5
Q4
23,29
R12
C7
R2
18 of Q5, and the trace from R2 to U2
R2 should be placed next to the base
21The trace from C7 to U2 pin 15 should be short and direct.
Use a minimum of 15 mil width traces in DAA section, use a minimum of
20 mil width traces for IGND. IGND must not be implemented as a plane.
Place R7 and R8 as close as possible to the RNG1 and
RNG2 pins (pins 8 and 9), ensuring a minimum trace
length from the RNG1 or RNG2 pin to the R7 or R8
resistor. In order to space the R7 component further
from the trace from C2 to the C2B pin, it is acceptable to
orient it 90 degrees relative to the RNG1 pin (pin 8).
The traces from the RJ11 through R7 and R8
to U2 pin 8 and pin 9 should be well matched.
These traces may be up to 10 cm long.
R7
C5
C4
8
Figure 26. Si3054 MDC/miniPCI Layout Guidelines
Minimize the area of the loop from U2
pin 7 and pin 10 to C5 and C6 and from
those components to U2 pin 15 (IGND).
R9
DAA Section
24 Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
19 Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
The area underneath the body of U2 should be filled with IGND trace, and an IGND pad
be placed on the back side directly underneath the body of the U2 package.
30 should
Multiple vias should be used to stitch between the two pads to improve thermal transfer.
C1 and C2 should be placed directly between U1 and U2. Short, direct traces
should be used to connect C1 and C2 to U1 and U2. These traces should
never be longer than two inches and should be minimized in length. Place C2
such that its accompanying trace to the C2B pin (pin 6) on the Si3018 is not
close to the trace from R7 to the RNG1 pin on the Si3018 (pin 8).
Place U1, U2, C1, C2, C8, and C9 so that the recommended
minimum creepage spacing for the target application is
implemented. See the section entitled "Isolation Barrier
Creepage Spacing Considerations" on page 3.
Provide a minimum of 5 mm creepage (or use the
capacitor terminal plating spacing as a guideline for small
form factor applications) from any TNV component, pad or
trace to any SELV component, pad or trace.
TNV to SELV creepage matches the spacing
between the surface mount capacitor terminals.
2, 23, 29
C50
C41
Notes:
A loop is minimized by reducing trace lengths and enclosed
loop area.
To expedite layout reviews, it is suggested that reference
designators for components on the DAA Section match those
of the reference design.
5
The area of the loop from
Vcc
C50 to U1 pin 4 and from
C51 to pin 13 back to pin 12
(DGND) should be minimized.
The return traces to U2 pin
12 (DGND) should be on the
component side.
C40
Y1
The loop formed by XIN, Y1, and XOUT should
be minimized and routed on one layer. The
loop formed by Y1, C40, and C41 should be
minimized and routed on one layer.
1
U1 and U2 are placed so that pins 9–16 of
U1 are facing pins 1–8 of U2. C1 and C2
are placed directly between U1 and U2. R12
and R13 should be placed close to U1.
AN67
C1A
C2A
R13
R12
C2
C1
R9
C4
C5
+
R1
1
2
3
4
5
6
7
8
U2
Rev. 0.5
16
15
14
13
12
11
10
9
R7
R8
C6
R2
R14
Q5
R11
Q4
R4
D1
D2
C3
C7
R5
Figure 27. Si3050 Typical Application Schematic
Si3018
QE
DCT2
DCT
IGND
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG VREG2
RNG1 RNG2
R3
R10
No Ground Plane In DAA Section
Z1
Q1
FB1
FB2
Q2
Q3
R6
C10
C8
C9
R15
R16
RV1
TIP
RING
AN67
25
AN67
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3

Corrected C7 capacitor in Figure 23 on page 15.
Revision 0.3 to Revision 0.4

Updated 1.1."Form Factor Overview" on page 1.
Updated 1.2."Placement Guidelines" on page 1.
 Updated 1.6."Si3018 Layout Recommendations" on
page 7.
 Updated 1.10."Si3050 Layout Check List" on page
13,

Revision 0.4 to Revision 0.5

26
Removed references to pending 2005 update of
EN60950.
Rev. 0.5
Smart.
Connected.
Energy-Friendly
Products
Quality
Support and Community
www.silabs.com/products
www.silabs.com/quality
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations
thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
Similar pages