8-bit High Withstand Voltage Microcontroller with Integrated 64K-byte FROM and 2048-byte RAM

Ordering number : ENA1007
LC87F6D64A
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F6D64A is 8-bit microcomputer with the following on-chip functional blocks:
• CPU: operable at a minimum bus cycle time of 100ns
• 64K-byte flash ROM (re-writeable on board/On-chip debugger)
• On-chip RAM: 2048 byte
• VFD automatic display controller/driver
• 16-bit timer/counter (can be divided into two 8-bit timers)
• two 8-bit timer with prescaler
• timer for use as date/time clock
• Day-Minute-Second Counter (DMSC)
• System clock divider function
• Synchronous serial I/O port (with automatic block transmit /receive function)
• Asynchronous/synchronous serial I/O port
• Remote control receive function
• 8-channel×8-bit AD converter
• 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
Flash ROM
• Single 5V power supply, writeable on-board.
• Block erase in 128 byte units
• 65536 × 8 bits
RAM
• 2048 × 9 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.21
30508HKIM 20071127-S00004 No.A1007-1/19
LC87F6D64A
Minimum Bus Cycle Time
• 100ns (10MHz) VDD=3.0 to 5.5V
• 150ns (4MHz) VDD=2.5 to 5.5V
Note: The bus cycle time indicates ROM read time.
Minimum Instruction Cycle Time (tCYC)
• 300ns (10MHz) VDD=3.0 to 5.5V
• 750ns (4MHz) VDD=2.5 to 5.5V
Ports
• Input/output ports
Data direction programmable for each bit individually: 10 (P1n, P7n)
Data direction programmable in nibble units:
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• VFD output ports
Large current outputs for digits:
9 (S0/T0 to S8/T8)
Large current outputs for digits/segments:
7 (S9/T9 to S15/T15)
Digit/segment outputs:
8 (S16 to S23)
Segment outputs:
30 (S24 to S53)
• Oscillator pins:
2 (CF1/XT1, CF2/XT2)
• Reset pin:
1 (RES)
• Power supply:
4 (VSS1, VDD1 to VDD3)
• VFD power supply:
1 (VP)
VFD Automatic Display Controller
• Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output
(pins 9 to 23 can be used for output of digit waveforms).
parallel-drive available for large current VFD.
• 16-step dimmer function available
Timers
• Timer 0: 16-bit timer/counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register
+ 8-bit counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Base Timer
1) The clock signal can be selected from any of the following.
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
• Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
SIO
• SIO 0: 8-bit synchronous serial interface
1) LSB first /MSB first function available
2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3) Consecutive automatic data communication
(1 to 256 bits (communication available for each bit) (stop and reopening available for each byte))
• SIO 1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
No.A1007-2/19
LC87F6D64A
AD Converter: 8 bits × 8 channels
Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN)
• Noise rejection function
(Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
• Supporting reception formats with a guide-pulse of half-clock/clock/none.
• Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
• X’tal HOLD mode release function
Watchdog Timer
• The watching timer period is set using an external RC.
• Watchdog timer can produce interrupt, system reset.
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts: 14 sources, 10 vector interrupts
• Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is refused.
• If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable Level
Interrupt Signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/remote control receiver
4
0001BH
H or L
INT3/Base timer 0/1
5
00023H
H or L
T0H
6
0002BH
H or L
7
00033H
H or L
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC
10
0004BH
H or L
Port0/T4/T5
SIO0
• Priority Level: X>H>L
• For equal priority levels, vector with lowest address takes precedence.
Subroutine Stack Levels: 1024 levels maximum (Stack is located in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• On-chip RC oscillation circuit for system clock use.
• On-chip CF oscillation circuit* for system clock use. (Rf built in)
• On-chip Crystal oscillation circuit* low speed system clock use. (Rf built in)
• Frequency variable RC oscillation circuit (internal) for system clock.
1) Adjustable in ±4% (typ) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
* The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of
commonness.
No.A1007-3/19
LC87F6D64A
System Clock Divider Function
• Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs.
(Using 10MHz main clock)
Standby Function
• HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate
but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
• HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped.
1) The CF, RC, X’tal and frequency variable RC oscillators automatically stop operation.
2) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) a specified level is input to at least one of INT0, INT1, INT2
(3) an interrupt condition arises at port 0
• X’tal HOLD mode.
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base-timer are stopped.
1) The CF, RC, frequency variable RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) Setting at least one of the INT0, INT1 and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QFP80(14×14): Lead-free type
Development Tools
• On-chip debugger: TCB87- type-B + LC87F6D64A
No.A1007-4/19
LC87F6D64A
Package Dimensions
unit : mm (typ)
3255
17.2
0.8
14.0
60
41
40
80
21
14.0
17.2
61
1
0.65
0.25
20
0.15
(2.7)
0.1
3.0max
(0.83)
SANYO : QFP80(14X14)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
Pin Assignment
LC87F6D64A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/INT2/T0IN
P17/INT3/T0IN
RES
VSS1
CF1/XT1
CF2/XT2
VDD1
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P70/INT0/T0LCP/RMIN
P71 INT1/T0HCP
S38
S39
VDD3
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
P10/SO0
P11/SI0/SB0
P12/SCK0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S17
S16
VDD2
VP1
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
Top view
QFP80(14×14) “Lead-free Type”
No.A1007-5/19
LC87F6D64A
System Block Diagram
Interrupt control
IR
CF
X’tal
VMRC
Flash ROM
Clock
generator
Standby control
PLA
PC
RC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Port 1
C register
Timer 0
ADC
ALU
Base timer
Remote control
receiver circuit
VFD Controller
DMSC
PSW
Timer 4
INT0 to 3
Noise Rejection Filter
RAR
Timer 5
RAM
Stack pointer
Watchdog timer
On-chip debugger
No.A1007-6/19
LC87F6D64A
Pin Description
Pin name
I/O
Function
Option
VSS1
-
• Power supply (-)
No
VDD1
VDD2
-
• Power supply (+)
No
-
• VFD Power supply (-)
No
I/O
• 8bit input/output port
Yes
VDD3
VP
PORT0
• Data direction programmable in nibble units
P00 to P07
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• Other functions
P04: clock output (system clock/can selected from sub clock)
On-chip debugger pins: DBGP0 to DBGP2 (P05 to P07)
PORT1
I/O
• 8bit input/output port
Yes
• Data direction programmable for each bit
P10 to P17
• Use of pull-up resistor can be specified for each bit
• Other pin functions
P10: SIO0 data output
P11: SIO0 data input/bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input/bus input/output
P15: SIO1 clock input/output
P16: INT2
P17: INT3/Buzzer output
The following types of interrupt detection are possible:
Rising
Falling
INT2
enable
enable
INT3
enable
enable
PORT7
• 2bit input/output port
P70 to P71
• Data direction can be specified for each bit
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
Falling
• Use of pull-up resistor can be specified for each bit
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/
output for watchdog timer/Remote control receiver input
P71: INT1 input/HOLD release input/Timer 0H capture input
The following types of interrupt detection are possible:
Rising
Falling
INT0
enable
enable
INT1
enable
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
Falling
S0/T0 to S8/T8
O
• Large current output for VFD display controller digit (can be used for segment)
No
S9/T9 to S15/T15
O
• Large current output for VFD display controller segment/digit
No
S16 to S53
O
• Output for VFD display controller segment
No
RES
I
Reset terminal
No
CF1/XT1
I
<ceramic oscillator selected>
No
• Input terminal for ceramic oscillator
< crystal oscillator selected>
• Input for 32.768kHz crystal oscillation
When not in use, connect to VDD1.
CF2/XT2
O
<ceramic oscillator selected>
No
• Output terminal for ceramic oscillator
< crystal oscillator selected>
• Output for 32.768kHz crystal oscillation
When not in use, set to oscillation mode and leave open circuit.
No.A1007-7/19
LC87F6D64A
Port Output Types
Output configuration and pull-up/pull-down resistor options are shown in the following table.
Input/output is possible even when port is set to output mode.
Terminal
Option Selected in
Units of
P00 to P07
Output Format
Pull-up Resistor
Pull-down Resistor
CMOS
Programmable
-
each bit
1
2
Nch-open drain
Programmable
-
each bit
1
CMOS
Programmable
-
2
Nch-open drain
Programmable
-
(Note 1)
P10 to P17
Options
P70
-
None
Nch-open drain
Programmable
-
P71
-
None
CMOS
Programmable
-
S0/T0 to S15/T15
-
None
High voltage Pch-open drain
-
Fixed
S16 to S53
Note 1: Programmable pull-up resisters of Port 0 can be attached in nibble units (P00 to P03, P04 to P07).
* Note: Connect as follows to reduce noise on VDD and increase the back-up time.
VSS1 must be connected together and grounded.
LSI
VDD1
Power
supply
Back-up capacitors
VDD2
VFD
powers
VDD3
VSS1
No.A1007-8/19
LC87F6D64A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Supply voltage
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
CF1/XT1, RES
VI(2)
VP
Output voltage
VO(1)
VDD1=VDD2=VDD3
S0/T0 to S15/T15
S16 to S53
Input/Output
VO(2)
CF2/XT2
VIO(1)
Ports 0, 1, 7
IOPH(1)
Ports 0, 1
voltage
Peak output
current
Average
VDD+0.3
VDD+0.3
VDD-45
VDD+0.3
-0.3
VDD+0.3
-0.3
VDD+0.3
-5
S0/T0 to S15/T15
Current at each pin
-30
IOPH(4)
S16 to S53
Current at each pin
-15
IOMH(1)
Ports 0, 1
• CMOS output selected
-7.5
IOMH(2)
Port 71
Current at each pin
-3
IOMH(3)
S0/T0 to S15/T15
Current at each pin
-15
IOMH(4)
S16 to S53
Current at each pin
-10
Total output
ΣIOAH(1)
Port 0
Total of all pins
-30
current
ΣIOAH(2)
Port 1
Total of all pins
-30
ΣIOAH(3)
Ports 0, 1
Total of all pins
-30
ΣIOAH(4)
Port 71
Total of all pins
-5
ΣIOAH(5)
S0/T0 to S15/T15
Total of all pins
-60
ΣIOAH(6)
S16 to S33
Total of all pins
-60
S0/T0 to S15/T15
Total of all pins
mA
-60
ΣIOAH(8)
S34 to S39
Total of all pins
-60
ΣIOAH(9)
S40 to S47
Total of all pins
-60
ΣIOAH(10)
S48 to S53
Total of all pins
-60
ΣIOAH(11)
S34 to S53
Total of all pins
-60
Peak output
IOPL(1)
Ports 0, 1
Current at each pin
current
IOPL(2)
Port 7
Current at each pin
10
Total output
IPML(1)
Ports 0, 1
Current at each pin
15
current
IOML(2)
Port 7
Current at each pin
7.5
Total output
ΣIOAL(1)
Port 0
Total of all pins
50
current
ΣIOAL(2)
Port 1
Total of all pins
50
ΣIOAL(3)
Port 7
Total of all pins
20
ΣIOAL(4)
Ports 0, 1, 7
Total of all pins
80
Pd max
QFP80(14×14)
Ta=-40 to +85°C
Maximum power
20
mW
dissipation
Operating
Topr
-40
temperature
+85
range
Storage
temperature
V
-10
IOPH(3)
S16 to S33
unit
+6.5
-0.3
Current at each pin
• Current at each pin
max
VDD-45
Port 71
ΣIOAH(7)
Low level output current
typ
-0.3
IOPH(2)
output current
High level output current
• CMOS output selected
• Current at each pin
min
°C
Tstg
-55
+125
range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1007-9/19
LC87F6D64A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD(1)
supply voltage
VDD(2)
VDD1=VDD2=VDD3
0.300μs≤tCYC≤200μs
min
typ
max
unit
3.0
5.5
2.5
5.5
2.0
5.5
-35
VDD
0.735μs≤tCYC≤200μs
range
(Note 2-1)
Hold voltage
VHD
VDD1
RAM and the register data are
kept in HOLD mode.
Pull-down
VP
VP
VIH(1)
Ports 0, 1
supply voltage
Input high
Output disable
voltage
VIH(2)
Port 70
VIH(3)
XT1/CF1, RES
VIL(1)
Ports 0, 1
Output disable
Watchdog timer
Input low
voltage
2.5 to 5.5
0.3VDD
2.5 to 5.5
0.9VDD
VDD
2.5 to 5.5
0.75VDD
VDD
2.5 to 5.5
VSS
2.5 to 5.5
VSS
2.5 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.300
200
2.5 to 5.5
0.735
200
3.0 to 5.5
0.1
10
VDD
+0.7
V
Output disable
Port 71
Port 70
0.1VDD
+0.4
port input/interrupt
VIL(2)
Port 70
Output disable
Watchdog timer
VIL(3)
Operation
XT1/CF1, RES
tCYC
cycle time
External
FEXCF(1)
CF1
• CF2 open circuit
0.8VDD
-1.0
system clock
• system clock divider set to 1/1
frequency
• external clock DUTY=50±5%
2.5 to 5.5
0.1
4
• CF2 open circuit
3.0 to 5.5
0.2
20
2.5 to 5.5
0.2
8
• system clock divider set to 1/2
• external clock DUTY=50±5%
Oscillation
FmCF(1)
CF1, CF2
stabilizing
MHz
• 10MHz ceramic resonator
oscillation
3.0 to 5.5
10
2.5 to 5.5
4
• Refer to figure 1
time period
(Note 2-2)
μs
FmCF(2)
CF1, CF2
• 4MHz ceramic resonator
oscillation
MHz
• Refer to figure 1
FmRC
RC oscillation
FmVMRC
Frequency variable RC oscillation
circuit
FsX’tal
XT1, XT2
2.5 to 5.5
0.3
1.0
2.5 to 5.5
4
2.5 to 5.5
32.768
2.0
32.768kHz crystal resonator
oscillation
kHz
Refer to figure 2
Note 2-1: Re-writeable on board VDD≥4.5V.
Note 2-2: The oscillation constant is shown in table 1 and table 2.
The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time
because of commonness.
No.A1007-10/19
LC87F6D64A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Input high current
IIH(1)
Ports 0, 1, 7
min
typ
max
unit
• Output disable
• Pull-up resister OFF.
• VIN=VDD
2.5 to 5.5
1
(including OFF state leak current
of the output Tr.)
Input low current
IIH(2)
RES
VIN=VDD
2.5 to 5.5
1
IIH(3)
CF1/XT1
VIN=VDD
2.5 to 5.5
1
IIL(1)
Ports 0, 1, 7
• Output disable
μA
• Pull-up resister OFF.
• VIN=VSS
2.5 to 5.5
-1
-1
(including OFF state leak current
of the output Tr.)
IIL(2)
RES
VIN=VSS
2.5 to 5.5
IIL(3)
CF1/XT1
VIN=VSS
2.5 to 5.5
-1
Output high
VOH(1)
Port 0: CMOS
IOH=-1.0mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
output option
IOH=-0.5mA
3.0 to 5.5
VDD-1
IOH=-0.1mA
2.5 to 5.5
VDD-0.5
VOH(3)
Ports 1
VOH(4)
Port 71
IOH=-0.4mA
2.5 to 5.5
VDD-1
VOH(5)
S0/T0 to S15/T15
IOH=-20.0mA
4.5 to 5.5
VDD-1.8
VOH(6)
IOH=-10.0mA
3.0 to 5.5
VDD-1.8
VOH(7)
• IOH=-1.0mA
2.5 to 5.5
VDD-1
IOH=-5.0mA
4.5 to 5.5
VDD-1.8
VOH(9)
IOH=-2.5mA
3.0 to 5.5
VDD-1.8
VOH(10)
• IOH=-1.0mA
2.5 to 5.5
VDD-1
• IOH at any single pin is
not over 1mA.
VOH(8)
S16 to S53
• IOH at any single pin is
V
not over 1mA.
Output low
VOL(1)
voltage
Pull-up resistor
Output off-leak
Ports 0, 1
IOL=10mA
4.5 to 5.5
1.5
VOL(2)
IOL=5mA
3.0 to 5.5
1.5
VOL(3)
IOL=1.6mA
2.5 to 5.5
0.4
2.5 to 5.5
0.4
VOL(4)
Port 7
IOL=1mA
Rpu
Ports 0, 1, 7
VOH=0.9VDD
IOFF(1)
current
S0/T0 to S15/T15,
• Output P-ch Tr. OFF
S16 to S53
• VOUT=VSS
• Output P-ch Tr. OFF
IOFF(2)
Pull-down resistor
Rpd
• S0/T0 to S15/T15
• VOUT=VDD-40V
• Output P-ch Tr. OFF
• S16 to S53
• VOUT=3V
4.5 to 5.5
15
40
70
2.5 to 4.5
25
70
150
2.5 to 5.5
-1
2.5 to 5.5
-30
5.0
60
kΩ
μA
100
200
kΩ
• Vp=-30V
Hysteresis
VHYS(1)
Pin capacitance
• Ports 0, 1, 7
• RES
voltage
CP
All pins
2.5 to 5.5
0.1VDD
V
2.5 to 5.5
10
pF
• f=1MHz
• All other terminals connected
to VSS.
• Ta=25°C
No.A1007-11/19
LC87F6D64A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pin/
Conditions
Remarks
SCK0(P12)
VDD[V]
See Fig. 6.
tSCKH(1)
2.5 to 5.5
pulse width
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.5 to 5.5
pulse width
1/2
• Continuous data
tSCKHA(2)
tSCKH(2)
transmission/reception mode
• CMOS output selected
+2tCYC
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
tSCKHA(1)
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
2.5 to 5.5
0.03
2.5 to 5.5
0.03
• See Fig. 6.
Data hold time
Input clock
Output delay
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.5 to 5.5
• (Note 4-1-3)
tdD0(2)
(1/3)tCYC
+0.05
µs
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
Output clock
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
2.5 to 5.5
1tCYC
+0.05
(Note 4-1-3)
2.5 to 5.5
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1007-12/19
LC87F6D64A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Pin/
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Remarks
SCK1(P15)
Specification
Conditions
VDD[V]
See Fig. 6.
SCK1(P15)
• CMOS output selected
1
2
• See Fig. 6.
tSCKL(4)
2.5 to 5.5
pulse width
High level
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
unit
1
tSCK(4)
Low level
max
tCYC
tSCKH(3)
Frequency
typ
2
2.5 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
Parameter
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
2.5 to 5.5
0.03
2.5 to 5.5
0.03
SIOCLK.
Data hold time
• See Fig. 6.
thDI(2)
Output delay time
tdD0(4)
SO1(P13),
Serial output
SB1(P14)
• Must be specified with
μs
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
(1/3)tCYC
2.5 to 5.5
+0.05
output state change in
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt acceptable
pulse width
tPIL(1)
INT1(P71),
• Events to timer 0, 1 can be input.
min
typ
2.5 to 5.5
1
2.5 to 5.5
2
max
unit
INT2(P16)
tPIH(2)
INT3(P17)
• Interrupt acceptable
tPIL(2)
(Noise rejection ratio
• Events to timer 0 can be input.
set to 1/1.)
tPIH(3)
INT3(P17)
• Interrupt acceptable
tPIL(3)
(Noise rejection ratio
• Events to timer 0 can be input.
tCYC
2.5 to 5.5
64
set to 1/32.)
tPIH(4)
INT3(P17)
• Interrupt acceptable
tPIL(4)
(Noise rejection ratio
• Events to timer 0 can be input.
2.5 to 5.5
256
Reset possible
2.5 to 5.5
200
set to 1/128.)
tPIL(5)
RES
μs
No.A1007-13/19
LC87F6D64A
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07)
tCAD
(Note 6-1)
max
bit
±1.5
AD conversion time=32×tCYC
15.62
97.92
(tCYC=
(tCYC=
0.488μs)
3.06μs)
4.5 to 5.5
(Note 6-2)
23.52
97.92
(tCYC=
(tCYC=
0.735μs)
3.06μs)
18.82
97.92
3.0 to 5.5
AD conversion time=64×tCYC
(ADCR2=1)
4.5 to 5.5
(Note 6-2)
(tCYC=
(tCYC=
0.294μs)
1.53μs)
47.04
97.92
(tCYC=
(tCYC=
0.735μs)
1.53μs)
VSS
VDD
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
unit
8
3.0 to 5.5
(ADCR2=0)
Analog input
typ
3.0 to 5.5
precision
Conversion time
min
1
-1
LSB
μs
V
μA
Note 6-1: Absolute precision not including quantizing error (±1/2 LSB).
Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value to
register.
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Parameter
Symbol
Specification
Pin/
Conditions
Remarks
VDD[V]
• FmCF=10Hz for ceramic resonator
dissipation
VDD1
=VDD2
during basic
=VDD3
• System clock: 10MHz
Current
IDDOP(1)
oscillation
operation
• Internal RC oscillation stopped.
(Note 7-1)
• 1/1 frequency division ratio
IDDOP(2)
• CF1=15MHz for external clock
• System clock: CF1 oscillation
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(3)
• FmCF=4MHz for ceramic resonator
oscillation
min
typ
max
4.5 to 5.5
8.0
24
3.0 to 4.5
6.1
19
4.5 to 5.5
10.5
32
3.0 to 4.5
9.5
28
4.5 to 5.5
3.8
9.5
3.0 to 4.5
3.1
7.8
4.5 to 5.5
0.72
3
2.5 to 4.5
0.53
2
4.5 to 5.5
39
220
2.5 to 4.5
25
150
unit
mA
• System clock: 4MHz
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
• FmCF=0Hz (No oscillation)
• System clock: RC oscillation
• Divider set to 1/2
IDDOP(5)
• FsX’tal=32.768kHz for crystal oscillation
• System clock: 32.768KHz
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
μA
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1007-14/19
LC87F6D64A
Continued from preceding page.
Parameter
Current
Symbol
IDDHALT(1)
Specification
Pin/
Conditions
Remarks
VDD[V]
HALT mode
dissipation
VDD1
=VDD2
HALT mode
=VDD3
oscillation
• FmCF=10MHz for Ceramic resonator
min
typ
max
unit
4.5 to 5.5
3.0
9
3.0 to 4.5
2.1
6.3
4.5 to 5.5
4.2
12.5
3.0 to 4.5
2.5
7.8
4.5 to 5.5
1.4
3.5
2.5 to 4.5
1.0
2.5
4.5 to 5.5
420
1600
2.5 to 4.5
280
1100
4.5 to 5.5
24
80
2.5 to 4.5
14
60
• System clock : 10MHz
(Note 7-1)
• Internal RC oscillation stopped.
• Divider: 1/1
IDDHALT(2)
HALT mode
• CF1=15MHz for external clock
• System clock : CF1 oscillation
• Internal RC oscillation stopped.
• Divider 1/2
IDDHALT(3)
mA
HALT mode
• FmCF=4MHz for Ceramic resonator
oscillation
• System clock : 4MHz
• Internal RC oscillation stopped.
• Divider: 1/1
IDDHALT(4)
HALT mode
• FmCF=0Hz (When oscillation stops.)
• System clock : RC oscillation
• Divider: 1/2
IDDHALT(5)
HALT mode
• FsX’tal=32.768kHz for crystal oscillation
• Internal RC oscillation stopped.
• System clock : 32.768kHz
• Divider: 1/2
Current
IDDHOLD(1)
VDD1
• CF1=VDD or open circuit
dissipation
HOLD mode
Current
μA
HOLD mode
(when using external clock)
IDDHOLD(2)
VDD1
4.5 to 5.5
0.10
20
2.5 to 4.5
0.02
15
4.5 to 5.5
21
65
2.5 to 4.5
11
50
Date/time clock HOLD mode
• CF1=VDD or open circuit
dissipation
Date/time
(when using external clock)
• FsX’tal=32.768kHz for crystal oscillation
clock
HOLD mode
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V
Parameter
On-board writing
Symbol
IDDFW(1)
current
Writing time
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
• The current dissipation of the
microcomputer is excluded.
tFW(1)
tFW(2)
4.5 to 5.5
• Erase time
• Writing time
min
typ
max
unit
5
10
mA
20
30
ms
40
60
μs
4.5 to 5.5
No.A1007-15/19
LC87F6D64A
Characteristics of a Sample Main System Clock Oscillation Circuit
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board Our company has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Circuit Parameters
Frequency
10MHz
4MHz
Manufacturer
Oscillator
C1
C2
Rd1
Operating
Oscillation
Supply
Stabilizing Time
Voltage Range
typ
max
[ms]
[pF]
[pF]
[Ω]
[V]
[ms]
CSTCE10M0G52-R0
10
10
1k
2.8 to 5.5
0.029
Notes
MURATA
CSTLS10M0G53-B0
15
15
1k
3.0 to 5.5
0.028
CSTCR4M00G53-R0
15
15
2.2k
2.3 to 5.5
0.034
CSTLS4M00G53-B0
15
15
2.2k
2.3 to 5.5
0.030
MURATA
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than
minimum operating voltage. (Refer to Figure 4)
Characteristics of a Sample Subsystem Clock Oscillator Circuit
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board Our company has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Circuit Parameters
Frequency
Manufacturer
Oscillator
Operating
Oscillation
Supply Voltage
Stabilizing Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4)
Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the
oscillation pins as possible with the shortest possible pattern length.
CF1
XT1
CF2
Rf1
C1
Rf2
Rd1
C2
XT2
C3
CF
Rd2
C4
X’tal
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1007-16/19
LC87F6D64A
VDD
VDD limit
Power supply
0V
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD release
signal
Witout HOLD
release signal
HOLD reset signal VALID
Internal RC
oscillation
tmsCF
CF1,CF2
tmsX’tal
XT1, XT2
Operating mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A1007-17/19
LC87F6D64A
VDD
Note:
Set CRES, RRES values such that reset time
exceeds 200μs.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transmission
period (only SIO0)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transmission
period (only SIO0)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveform
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1007-18/19
LC87F6D64A
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PS No.A1007-19/19
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