8-bit Microcontroller with 128K-byte Flash ROM and 6144-byte RAM

Ordering number : ENA1380
LC87F5ND0C
CMOS IC
FROM 128K byte, RAM 6144 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F5ND0C is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard rewritable),
6144-byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers),
a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a
base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with automatic
block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex),
four 12-bit PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-source 10vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
• Block-erase in 128 byte units
• 131072 × 8 bits
RAM
• 6144 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
VDD=2.8 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 500ns (2MHz)
VDD=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
10709HKIM 20081126-S00001 No. A1380-1/25
LC87F5ND0C
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
VDD=2.8 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 2-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
16 (PEn, PFn)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
8 (VSS1 to VSS4, VDD1 to VDD4)
Timers
• Timer 0: 16-bit timer/counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
No.A1380-2/25
LC87F5ND0C
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bits in continuous transmission mode)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 15 channels
PWM: Multifrequency 12-bit PWM × 4 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer0/base timer1
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
INT0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 3072 levels maximum (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal)
• CF oscillation circuit
• Crystal oscillation circuit
• Multifrequency RC oscillation circuit (internal)
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
: For system clock
No.A1380-3/25
LC87F5ND0C
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Package Form
• QIP100E (14 × 20) : “Lead-free type”
Development Tools
• Evaluation (EVA) chip
• Emulator
• On-chip-debugger
: LC87EV690
: EVA62S + ECB876600D + SUB875C00 + POD100QFP
ICE-B877300 + SUB875C00 + POD100QFP
: TCB87-TypeB + LC87F5ND0C
Programming Boards
Package
Programming boards
QIP100E (14 × 20)
W87F52256Q
Flash ROM Programmer
Maker
Model
Flash Support Group, Inc.
AF9708/09/09B
(Single)
(including product of Ando Electric Co.,Ltd)
Flash Support Group, Inc.
(including product of Ando Electric Co.,Ltd)
(Gang)
AF9833(Unit)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
Support version(Note)
Device
Revision : After Rev.02.82
LC87F5NC8A
Revision : After Rev.02.29
LC87F5NC8A
Revision : After Rev.01.88
Application Version:
Our company
SKK/SKK Type-B/SKK DBG Type-B
After 1.04
(SANYO FWS)
Chip Data Version:
LC87F5NC8A
After2.10
No.A1380-4/25
LC87F5ND0C
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.A1380-5/25
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
PA3/AN12
PA4/AN13
PA5/AN14
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
Pin Assignment
PB7
P36
P35/URX2
P34/UTX2
P33/URX1
P32/UTX1
P31/PWM5
P30/PWM4
P27/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P25/INT5/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1
P23/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP
P21/INT4/T1IN/T0LCP/T0HCP
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1
P07/T7O
P06/T6O
P05/CKO
P04
P03
P02
P01
P00
VSS2
VDD2
PWM0
PWM1
SI2P3/SCK20
SI2P2/SCK2
LC87F5ND0C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LC87F5ND0C
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SI2P1/SI2/SB2
SI2P0/SO2
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
VDD4
VSS4
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top view
QIP100E(14×20) “Lead-free Type”
No.A1380-6/25
LC87F5ND0C
System Block Diagram
IR
Interrupt control
PLA
Flash ROM
Standby control
RC
X’tal
Clock
generator
CF
PC
MRC
SIO0
Bus Interface
ACC
SIO1
Port 0
B register
SIO2
Port 1
C register
Timer 0
Port 3
Timer 1
Port 7
Timer 4
Port 8
Timer 5
ADC
ALU
PWM0/1
PWM4/5
INT0 to 7
Noise rejection filter
PSW
RAR
RAM
Port 2
Stack Pointer
Base timer
Port A
Watchdog Timer
Timer 6
Port B
On-chip debugger
Timer 7
Port C
UART1
Port E
UART2
Port F
No.A1380-7/25
LC87F5ND0C
Pin Description
Pin Name
I/O
Description
Option
VSS1, VSS2
VSS3, VSS4
-
- Power supply pin
No
VDD1, VDD2
VDD3, VDD4
-
+ Power supply pin
No
• 8-bit I/O port
Yes
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05: System clock output (system clock/subclock selectable)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, Beeper output
Port 2
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Port 3
P30 to P36
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Continued on next page.
No.A1380-8/25
LC87F5ND0C
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer 0H capture input
P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input
P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• AD converter input port: AN8 (P70), AN9 (P71)
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P87
• Other functions
P80 to P87: AD converter input port
Port A
I/O
• 6-bit I/O port
Yes
• I/O specifiable in 1-bit units
PA0 to PA5
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
AD converter input ports: PA3(AN12) to PA5(AN15)
Port B
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistor can be turned on and off in 1-bit units
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
DBGP0 to DBGP2 (PC5 to PC7): On-chip Debugger
Port E
I/O
• 8-bit I/O port
No
• I/O specifiable in 2-bit units
PE0 to PE7
• Pull-up resistor can be turned on and off in 1-bit units
Port F
I/O
• 8-bit I/O port
No
• I/O specifiable in 2-bit units
PF0 to PF7
• Pull-up resistor can be turned on and off in 1-bit units
SIO2 Port
I/O
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
SI2P0 to SI2P3
• Shared functions:
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0, PWM1
I/O
• PWM0, PWM1 output port
No
• General-purpose I/O available
RES
I
XT1
I
Reset pin
No
• Input terminal for 32.768kHz X'tal oscillation
No
• Shared functions:
AN10: AD converter input port
General-purpose input port
XT2
I/O
Must be connected to VDD1 if not to be used.
• Output terminal for 32.768kHz X'tal oscillation
No
• Shared functions:
AN11: AD converter input port
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
CF1
I
Ceramic resonator input pin
No
CF2
O
Ceramic resonator output pin
No
No.A1380-9/25
LC87F5ND0C
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port
Options Selected
in Units of
Option Type
Output Type
P00 to P07
1 bit
1
2
N-channel open drain
No
P10 to P17
1 bit
1
CMOS
Programmable
2
N-channel open drain
Programmable
1
CMOS
Programmable
2
N-channel open drain
Programmable
1 bit
1
CMOS
Programmable
2
N-channel open drain
Programmable
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P87
-
No
N-channel open drain
No
PA0 to PA5
1 bit
1
CMOS
Programmable
2
N-channel open drain
Programmable
1
CMOS
Programmable
2
N-channel open drain
Programmable
1
CMOS
Programmable
2
N-channel open drain
Programmable
Programmable
P20 to P27
P30 to P36
1 bit
PB0 to PB7
1 bit
PC0 to PC7
1 bit
CMOS
Pull-up Resistor
Programmable (Note 1)
PE0 to PE7
-
No
CMOS
PF0 to PF7
-
No
CMOS
Programmable
SI2P0, SI2P2
-
No
CMOS
No
-
No
CMOS (when selected as ordinary port)
No
SI2P3
SI2P1
N-channel open drain (When SIO2 data is selected)
PWM0, PWM1
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
Output for 32.768kHz quartz oscillator
No
N-channel open drain (when in general-purpose No
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
capacitor
Power
Supply
LSI
VDD1
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
No.A1380-10/25
LC87F5ND0C
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
capacitor
LSI
VDD1
Power
Supply
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Maximum Supply
VDD max
VDD1, VDD2,
Input voltage
VI(1)
VDD3, VDD4
XT1, CF1
Input/Output
VIO(1)
Ports 0, 1, 2
voltage
Voltage
VDD1=VDD2=VDD3=VDD4
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 3, 7, 8
-0.3
Ports A, B, C, E, F
VDD+0.3
SI2P0 to SI2P3
PWM0, PWM1,XT2
Peak output
IOPH(1)
current
Ports 0, 1, 2, 3
CMOS output select per 1
Ports A, B, C, E, F
application pin
-10
SI2P0 to SI2P3
IOPH(2)
PWM0, PWM1
Per 1 application pin.
-20
IOPH(3)
P71 to P73
Per 1 application pin.
-5
IOM(1)
Ports 0, 1, 2, 3
CMOS output select per 1
current
Ports A, B, C, E, F
application pin
-7.5
(Note1-1)
SI2P0 to SI2P3
-10
High level output current
Average output
IOM(2)
PWM0, PWM1
Per 1 application pin.
IOM(3)
P71 to P73
Per 1 application pin.
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
PWM0, PWM1
Total of all applicable pins
SI2P0 to SI2P3
ΣIOAH(3)
Port 0
Total of all applicable pins
ΣIOAH(4)
Port 0
Total of all applicable pins
-3
-10
-25
mA
-25
-45
PWM0, PWM1
SI2P0 to SI2P3
ΣIOAH(5)
Ports 2, 3, B
Total of all applicable pins
-25
ΣIOAH(6)
Ports A, C
Total of all applicable pins
-25
ΣIOAH(7)
Ports 2, 3, A, B, C
Total of all applicable pins
-45
ΣIOAH(8)
Port F
Total of all applicable pins
-25
ΣIOAH(9)
Ports 1, E
Total of all applicable pins
-25
ΣIOAH(10)
Ports 1, E, F
Total of all applicable pins
-45
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A1380-11/25
LC87F5ND0C
Continued from preceding page.
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Peak output
IOPL(1)
current
P02 to P07
min
typ
max
unit
Per 1 application pin.
Ports 1, 2, 3
Ports A, B, C, E, F
20
SI2P0 to SI2P3
PWM0, PWM1
Average output
IOPL(2)
P00, P01
Per 1 application pin.
30
IOPL(3)
Ports 7, 8, XT2
Per 1 application pin.
10
IOML(1)
P02 to P07
Per 1 application pin.
current
Ports 1, 2, 3
(Note1-1)
Ports A, B, C, E, F
15
SI2P0 to SI2P3
Low level output current
PWM0, PWM1
IOML(2)
P00, P01
Per 1 application pin.
20
7.5
IOML(3)
Ports 7, 8, XT2
Per 1 application pin.
Total output
ΣIOAL(1)
Port 7, XT2
Total of all applicable pins
15
current
ΣIOAL(2)
Port 8
Total of all applicable pins
15
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
20
ΣIOAL(4)
PWM0, PWM1
Total of all applicable pins
45
SI2P0 to SI2P3
ΣIOAL(5)
Port 0
Total of all applicable pins
ΣIOAL(6)
Port 0
Total of all applicable pins
mA
45
PWM0, PWM1
80
SI2P0 to SI2P3
Maximum power
ΣIOAL(7)
Ports 2, 3, B
Total of all applicable pins
45
ΣIOAL(8)
Ports A, C
Total of all applicable pins
45
ΣIOAL(9)
Ports 2, 3, A, B, C
Total of all applicable pins
80
ΣIOAL(10)
Port F
Total of all applicable pins
45
ΣIOAL(11)
Ports 1, E
Total of all applicable pins
45
ΣIOAL(12)
Ports 1, E, F
Total of all applicable pins
80
Pd max
QIP100E(14×20)
Ta=-40 to +85°C
320
dissipation
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
-40
+85
-55
+125
mW
°C
Note 1-1: Average output current is average of current in 100ms interval.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1380-12/25
LC87F5ND0C
Recommended Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Operating
VDD(1)
supply voltage
VDD1=VDD2
=VDD3=VDD4
(Note2-1)
Memory
VHD
sustaining
min
typ
max
unit
0.245μs≤ tCYC≤200μs
2.8
5.5
0.367μs≤ tCYC≤200μs
2.5
5.5
1.470μs≤ tCYC≤200μs
2.2
5.5
2.0
5.5
0.3VDD
VDD
VDD1=VDD2
RAM and register contents in
=VDD3=VDD4
HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
2.2 to 5.5
P70 port input/
+0.7
interrupt side
VIH(2)
Ports 0, 8
Ports A, B, C, E, F
2.2 to 5.5
PWM0, PWM1
VIH(3)
P70 Watchdog timer
side
VIH(4)
Low level input
VIL(1)
voltage
XT1, XT2, CF1,
RES
0.3VDD
VDD
+0.7
2.2 to 5.5
0.9VDD
2.2 to 5.5
0.75VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
VDD
VDD
Ports 1, 2, 3
SI2P0 to SI2P3
V
0.1VDD
+0.4
P71 to P73
P70 port input/
interrupt
VIL(2)
Ports 0, 8
Ports A, B, C, E, F
PWM0, PWM1
VIL(5)
Port 70 Watchdog
Timer
VIL(6)
Instruction cycle
XT1, XT2, CF1, RES
tCYC
time
(Note2-2)
External system
FEXCF(1)
CF1
clock frequency
• CF2 pin open
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
0.25VDD
2.8 to 5.5
0.245
200
2.5 to 5.5
0.367
200
2.2 to 5.5
1.470
200
2.8 to 5.5
0.1
12
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
2
μs
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
• CF2 pin open
2.8 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
4
division rate=1/2
Oscillation
FmCF(1)
CF1, CF2
2.8 to 5.5
12
2.5 to 5.5
8
See Fig. 1.
2.2 to 5.5
4
FmRC
Internal RC oscillation
2.2 to 5.5
FmMRC
Frequency variable RC
frequency
Range
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note2-3)
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
oscillation source oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation.
See Fig. 2.
0.3
1.0
2.2 to 5.5
16
2.2 to 5.5
32.768
MHz
MHz
2.0
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1380-13/25
LC87F5ND0C
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C
VIN=VDD
(including the off-leak current of the
SI2P0 to SI2P3
RES
min
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
output Tr.)
PWM0, PWM1
IIH(2)
XT1, XT2
Using as an input port
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C, E, F
VIN=VSS
(including the off-leak current of the
current
SI2P0 to SI2P3
RES
2.2 to 5.5
-1
2.2 to 5.5
-1
μA
output Tr.)
PWM0, PWM1
IIL(2)
XT1, XT2
Using as an input port
VIN=VSS
IIL(3)
CF1
VIN=VSS
2.2 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1.0mA
4.5 to 5.5
voltage
VOH(2)
Ports A, B, C, E, F
IOH=-0.4mA
VDD-1
VDD
SI2P0 to SI2P
VOH(3)
VOH(4)
IOH=-0.2mA
Ports 71, 72, 73
VOH(5)
VOH(6)
IOH=-0.4mA
IOH=-0.2mA
PWM0, PWM1
IOH=-10mA
P30, P31(PWM4, 5
VOH(7)
output mode)
VOH(8)
IOH=-1.6mA
IOH=-1.0mA
3.0 to 5.5
-0.4
2.2 to 5.5
VDD
-0.4
3.0 to 5.5
VDD
-0.4
2.2 to 5.5
VDD
-0.4
4.5 to 5.5
VDD
-1.5
3.0 to 5.5
VDD
-0.4
2.2 to 5.5
VDD
-0.4
V
Low level output
VOL(1)
Ports 0, 1, 2, 3
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports A, B, C, E, F
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1.0mA
2.2 to 5.5
0.4
VOL(3)
VOL(4)
SI2P0 to SI2P3
PWM0, PWM1,
IOL=30mA
4.5 to 5.5
1.5
VOL(5)
IOL=5.0mA
3.0 to 5.5
0.4
VOL(6)
IOL=2.5mA
2.2 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
VOL(7)
P00, P01
Ports 7, 8, XT2
VOL(8)
Pull-up resistation
Rpu(1)
Ports 0, 1, 2, 3
Rpu(2)
Port 7
IOL=1.0mA
2.2 to 5.5
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 5.5
15
35
120
kΩ
Ports A, B, C, E, F
Hysteresis voltage
VHYS
0.4
RES
Ports 1, 2, 7
2.2to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
SI2P0 to SI2P3
Pin capacitance
CP
All pins
• For pins other than that under
test: VIN=VSS
• f=1MHz
• Ta=25°C
No.A1380-14/25
LC87F5ND0C
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pins
Conditions
/Remarks
SCK0(P12)
VDD[V]
• See Fig. 6.
max
unit
1
tSCKH(1)
1
pulse width
tSCKHA(1a)
Input clock
typ
2
pulse width
High level
min
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
2.2 to 5.5
4
tCYC
• See Fig. 6.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
6
Serial clock
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected.
4/3
• See Fig. 6.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
Output clock
pulse width
tSCKHA(2a)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
2.2 to 5.5
tSCKH(2)
+2tCYC
• CMOS output selected.
tSCKH(2)
+(10/3)
tCYC
• See Fig. 6.
tSCKHA(2b)
tCYC
• Continuous data
transmission/reception mode
tSCKH(2)
• SIO2 is in use simultaneous.
+2tCYC
• CMOS output selected.
tSCKH(2)
+(16/3)
tCYC
• See Fig. 6.
Serial input
Data setup time
SI0(P11),
SB0(P11)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
Data hold time
thDI(1)
0.03
2.2 to 5.5
0.03
Input clock
Output
tdD0(1)
delay time
SO0(P10),
SB0(P11),
• Continuous data
(1/3)tCYC
transmission/reception mode
+0.05
• (Note 4-1-3)
tdD0(2)
μs
• Synchronous 8-bit mode.
1tCYC
• (Note 4-1-3)
tdD0(3)
Output clock
Serial output
tsDI(1)
• (Note 4-1-3)
+0.05
2.2 to 5.5
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1380-15/25
LC87F5ND0C
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
Tsck(3)
Low level
tSCKL(3)
Specification
Pins/
Conditions
Remarks
SCK1(P15)
VDD[V]
• See Fig. 6.
2.2 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected.
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
Data hold time
thDI(2)
0.03
2.2 to 5.5
0.03
Output delay
Serial output
tsDI(2)
unit
1
2.2 to 5.5
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Parameter
time
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
2.2 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1380-16/25
LC87F5ND0C
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Symbol
tSCK(5)
Specification
Pins/
Conditions
Remarks
SCK2
VDD[V]
• See Fig. 6.
tSCKL(5)
tSCKH(5)
unit
1
pulse width
tSCKHA(5a)
Input clock
max.
1
pulse width
High level
typ
2
(SI2P2)
Low level
min.
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
2.2 to 5.5
4
tCYC
• See Fig. 6.
• (Note 4-3-2)
tSCKHA(5b)
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
7
Serial clock
• See Fig. 6.
• (Note 4-3-2)
Frequency
Low level
tSCK(6)
tSCKL(6)
• CMOS output selected.
(SI2P2),
• See Fig. 6.
4/3
SCK2O
1/2
(SI2P3)
pulse width
High level
SCK2
tSCK
tSCKH(6)
1/2
Output clock
pulse width
tSCKHA(6a)
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
2.2 to 5.5
• CMOS output selected.
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(10/3)tCYC
• See Fig. 6.
tSCKHA(6b)
tCYC
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• CMOS output selected.
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(19/3)tCYC
• See Fig. 6.
Serial input
Data setup time
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
Data hold Time
thDI(3)
0.03
2.2 to 5.5
0.03
Output delay
Serial output
tsDI(3)
time
tdD0(5)
SO2
(SI2P0),
SB2(SI2P1)
μs
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
2.2 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A1380-17/25
LC87F5ND0C
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
min
typ
max
unit
enabled.
INT2(P72)
2.2 to 5.5
INT4(P20 to P23),
1
INT5(P24 to P27),
INT6(P20)
INT7(P24)
tCYC
tPIH(2)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(2)
time constant is 1/1.
• Event inputs for timer 0 are enabled.
tPIH(3)
INT3(P73)(The noise rejection
• Interrupt source flag can be set.
tPIL(3)
clock is selected to 1/32.)
• Event inputs for timer 0 are enabled.
tPIH(4)
INT3(P73)(The noise rejection
• Interrupt source flag can be set.
tPIL(4)
clock is selected to 1/128.)
• Event inputs for timer 0 are enabled.
tPIL(5)
RES
Reset acceptable.
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
μs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P80) to
Absolute
ET
AN7(P87),
(Note 6-1)
Conversion time
AN9(P71),
AD conversion time=32×tCYC
AN10(XT1),
(when ADCR2=0)
max
unit
8
bit
±1.5
3.0 to 5.5
AN8(P70),
11.74
97.92
(tCYC=
(tCYC=
AN11(XT2),
0.367μs)
3.06μs)
AN12(PA3),
23.53
97.92
(tCYC=
(tCYC=
0.735μs)
3.06μs)
15.68
97.92
(Note 6-2)
AN13(PA4),
4.5 to 5.5
3.0 to 5.5
AN14(PA5)
AD conversion time=64×tCYC
(when ADCR2=1)
(Note 6-2)
4.5 to 5.5
3.0 to 5.5
Analog input
typ
3.0 to 5.5
accuracy
TCAD
min
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
(tCYC=
(tCYC=
0.245μs)
1.53μs)
23.49
97.92
(tCYC=
(tCYC=
0.367μs)
1.53μs)
VSS
VDD
1
-1
LSB
μs
V
μA
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A1380-18/25
LC87F5ND0C
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Normal mode
IDDOP(1)
consumption
current
VDD1
=VDD2
=VDD3
=VDD4
(Note 7-1)
min
typ
max
unit
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
10.9
21.5
2.8 to 4.5
6.1
15.8
4.5 to 5.5
8.1
16.5
2.5 to 4.5
4.4
11.5
4.5 to 5.5
3.0
7.8
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(2)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
IDDOP(3)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(4)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
mA
• System clock set to 4MHz side
IDDOP(5)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
1.7
4.5
4.5 to 5.5
1.1
5.0
2.2 to 4.5
0.65
3.5
4.5 to 5.5
1.45
6.0
2.2 to 4.5
0.78
4.8
4.5 to 5.5
45
125
• 1/1 frequency division ratio.
IDDOP(6)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
IDDOP(7)
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
IDDOP(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
IDDOP(9)
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDOP(10)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
μA
• System clock set to 32.768kHz side.
IDDOP(11)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
23
80
4.5 to 5.5
3.6
8.3
2.8 to 5.5
2.1
4.4
• 1/2 frequency division ratio.
HALT mode
IDDHALT(1)
current
VDD1
=VDD2
=VDD3
(Note 7-1)
=VDD4
consumption
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(2)
mA
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
2.7
5.8
2.5 to 4.5
1.4
3.1
mode
IDDHALT(3)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A1380-19/25
LC87F5ND0C
Continued from preceding page.
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
HALT mode
IDDHALT(4)
consumption
current
(Note 7-1)
VDD1
=VDD2
• HALT mode
=VDD3
=VDD4
• FmX’tal=32.768kHz by crystal oscillation
• FmCF=4MHz ceramic oscillation mode
min
typ
max
4.5 to 5.5
1.1
2.6
2.2 to 4.5
0.57
1.5
4.5 to 5.5
0.38
1.0
unit
mode
• System clock set to 4MHz side
IDDHALT(5)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(6)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mA
mode
IDDHALT(7)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
2.2 to 4.5
0.19
0.8
4.5 to 5.5
1.15
4.2
2.2 to 4.5
0.57
3.0
4.5 to 5.5
21
77
2.2 to 4.5
6
70
4.5 to 5.5
0.05
22
2.2 to 4.5
0.02
16
4.5 to 5.5
19
72
2.2 to 4.5
5
58
•1/2 frequency division ratio.
• HALT mode
IDDHALT(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
IDDHALT(9)
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDHALT(10)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
IDDHALT(11)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
μA
• 1/2 frequency division ratio.
HOLD mode
consumption
current
Timer HOLD
IDDHOLD(1)
VDD1
• CF1=VDD or open (External clock mode)
IDDHOLD(2)
IDDHOLD(3)
• Timer HOLD mode
mode
consumption
• HOLD mode
• CF1=VDD or open (External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
IDDHOLD(4)
current
mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
min
typ
max
unit
• Without CPU current
programming
2.7 to 5.5
5
10
mA
current
Programming
tFW(1)
• Erasing
2.7 to 5.5
20
30
ms
time
tFW(2)
• programming
2.7 to 5.5
40
60
μs
No.A1380-20/25
LC87F5ND0C
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Transfer rate
UBR, UBR2
min
typ
max
unit
8192/3
tCYC
UTX1(P32),
RTX1(P33),
2.5 to 5.5
UTX2(P33),
16/3
RTX2(P34)
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Stop bit
Start bit
Start of
transmission
Transmit data (LSB first)
End of
transmission
UBR
UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
UBR2
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1μF.
• Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
No.A1380-21/25
LC87F5ND0C
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
12MHz
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf1
Rd1
Range
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
Open
CSTCE10M0G52-R0
(10)
(10)
CSTLS10M0G53-B0
(15)
CSTCE8M00G52-R0
CSTLS8M00G53-B0
Remarks
typ
max
[V]
[ms]
[ms]
470
2.5 to 5.5
0.03
0.5
Open
680
2.4 to 5.5
0.03
0.5
Internal C1,C2
(15)
Open
680
2.5 to 5.5
0.03
0.5
Internal C1,C2
(10)
(10)
Open
1k
2.3 to 5.5
0.03
0.5
Internal C1,C2
(15)
(15)
Open
1k
2.5 to 5.5
0.03
0.5
Internal C1,C2
CSTCR4M00G53-R0
(15)
(15)
Open
1.5k
2.2 to 5.5
0.03
0.5
Internal C1,C2
CSTLS4M00G53-B0
(15)
(15)
Open
1.5k
2.2 to 5.5
0.03
0.5
Internal C1,C2
Internal C1,C2
10MHz
MURATA
8MHz
4MHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
MC-306
Operating Voltage
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
560k
Range
[V]
2.2 to 5.5
Oscillation
Stabilization Time
typ
max
[s]
[s]
1.5
3.0
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
Rf1
XT1
Rd1
XT2
Rf2
Rd2
C1
CF
C2
C3
C4
X’tal
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1380-22/25
LC87F5ND0C
VDD
VDD limit
Power supply
GND
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Unfixed
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset
Signal absent
HOLD reset signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A1380-23/25
LC87F5ND0C
VDD
RRES
Note:
Select CRES and RRES value to assure that at least 200μs
reset time is generated after the VDD becomes higher than
the minimum operating voltage..
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0,2 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0,2 only)
tSCKLA
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1380-24/25
LC87F5ND0C
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PS No.A1380-25/25
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