8-bit Microcontroller with Integrated 32K-byte Flash ROM and 2048-byte RAM

Ordering
Orderingnumber
number: :ENA1210A
ENA1951
LC87F2932A
CMOS IC
FROM 32K byte, RAM 2048 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F2932A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard
programmable), 2048-byte RAM, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, day and time counter, a high-speed clock counter, a
synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous
SIO interface, a UART interface (full duplex), an 8-bit 13-channel AD converter, two 12-bit PWM channels, a
system clock frequency divider, frequency variable RC oscillation circuit, and a 26-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128-byte units
• Writable in 2-byte units
• 32768 × 8 bits
RAM
• 2048 × 9 bits
Minimum Bus Cycle
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 250ns (4MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.02a
91708HKIM 20080804-S00001 No.A1210-1/29
LC87F2932A
Minimum Instruction Cycle Time
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 750ns (4MHz)
VDD=2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
• Normal withstand voltage input port
• Reset pins
• Power pins
59 (P0n, P1n, P2n, P30 to P33, P70 to P73, P80 to P86,
PBn, PCn, PWM2, PWM3, CF2, XT2)
(Ports P30 to P33 are available in FLGA68K(6.0×6.0) package only.)
2 (CF1, XT1)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture register)
Mode 3: 16-bit counter (with two 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
Day and Time Counter
1) With a base timer, it can be used as 65535days + 23hours + 59minutes + 59seconds counter.
2) Interrupts are programmable in 4 different time schemes (day, hour, minute or second).
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
2) Can generate output real-time
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
No.A1210-2/29
LC87F2932A
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 8 bits × 13 channels
PWM: Multifrequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Outputs clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock of the system clock
2) Outputs clock of the subclock
Interrupts
• 26 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/ BT0/BT1/DHMSC
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
INT0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table
above).
Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
No.A1210-3/29
LC87F2932A
Oscillation Circuits
• RC oscillation circuit (internal):
For system clock
• CF oscillation circuit:
For system clock, with internal Rf
• Crystal oscillation circuit:
For low-speed system clock, with internal Rf
• Frequency variable RC oscillation circuit (internal): For system clock
1) Adjustable in ±4% (typ) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5, INT6, or INT7
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are six ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5, INT6, or INT7
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
(6) Having an interrupt source established in the day and time counter circuit
On-chip Debugger
• Supports software debugging with the IC mounted on the target board (LC87D2932A).
LC87F2932A has an On-chip debugger but its function is limited.
Package Form
• QIP64E (14 × 14):
• TQFP64J (7 × 7):
• FLGA68K (6.0 × 6.0):
• FLGA64 (5.0 × 5.0):
Lead-free type
Lead-free type
Lead-free type
Lead-free type
Development Tools
• On-chip debugger: TCB87- TypeB + LC87D2932A
No.A1210-4/29
LC87F2932A
Programming Boards
Package
Programming boards
QIP64E (14×14)
W87F50256Q
TQFP64J (7×7)
W87F58256TQ7
FLGA68K (6.0×6.0)
W87F58256FL6 * This board is Built To Order. It may take about a month to deliver.
FLGA64 (5.0×5.0)
W87F59256FL5 * This board is Built To Order. It may take about a month to deliver.
Flash ROM Programmer
Maker
Flash Support Group, Inc.
(FSG)
Model
Single Programmer
AF9709/AF9709B/AF9709C
Rev 03.04 or later
LC87F2932A
(Note 2)
LC87F2932A
AF9101/AF9103(Main body)
(FSG)
(FSG models)
In-circuit Programmer
Our company
SIB87(Inter Face Driver)
(Our company model)
(Note 1)
Our company
Device
(Including Ando Electric Co., Ltd. models)
Flash Support Group, Inc.
+
Supported version
AF9708
Single/Gang
SKK/SKK Type B
Programmer
(SANYO FWS)
1.04 or later
In-circuit/Gang
SKK-DBG Type B
Chip Data Version
Programmer
(SANYO FWS)
2.15 or later
Application Version
LC87F2924
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
No.A1210-5/29
LC87F2932A
Package Dimensions
unit : mm (typ)
3159A
33
32
64
17
14.0
49
1
16
0.35
0.8
17.2
48
0.8
17.2
14.0
0.15
0.1
3.0max
(2.7)
(1.0)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3289
9.0
0.5
7.0
33
32
64
17
7.0
49
1
16
0.4
0.16
9.0
48
0.125
0.1
1.2max
(1.0)
(0.5)
SANYO : TQFP64J(7X7)
No.A1210-6/29
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC4
PC3/AN11
PC2/AN10
PC1/AN9
PC0/AN8
P86/AN6
P85/AN5
P84/AN4
P83/AN3
Pin Assignment
PC5/DBGP0
LC87F2932A
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP
49
32
PB2
P71/INT1/T0HCP
50
31
PB3
P72/INT2/T0IN
51
30
PB4
P73/INT3/T0IN
52
29
PB5
RES
53
28
PB6
XT1
54
27
PB7
XT2
55
26
P27/INT5/T1IN/INT7/T0HCP1
VSS1
56
25
P26/INT5/T1IN/INT6/T0LCP1
CF1/AN12
57
24
P25/INT5/T1IN
CF2/AN13
58
23
P24/INT5/T1IN
VDD1
59
22
P23/INT4/T1IN
P80/AN0
60
21
P22/INT4/T1IN
P81/AN1
61
20
P21/URX/INT4/T1IN
LC87F2932A
P06/T6O
9 10 11 12 13 14 15 16
P05/CKO
8
P04
7
P03
6
P02
5
P01
4
P00
3
VSS2
2
VDD2
1
PWM3
17
PWM2
64
P16/T1PWML
P11/SI0/SB0
P17/T1PWMH/BUZ
P07/T7O
P15/SCK1
P20/UTX/INT4/T1IN
18
P14/SI1/SB1
19
63
P13/SO1
62
P12/SCK0
P82/AN2
P10/SO0
Top view
Note: Port P30, p31, p32, p33 are not available in the above package.
QIP64E(14 × 14)
TQFP64J(7 × 7)
“Lead-free Type”
“Lead-free Type”
No.A1210-7/29
LC87F2932A
Package Dimensions
unit : mm (typ)
3326
BOTTOM VIEW
6.0
1 2 3 4 56 7
8 9 10 11
0.5
0.5
0.3
0.5
6.0
(0.45)
TOP VIEW
L K J H G F ED C BA
0.5
0.3
0.4
0.0NOM
SIDE VIEW
0.85MAX
(0.45)
SANYO : FLGA68K(6.0X6.0)
Package Dimensions
unit : mm (typ)
3328
5.0
1 2 34 5
5.0
6 78
0.5
0.75
0.75
H G FE
DC B A
0.5
0.8
0.0NOM
0.3
s
SANYO : FLGA64(5.0X5.0)
No.A1210-8/29
LC87F2932A
Pin Assignments
11
51
49
47
45
43
41
39
37
35
48
46
44
42
40
38
36
33
34
10
52
50
9
54
53
31
32
8
56
55
29
30
7
58
57
27
28
6
60
59
25
26
5
62
61
23
24
4
64
63
21
22
3
66
65
19
20
2
68
67
2
4
6
8
10
12
14
16
18
1
3
5
7
9
11
13
15
17
C
D
E
F
G
H
J
K
1
A
B
LC87F2932A
L
Top view
Pin
Pin Name
No.
Pin
Pin Name
No.
Pin
No.
Pin Name
Pin
Pin Name
No.
1
P12/SCK0
18
P06/T6O
35
PB1
52
P70/INT0/T0LCP
2
P13/SO1
19
P07/T7O
36
PB0
53
P71/INT1/T0HCP
3
P14/SI1/SB1
20
P20/UTX/INT4/T1IN
37
VSS3
54
P72/INT2/T0IN
4
P15/SCK1
21
P21/URX/INT4/T1IN
38
VDD3
55
P73/INT3/T0IN
5
P16/T1PWML
22
P22/INT4/T1IN
39
PC7/DBGP2
56
RES
6
P17/T1PWMH/BUZ
23
P23/INT4/T1IN
40
PC6/DBGP1
57
XT1
7
PWM2
24
P24/INT5/T1IN
41
PC5/DBGP0
58
XT2
8
PWM3
25
P25/INT5/T1IN
42
PC4
59
VSS1
CF1/AN12
9
VDD2
26
P26/INT5/T1IN/INT6/TOLCP1
43
PC3/AN11
60
10
VSS2
27
P27/INT5/T1IN/INT7/T0HCP1
44
PC2/AN10
61
CF2/AN13
11
P00
28
PB7
45
PC1/AN9
62
VDD1
12
P01
29
PB6
46
PC0/AN8
63
P80/AN0
13
P02
30
PB5
47
P86/AN6
64
P81/AN1
14
P03
31
PB4
48
P85/AN5
65
P82/AN2
15
P04
32
PB3
49
P84/AN4
66
P10/SO0
16
P05/CKO
33
PB2
50
P83/AN3
67
P11/SI0/SB0
17
P30
34
P31
51
P32
68
P33
Note: A1, A11, L1, L11 are dummy terminals for the package.
These terminals need to be bonded with foot pattern for the secure bonding of the package.
FLGA68K(6.0 × 6.0) “Lead-free Type”
No.A1210-9/29
LC87F2932A
LC87F2932A
8
47
48
43
41
40
38
33
31
7
49
50
45
42
37
36
34
32
6
54
52
51
44
39
35
29
27
5
56
53
55
46
30
28
26
25
4
57
58
60
62
14
23
21
24
3
59
61
3
7
12
19
20
22
2
64
2
4
5
10
13
18
17
1
63
1
6
8
9
11
16
15
A
B
C
D
E
F
G
H
Top view
Pin
Pin Name
No.
Pin
Pin Name
No.
Pin
No.
Pin Name
Pin
Pin Name
No.
1
P12/SCK0
17
P06/T6O
33
PB1
49
P70/INT0/T0LCP
2
P13/SO1
18
P07/T7O
34
PB0
50
P71/INT1/T0HCP
3
P14/SI1/SB1
19
P20/UTX/INT4/T1IN
35
VSS3
51
P72/INT2/T0IN
4
P15/SCK1
20
P21/URX/INT4/T1IN
36
VDD3
52
P73/INT3/T0IN
5
P16/T1PWML
21
P22/INT4/T1IN
37
PC7/DBGP2
53
RES
6
P17/T1PWMH/BUZ
22
P23/INT4/T1IN
38
PC6/DBGP1
54
XT1
XT2
7
PWM2
23
P24/INT5/T1IN
39
PC5/DBGP0
55
8
PWM3
24
P25/INT5/T1IN
40
PC4
56
VSS1
9
VDD2
25
P26/INT5/T1IN/INT6/T0LCP1
41
PC3/AN11
57
CF1/AN12
10
VSS2
26
P27/INT5/T1IN/INT7/T0HCP1
42
PC2/AN10
58
CF2/AN13
11
P00
27
PB7
43
PC1/AN9
59
VDD1
12
P01
28
PB6
44
PC0/AN8
60
P80/AN0
13
P02
29
PB5
45
P86/AN6
61
P81/AN1
14
P03
30
PB4
46
P85/AN5
62
P82/AN2
15
P04
31
PB3
47
P84/AN4
63
P10/SO0
16
P05/CKO
32
PB2
48
P83/AN3
64
P11/SI0/SB0
Note: Port P30, p31, p32, p33 are not available in the above package.
FLGA64(5.0 × 5.0) “Lead-free Type”
No.A1210-10/29
LC87F2932A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF
VMRC
Clock
generator
RC
Flash ROM
X’tal
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 3
ALU
Timer 5
Port 7
Timer 6
Port 8
PSW
Timer 7
ADC
RAR
Base timer
INT0 to 7
Noise filter
RAM
Port B
Stack pointer
Port C
Watchdog timer
UART1
On-chip debugger
Day and time
counter
PWM2/3
No.A1210-11/29
LC87F2932A
Pin Description
Pin Name
VSS1
VSS2
I/O
-
Description
Option
-power supply pin
No
VSS3
VDD1
VDD2
-
+power supply pin
No
• 8-bit I/O port
Yes
VDD3
Port 0
I/O
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units.
• HOLD reset input
• Port 0 interrupt input
• Shared pins
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
Port 2
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P20: UART transmit
P21: UART receive
P26: INT6 input/HOLD reset input/timer 0L capture 1 input
P27: INT7 input/ HOLD reset input/timer 0H capture 1 input
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
Interrupt acknowledge type
Port 3
P30 to P33
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 4-bit I/O port
Yes
(These ports are available in FLGA68K(6.0×6.0) package only.)
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
Continued on next page.
No.A1210-12/29
LC87F2932A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
High speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input port: AN0 (P80) to AN6 (P86)
PWM2
I/O
PWM3
Port B
• PWM2 and PWM3 output ports
No
• General-purpose I/O available
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistors can be turned on and off in 1 bit units.
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
AD converter input port: AN8 (PC0) to AN11 (PC3)
On-chip debugger pins: DBGP0 to DBGP2 (PC5 to PC7)
RES
Input
XT1
Input
Reset pin
No
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
CF1
Input
• Ceramic resonator input pin
No
• Shared pins
General-purpose input port
AD converter input port: AN12
CF2
I/O
• Ceramic resonator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port: AN13
No.A1210-13/29
LC87F2932A
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “RD87 On-chip
Debugger Installation Manual”
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P27
Open
Output low
P30 to P33
Open
Output low
P70 to P73
Open
Output low
P80 to P86
Open
Output low
PWM2,PWM3
Open
Output low
PB0 to PB7
Open
Output low
PC0 to PC6
Open
Output low
PC7
Pulled low with a 100kΩ resistor or less
Output disable
XT1
Pulled low with a 100kΩ resistor or less
-
XT2
Open
Output low
CF1
Pulled low with a 100kΩ resistor or less
-
CF2
Open
Output low
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
P10 to P17
P20 to P27
Option Selected
in Units of
1 bit
1 bit
1 bit
Option Type
1 bit
Pull-up Resistor
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
Nch-open drain
Programmable
2
P30 to P33
Output Type
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
PWM2, PWM3
-
No
CMOS
No
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
-
No
Input for 32.768kHz crystal oscillator
No
PB0 to PB7
PC0 to PC7
XT1
(Input only)
XT2
-
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose
output mode)
CF1
-
No
Input for ceramic oscillator
No
(Input only)
CF2
-
No
Output for ceramic oscillator
No
(Nch-open drain when in general-purpose
output mode)
No.A1210-14/29
LC87F2932A
User Option Table
Option Name
Option to be Applied on
P00 to P07
P10 to P17
P20 to P27
Flash-ROM
Version



Option Selected in Units of
CMOS
1 bit
Nch-open drain
CMOS
1 bit
Nch-open drain
CMOS
1 bit
Nch-open drain
Port output type
P30 to P33
Program start
address

CMOS
1 bit
PB0 to PB7

1 bit
PC0 to PC7

1 bit
-

-
Option Selection
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
00000h
07E00h
*1: Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
supply
For backup *2
VDD2
VDD3
VSS1
VSS2
VSS3
*2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A1210-15/29
LC87F2932A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Maximum supply
Symbol
VDD max
Pin/Remarks
VDD1, VDD2, VDD3
Conditions
VDD1=VDD2=VDD3
voltage
Input voltage
VI(1)
XT1, CF1
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7, 8
voltage
Specification
VDD[V]
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports B, C
-0.3
PWM2, PWM3, XT2,
VDD+0.3
CF2
Peak output
IOPH(1)
current
High level output current
Mean output
CMOS output select
Per 1 applicable pin
PWM2, PWM3
Per 1 applicable pin
-20
IOPH(3)
P71 to P73
Per 1 applicable pin
-5
IOMH(1)
Ports 0, 1, 2, 3
CMOS output select
Ports B, C
Per 1 applicable pin
IOMH(2)
PWM2, PWM3
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
ΣIOAH(1)
P71 to P73, P32
Total of all applicable pins
current
ΣIOAH(2)
Port 1, P33
Total of all applicable pins
PWM2, PWM3
ΣIOAH(3)
Ports 0, 2, P30
Total of all applicable pins
ΣIOAH(4)
Ports 0, 1, 2, P30,
Total of all applicable pins
PWM2, PWM3, P33
Peak output
-10
IOPH(2)
current
(Note 1-1)
Ports 0, 1, 2, 3
Ports B, C
-7.5
-10
-3
-10
-25
-25
-45
ΣIOAH(5)
Port B, P31
Total of all applicable pins
-25
ΣIOAH(6)
Port C
Total of all applicable pins
-25
ΣIOAH(7)
Ports B, C, P31
Total of all applicable pins
-45
P02 to P07
Per 1 applicable pin
IOPL(1)
current
Ports 1, 2, 3, B, C
20
PWM2, PWM3
Low level output current
Mean output
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
Ports 7, 8, XT2, CF2
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
current
Ports 1, 2, 3, B, C
(Note 1-1)
PWM2, PWM3
15
IOML(2)
P00, P01
Per 1 applicable pin
IOML(3)
Ports 7, 8
Per 1 applicable pin
XT2, CF2
Total output
ΣIOAL(1)
current
Port 7, P32
mA
20
7.5
Total of all applicable pins
15
P83 to P86, XT2,
CF2
ΣIOAL(2)
P80 to P82
Total of all applicable pins
ΣIOAL(3)
Ports 7, 8, P32
Total of all applicable pins
XT2, CF2
ΣIOAL(4)
Port 1, P33
Total of all applicable pins
PWM2, PWM3
ΣIOAL(5)
Ports 0, 2, P30
Total of all applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of all applicable pins
15
20
45
45
80
P30, P33
PWM2, PWM3
ΣIOAL(7)
Port B, P31
Total of all applicable pins
45
ΣIOAL(8)
Port C
Total of all applicable pins
45
ΣIOAL(9)
Ports B, C, P31
Total of all applicable pins
80
Note 1-1: The mean output current is a mean value measured over 100ms.
Continued on next page.
No.A1210-16/29
LC87F2932A
Continued from preceding page.
Parameter
Power dissipation
Symbol
Pin/Remarks
Pd max
QIP64E(14×14)
Conditions
Specification
VDD[V]
min
typ
max
Ta=-40 to +85°C
TQFP64J(7×7)
Operating ambient
133
FLGA68K(6.0×6.0)
96
FLGA64(5.0×5.0)
91
Topr
temperature
Storage ambient
unit
292
-40
+85
-55
+125
mW
°C
Tstg
temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
Symbol
VDD(1)
Pin/Remarks
VDD1=VDD2=VDD3
supply voltage
(Note 2-1)
Memory
VHD
VDD1=VDD2=VDD3
sustaining
Conditions
Specification
VDD[V]
min
typ
max
unit
0.245µs ≤ tCYC ≤ 200µs
3.0
5.5
0.367µs ≤ tCYC ≤ 200µs
2.5
5.5
0.681µs ≤ tCYC ≤ 200µs
2.2
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.2 to 5.5
P70 port input/
0.3VDD
+0.7
VDD
interrupt side
VIH(2)
Ports 0, 3, 8, B, C
PWM2, PWM3
VIH(3)
Port 70 watchdog
timer side
VIH(4)
Low level input
VIL(1)
voltage
XT1, XT2, CF1, CF2,
RES
Ports 1, 2
P71 to P73
P70 port input/
interrupt side
VIL(2)
Ports 0, 3, 8, B, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
Instruction cycle
XT1, XT2, CF1, CF2,
RES
tCYC
time
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
2.2 to 5.5
0.3VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.5 to 5.5
0.367
200
+0.7
VDD
V
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
2.2 to 5.5
0.681
200
• CF2 pin open
3.0 to 5.5
0.1
12
• System clock frequency
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
4
μs
division ratio=1/1
• External system clock duty
=50±5%
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
8
division ratio=1/2
MHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.
No.A1210-17/29
LC87F2932A
Continued from preceding page.
Parameter
Oscillation
Symbol
FmCF(1)
Pin/Remarks
CF1, CF2
frequency
range
Conditions
• 12MHz ceramic oscillation
• See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
• 8MHz ceramic oscillation
• See Fig. 1.
FmCF(3)
CF1, CF2
• 4MHz ceramic oscillation
• See Fig. 1.
FmRC
Internal RC oscillation
FmVMRC(1)
• Frequency variable RC
Specification
VDD[V]
min
typ
max
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
unit
2.0
source oscillation
• When
VMRAJ2 to 0=4,
2.2 to 5.5
10
2.2 to 5.5
4
2.2 to 5.5
32.768
MHz
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
Frequency
OpVMRC(1)
When VMSL4M=0
variable RC
OpVMRC(2)
When VMSL4M=1
oscillation
kHz
2.2 to 5.5
8
10
12
2.2 to 5.5
3.5
4
4.5
2.2 to 5.5
8
24
64
2.2 to 5.5
1
4
8
MHz
usable range
Frequency
VmADJ(1)
oscillation
adjustment
Each step of VMRAJn
(Wide range)
variable RC
VmADJ(2)
%
Each step of VMFAJn
(Small range)
range
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1210-18/29
LC87F2932A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High level input
Symbol
IIH(1)
current
IIH(2)
Low level input
Pin/Remarks
Conditions
Ports 0, 1, 2, 3
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VDD
(Including output Tr's off
PWM2, PWM3
leakage current)
XT1, XT2,
For input port specification
CF1, CF2
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VSS
(Including output Tr's off
current
IIL(2)
PWM2, PWM3
leakage current)
XT1, XT2,
For input port specification
CF1, CF2
VIN=VSS
Specification
VDD[V]
min
typ
1
2.2 to 5.5
1
2.2 to 5.5
15
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-15
IIL(3)
CF1
VIN=VSS
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports B, C
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(8)
IOH=-1mA
2.2 to 5.5
VDD-0.4
VOH(4)
P71 to P73
VOH(5)
VOH(6)
PWM2, PWM3
unit
2.2 to 5.5
High level output
VOH(3)
max
Low level output
VOL(1)
Ports 0, 1, 2, 3
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports B, C
IOL=1.6mA
3.0 to 5.5
0.4
0.4
VOL(3)
Pull-up resistance
Hysteresis voltage
PWM2, PWM3
IOL=1mA
2.2 to 5.5
VOL(4)
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(5)
XT2, CF2
IOL=1mA
2.2 to 5.5
0.4
VOL(6)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(7)
IOL=5mA
3.0 to 5.5
0.4
VOL(8)
IOL=2.5mA
2.2 to 5.5
0.4
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 5.5
18
50
150
Rpu(1)
Ports 0, 1, 2, 3
Rpu(2)
Ports 7, B, C
VHYS
RES
Ports 1, 2, 7
Pin capacitance
CP
All pins
μA
V
kΩ
2.2 to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
For pins other than that under
test:
VIN=VSS
f=1MHz
Ta=25°C
No.A1210-19/29
LC87F2932A
Serial Input/Output Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/Remarks
SCK0(P12)
Conditions
Specification
VDD[V]
See Fig. 6.
tSCKH(1)
pulse width
tSCKHA(1)
2.2 to 5.5
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
tSCKH(2)
transmission/reception mode
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
• See Fig. 6.
Low level
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with
respect to rising edge of
2.2 to 5.5
0.03
2.2 to 5.5
0.03
SIOCLK.
Data hold time
Output clock
Input clock
Output delay
Serial output
max
1
transmission/reception mode
Serial clock
typ
2
pulse width
High level
min
• See Fig. 6.
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
2.2 to 5.5
(1/3)tCYC
+0.05
μs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A1210-20/29
LC87F2932A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
2.2 to 5.5
0.03
2.2 to 5.5
0.03
SIOCLK.
Data hold time
Output delay time
• See Fig. 6.
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
Serial output
unit
1
2.2 to 5.5
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
2.2 to 5.5
pulse width
High level
Specification
VDD[V]
pulse width
Output clock
Serial clock
Parameter
• Must be specified with
μs
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
2.2 to 5.5
(1/3)tCYC
+0.05
output state change in
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1210-21/29
LC87F2932A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
Specification
VDD[V]
min
typ
max
unit
are enabled.
INT3(P73) when
noise filter not used,
2.2 to 5.5
1
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P26),
INT7(P27)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
tPIL(5)
RES
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
enabled.
tPIH(4)
constant is 1/128
2.2 to 5.5
enabled.
tPIH(3)
constant is 1/32
tCYC
enabled.
Resetting is enabled.
μs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
Conditions
(Note 6-1)
AN8(PC0),
Conversion
AN9(PC1),
AD conversion time=32×tCYC
AN10(PC2),
(when ADCR2=0) (Note 6-2)
tCAD
VDD[V]
typ
max
unit
8
3.0 to 5.5
bit
±1.5
15.68
97.92
(tCYC=
(tCYC=
AN11(PC3),
0.49µs)
3.06µs)
AN12(CF1),
21.8
97.92
(tCYC=
(tCYC=
0.681µs)
3.06µs)
18.82
97.92
AN13(CF2)
4.5 to 5.5
3.0 to 5.5
AD conversion time=64×tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
Analog input
min
3.0 to 5.5
accuracy
time
Specification
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
(tCYC=
(tCYC=
0.294µs)
1.53µs)
43.6
97.92
(tCYC=
(tCYC=
0.681µs)
1.53µs)
VSS
VDD
LSB
1
-1
μs
V
μA
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued
to the time the complete digital value corresponding to the analog input value is loaded in the required
register.
No.A1210-22/29
LC87F2932A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal
Symbol
Conditions
• FmCF=12MHz ceramic oscillation mode
mode
VDD1
=VDD2
consumption
=VDD3
• System clock set to 12MHz side
current
IDDOP(1)
Pin/
Remarks
IDDOP(2)
(Note 7-1)
• FsX’tal=32.768kHz crystal oscillation mode
Specification
VDD[V]
min
typ
max
unit
4.5 to 5.5
8.38
20.9
3.0 to 3.6
4.85
11.9
4.5 to 5.5
6.36
15.7
3.0 to 3.6
3.64
9.1
2.5 to 3.0
2.42
7.1
4.5 to 5.5
2.42
6
3.0 to 3.6
1.31
3.3
2.2 to 3.0
0.87
2.5
4.5 to 5.5
0.76
3.1
3.0 to 3.6
0.4
1.7
2.2 to 3.0
0.28
1.35
4.5 to 5.5
8.08
20
3.0 to 3.6
4.75
12
4.5 to 5.5
4.55
11.5
3.0 to 3.6
2.63
6.6
2.2 to 3.0
1.72
5
4.5 to 5.5
35.4
115
3.0 to 3.6
18.2
65
2.2 to 3.0
12.1
46
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=8MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped.
IDDOP(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(6)
• FmCF=4MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(7)
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDOP(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(9)
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(10)
IDDOP(11)
IDDOP(12)
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
mA
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDOP(13)
• System clock set to 10MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDOP(14)
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz with
IDDOP(16)
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDOP(17)
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
IDDOP(19)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
μA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1210-23/29
LC87F2932A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(1)
Pin/
Conditions
Remarks
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• FmCF=12MHz ceramic oscillation mode
Specification
VDD[V]
min
typ
max
unit
4.5 to 5.5
3.71
8.2
3.0 to 3.6
2.06
4.6
4.5 to 5.5
2.68
5.9
3.0 to 3.6
1.44
3.3
2.5 to 3.0
1.03
2.5
4.5 to 5.5
1.18
2.65
3.0 to 3.6
0.62
1.5
2.2 to 3.0
0.41
1.1
• System clock set to 12MHz side
IDDHALT(2)
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped.
IDDHALT(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(6)
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(7)
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDHALT(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(9)
• HALT mode
4.5 to 5.5
0.38
1.3
3.0 to 3.6
0.21
0.75
2.2 to 3.0
0.13
0.54
4.5 to 5.5
3.71
8.2
3.0 to 3.6
2.06
4.6
4.5 to 5.5
1.75
4
3.0 to 3.6
1.03
2.5
2.2 to 3.0
0.72
1.8
4.5 to 5.5
19.1
68
3.0 to 3.6
10.3
38
2.2 to 3.0
6.7
26
• HOLD mode
4.5 to 5.5
0.1
20
• CF1=VDD or open (External clock mode)
3.0 to 3.6
0.06
12
2.2 to 3.0
0.04
8
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(10)
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
IDDHALT(11)
• 1/2 frequency division ratio
IDDHALT(12)
mA
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDHALT(13)
• System clock set to 10MHz with frequency
variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(14)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz with frequency
IDDHALT(16)
variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(17)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
IDDHALT(19)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
VDD1
IDDHOLD(3)
Timer HOLD
IDDHOLD(4)
• Timer HOLD mode
4.5 to 5.5
16.5
58
mode
IDDHOLD(5)
• CF1=VDD or open (External clock mode)
3.0 to 3.6
8.8
32
2.2 to 3.0
5.2
20
consumption
current
IDDHOLD(6)
• FsX’tal=32.768kHz crystal oscillation mode
μA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A1210-24/29
LC87F2932A
F-ROM Programming Characteristics at Ta = -10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Onboard
IDDFW(1)
Pin/Remarks
VDD1
Conditions
Specification
VDD[V]
min
typ
max
unit
• Without CPU current
programming
3.0 to 5.5
5
10
mA
20
30
ms
40
60
μs
current
Programming
tFW(1)
• Erasing
time
tFW(2)
• Programming
3.0 to 5.5
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Transfer rate
UBR
Pin/Remarks
Conditions
UTX(P20),
2.2 to 5.5
URX(P21)
Data length:
Stop bits:
Parity bits:
Specification
VDD[V]
min
typ
16/3
max
unit
8192/3
tCYC
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
No.A1210-25/29
LC87F2932A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
12MHz
MURATA
8MHz
MURATA
4MHz
MURATA
Circuit Constant
Oscillator Name
Operating
C1
C2
Rf1
Rd1
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
Open
680
CSTCE8M00G52-R0
(10)
(10)
Open
CSTLS8M00G53-B0
(15)
(15)
CSTCR4M00G53-R0
(15)
CSTLS4M00G53-B0
(15)
Voltage Range
Oscillation
Stabilization Time
Remarks
typ
max
[ms]
[ms]
3.0 to 5.5
0.05
0.15
1k
2.5 to 5.5
0.13
0.4
Internal
Open
1k
2.5 to 5.5
0.12
0.4
C1, C2
(15)
Open
2.2k
2.2 to 5.5
0.07
0.2
Internal
(15)
Open
2.2k
2.2 to 5.5
0.05
0.15
C1, C2
[V]
Internal
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
Circuit Constant
Vendor Name
Oscillator Name
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
560k
2.2 to.5.5
1.3
3.0
Remarks
Applicable
EPSON
32.768kHz
Operating
MC-306
TOYOCOM
CL value=
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
Rf1
Rf2
Rd1
C1
C2
XT2
C3
Rd2
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1210-26/29
LC87F2932A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A1210-27/29
LC87F2932A
VDD
RRES
Note:
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1210-28/29
LC87F2932A
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A1210-29/29
Similar pages