7-Channel x 17-Channel LED Driver for Cell Phones

Ordering number : ENA1359A
LV5230LG
Bi-CMOS IC
7ch×17ch LED Driver
http://onsemi.com
Overview
The LV5230LG is a dot-matrix LED driver IC for cell phones.
Features
• 7×17 dot-matrix LED driver
(5×15 dot-matrix supported)
• Each dot can be set for display over the serial bus.
Functions
• LED driver
Column (anode) driving P-channel driver × 17 channels
Row (cathode ) driving N-channel driver × 7 channels
LED current per dot : 25mA maximum
Two flames of 7×17 (5×15) patterns can be set.
7 grayscale level adjustment on a dot basis (PWM duty factor switching)
Reverse display
Horizontal scroll (1 frame/2 frames)
Continuous/single scroll selectable
Vertical scroll (1 frame/2 frames)
Continuous/single scroll selectable
Automatic flashing can be specified per each dot
Interupt output at the end of scroll
Ring tone synchronization function
• LED driving open drain output × 2
Semiconductor Components Industries, LLC, 2013
August, 2013
O0610 SY/10709 MS PC 20081114-S00001 No.A1359-1/27
LV5230LG
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCC max1
SVCC, VDD
5.5
VCC max2
LEDVDD
V
6
V
Allowable power dissipation
Pd max
Mounted on a board *
1.2
W
Operating temperature
Topr
-30 to +85
°C
Storage temperature
Tstg
-40 to +125
°C
∗ Designated board : 40mm×50mm×0.8mm, glass epoxy 4-layter board (2S2P)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage 1
VBAT
SVCC
Supply voltage 2
VDD
Supply voltage 3
VLEDVDD
Ratings
Unit
3 to 4.5
V
VDD
1.65 to 3
V
LEDVDD
2.7 to 5.5
V
* Power application sequence : 1. VBAT 2. VDD VBAT > VDD, No restriction on VLEDVDD.
* Same level of voltage LEDVCC must be applied to the 4 pins as VLEDVDD voltage.
Electrical Characteristics, Analog Block Ta = 25°C, VBAT = 3.7V, VDD = 2.6V, LEDVDD = 3.7V,
unless otherwise specified
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Consumption current (SVCC+VDD+LEDVDD)
μA
Consumption current 1
ICC1
RESET : L
0
5
Consumption current 2
ICC2
RESET : H, serial default
0.3
5
μA
Consumption current 3A
ICC3A
When STBY mode is released, RT external
1.9
3
mA
Consumption current 3B
ICC3B
1
2
mA
resistance value is 27kΩ
When STBY mode is released, RT external
resistance value is 160kΩ
LEDSW
On resistance 1
Ron1
ROW1 to 7 : IL = 425mA
1
2
Ω
On resistance 2
Ron2
LEDO1, LED02 : IL = 20mA
2
4
Ω
LED current 1
ILED1
COL1 to COL17 : VO = LEDVDD-0.5V
RT external resistance value : 27kΩ
20
22.5
25
mA
LED current 2
ILED2
COL1 to COL17 : VO = LEDVDD-0.5V
RT external resistance value : 160kΩ
2.8
3.8
4.8
mA
Leakage current 1
IL1
ROW1 to ROW : VO = 5V
1
μA
Leakage current 2
IL2
COL1 to COL17 : VO = 0V, LEDVDD = 5V
1
μA
Leakage current 3
IL3
LEDO1, LED02 : VO = 5V
1
μA
OSC
Oscillator frequency
F1
When RT external resistance is 27kΩ,
900
1000
1100
kHz
900
1000
1100
kHz
20
22.5
25
mA
CT external capacitance is 120pF
Oscillator frequency
F1
When RT external resistance is 160kΩ,
CT external capacitance is 10pF
RT
Maximum. LED drive
current setting
LI1
RT external resistance : 27kΩ
LED maximum drive current = 607.5/RT resistance
Continued on next page.
No.A1359-2/27
LV5230LG
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
Control Circuit Block
H level 1
VINH1
VDD×0.8
Input H level, SDA, SCL
L level 1
VINL1
Input L level, SDA, SCL
H level 2
VINH2
Input H level, RESET, SCTL
1.5
L level 2
VINL2
Input L level, RESET, SCTL
0
H input current 3
IHIN3
Inflow-outflow current, when VBAT voltage is
L input current 3
ILIN3
V
VDD×0.2
0
V
V
0.3
V
-1
0
1
μA
-1
0
1
μA
15
47
75
μA
-1
0
1
μA
applied to RESET pin.
Inflow-outflow current, when 0V is applied to
RESET pin.
H input current 4
IHIN4
Inflow-outflow current, when VBAT voltage is
applied to SCTL pin.
L input current 4
ILIN4
Inflow-outflow current, when 0V is applied to SCTL
pin.
H output level 1
VH1
INTO pin, H level, IO = 1mA
VDD-0.3
VDD
V
L output level 1
VL1
INTO pin, L level, IO = 1mA
0
0.3
V
Package Dimensions
unit : mm (typ)
3359
Pd max – Ta
0.45
0.55
5.0
0.55
1
2
3 4
0.65
5.0
5 6 7
0.45
Allowable power dissipation, Pd max – W
1.4
G F E D
C B A
0.65
0.8
0.0 NOM
0.35
Specified board : 50 × 40 × 0.8mm3
4-layer glass epoxy (2S2P) board
1.2
1.0
0.8
0.6
0.48
0.4
0.2
0
– 30 – 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : FLGA49J(5.0X5.0)
Pin Assignment
1
G
F
E
NC
COL16
CT
D
LEDVDD COL17
SVCC
SDA
3
COL15 COL14 COL13
SCL
4
LEDVDD COL12 COL11 RESET
5
COL10
COL9
COL4
COL2
6
LEDVDD COL8
COL5
COL3
NC
COL7
G
F
B
SGND LEDGND ROW2
1
2
7
C
ROW1 ROW3
D
TEST
1
RT
2
VDD
LEDGND ROW4
2
3
INTO
ROW5
LEDGND
3
4
ROW6 LEDGND
4
5
LEDO2 LEDO1 ROW7
6
GPI
LEDGND
COL6 LEDVDD COL1
5
E
Top view
A
C
B
NC
7
A
No.A1359-3/27
COL17
COL16
COL15
COL14
COL13
COL12
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
LEDGND4
OSC
LEDGND3
LEDGND2
LEDGND1
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
VDD
SCL
SDA
INTO
GPI (SCTL)
LEDO2
LEDO1
TEST
LEDGND5
RESET
RT
CT
SVCC
SGND
NC
NC
NC
LV5230LG
Block Diagram
VBAT
IREF
I/F level shift
I2C bus
control
PWM
COUNTER
shift register
LEDVDD
No.A1359-4/27
LV5230LG
COL13
COL14
COL15
COL13
COL14
COL15
COL17
COL12
COL12
COL16
COL11
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
Dot Matrix LED 7 × 17
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
2ms
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
Dynamic Display
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
Dot Matrix LED 5 × 15
ROW1
ROW2
ROW3
ROW4
ROW5
2ms
ROW1
ROW2
ROW3
ROW4
ROW5
Dynamic Display
No.A1359-5/27
LV5230LG
Pin Functions
Pin No.
A1
Pin name
TEST
Pin Description
Equivalent Circuit
Test signal input pin.
Be sure to connect the pin to GND.
SVCC
A1 pin
A2
RT
Reference current setting resistor connection pin.
SVCC
By connecting the external resistor between this pin and GND, the
reference current is generated. The pin voltage is about 0.61V. Change
of this current value enables change of the oscillation frequency and
A2 pin
LED driver current value (COL1 to COL17 only).
A3
ROW4
N-channel driver output pins 1 to 7 for row (cathode) drive.
A6
ROW7
Must be connected to GND when not to be used.
B1
ROW2
B2
ROW3
B4
ROW5
B5
ROW6
C2
ROW1
A4
LEDGND3
ROW SW GND.
A5
LEDGND4
ROW SW GND.
A7
NC
No connection.
B3
LEDGND2
ROW SW GND.
B6
LEDO1
Open drain output pins for LED drive.
C6
LEDO2
Must be connected to GND when not to be used.
A3, A6, B1, B2,
B4, B5, C2 pin
G1
G7
B7
LEDGND5
GND pin dedicated for LEDO1 and LEDO2.
C1
LEDGND1
ROW SW GND.
C3
VDD
Power supply for serial I/F.
C4
INTO
Interrupt signal output pin.
B6, C6 pin
VDD
SVCC
C4 pin
Continued on next page.
No.A1359-6/27
LV5230LG
Continued from preceding page.
Pin No.
C5
Pin name
GPI
Pin Description
Ringing tone synchronization signal input pin.
Must be connected to GND when not to be used.
Equivalent Circuit
SVBAT
C5 pin
C7
COL1
P-channel driver output pins 1 to 17 for column (anode) drive.
D5
COL2
Must be connected to GND when not to be used.
D6
COL3
E3
COL13
E4
COL11
E5
COL4
E6
COL5
E7
COL6
F1
COL16
F2
COL17
F3
COL14
F4
COL12
F5
COL9
F6
COL8
F7
COL7
G3
COL15
G5
COL10
D7
LEDVDD
Dot matrix LED drive voltage supply pins.
D1
SGND
Analog circuit GND pin.
D2
SDA
Serial data signal input pin.
LEDVDD
C7, D5, D6,
E3, E4, E5,
E6, E7, F1,
F2, F3, F4,
F5, F6, F7,
G3, G5 pin
G2
G4
G6
VDD
D2 pin
D3
SCL
Serial clock signal input pin.
VDD
D3 pin
Continued on next page.
No.A1359-7/27
LV5230LG
Continued from preceding page.
Pin No.
D4
Pin name
RESET
Pin Description
Equivalent Circuit
Reset signal input pin.
Reset state when low.
SVCC
D4 pin
E1
CT
Oscillator frequency setting capacitor connection pin.
The oscillation frequency can be adjusted by changing the value of
SVCC
capacitor at CT pin.
E1 pin
E2
SVCC
Analog circuit power supply.
No.A1359-8/27
LV5230LG
Serial Bus Communication Specifications
I2C serial transfer timing conditions
twH
SCL
th1
twL
th2
tbuf
SDA
th1
ts2
ts1
ts3
Resend start condition
Start condition
ton
Stop condition
tof
Input waveform condition
Standard mode
Parameter
symbol
Conditions
min
ts1
SCL setup time relative to the fall of SDA
4.7
ts2
SDA setup time relative to the rise of SCL
250
ns
ts3
SCL setup time relative to the rise of SDA
4.0
μs
th1
SCL data hold time relative to the fall of SDA
4.0
μs
th2
SDA hold time relative to the fall of SCL
twL
Input waveform conditions
Bus free time
100
unit
Data set up time
Pulse width
0
max
fscl
Data hold time
SCL clock frequency
typ
SCL clock frequency
kHz
μs
0
μs
SCL pulse width for the L period
4.7
μs
twH
SCL pulse width for the H period
4.0
ton
SCL and SDA (input) rise time
1000
ns
tof
SCL and SDA (input) fall time
300
ns
tbuf
Time between STOP and START conditions
μs
μs
4.7
High-speed mode
Parameter
Symbol
Conditions
typ
ts1
SCL setup time relative to the fall of SDA
0.6
ts2
SDA setup time relative to the rise of SCL
100
ns
ts3
SCL setup time relative to the rise of SDA
0.6
μs
th1
SCL data hold time relative to the fall of SDA
0.6
μs
th2
SDA hold time relative to the fall of SCL
twL
Input waveform conditions
Bus free time
400
unit
Data setup time
Pulse width
0
max
fscl
Data hold time
SCL clock frequency
min
SCL clock frequency
kHz
μs
0
μs
SCL pulse width for the L period
1.3
μs
twH
SCL pulse width for the H period
0.6
ton
SCL and SDA (input) rise time
300
tof
SCL and SDA (input) fall time
300
tbuf
Time between STOP and START conditions
1.3
μs
ns
ns
μs
No.A1359-9/27
LV5230LG
I2C bus transmission method
Start and stop conditions
In the I2C bus, SDA must basically be kept in the constant state while SCL is “H” as shown below during data
transfer.
SCL
SDA
ts2
th2
When data transfer is not made, both SCL and SDA are in the “H” state.
When SCL = SDA = “H”, change of SDA from “H” to “L” enables the start conditions to start access.
When SCL is “H”, change of SDA from “L” to “H” enables the stop conditions to stop access.
Start condition
Stop condition
th1
ts3
SCL
SDA
No.A1359-10/27
LV5230LG
Data transfer and acknowledgement response
After establishment of start conditions, data transfer is made by one byte (8 bits).
Data transfer enables continuous transfer of any number of bytes.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side.
The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set “L” immediately
after fall of the clock pulse at the SCL eighth bit of data transfer to “L”.
When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side,
the receive side releases SDA at fall of the SCL ninth clock.
In the I2C bus, there is no CE signal. Instead, 7-bit slave address is assigned to each device and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction.
The 7-bit address is transferred sequentially from MSB and if the eighth bit is “L”, the second byte is WRITE mode
and if “H”, the second byte is READ mode.
In the READ mode, the ACK signal issued immediately before sending the stop condition must be 1.
In LV5230, the slave address is specified as (1110111).
Write mode
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Register address
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
Stop
A
C
K
Stop
SCL
SDA
1 1 1
0 1 1
1
0 0 0
Slave address
L
S
B
W
1
1
0 0 0
1 0
0 0 0
1 0 0
0 1
Read mode
Start
M
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
M
S
B
Data
L
S
B
SCL
SDA
1 1 1
0 1 1
STATUS
0
STATUS
1
No.A1359-11/27
LV5230LG
Serial modes setting
address : 00h CTRL1
00h CTRL1
D7
D6
D5
D4
D3
D2
D1
D0
Register name
STBY
-
MXMODE
MSWEN
-
DFCLR
FADECLR
SCRLCLR
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D0 : SCRLCLR Scroll interrupt signal clear
0 : Scroll interrupt signal stays active.
1 : Scroll interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D1 : FADECLR Fade interrupt signal clear
0 : Fade interrupt signal stays active.
1 : Fade interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D2 : DFCLR Pallete fade interrupt signal clear
0 : Pallete fade interrupt signal stays active.
1 : Pallete fade interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D4 : MSWEN Ringing tone synchronization enable
0 : Ringing tone synchronization enabled. * GPI = L : All LEDs turned off, GPI = H : Normal operation
1 : Ringing tone synchronization disabled.
D5 : MXMODE LED matrix mode switchingr
0 : 7 × 17 LED matrix
1 : 5 × 15 LED matrix
D7: STBY Standby mode
0 : Standby
1 : Operation
No.A1359-12/27
LV5230LG
address : 01h CTRL2
01h CTRL2
D7
D6
D5
D4
D3
D2
D1
D0
Register name
LEDOFF
-
LED2
LED1
-
ROTHEN
ROTVEN
PAGE
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D0 : PAGE Display page
0 : Frame 1 displayed
1 : Frame 2 displayed
D1 : ROTVEN Vertical rotation
0 : Normal display
1 : Vertically rotated display
D2 : ROTHEN Horizontal rotation
0 : Normal display
1 : Horizontally rotated display
D4 : LED1 LED1 enable
0 : LED1 turned off
1 : LED1 turned on
D5 : LED2 LED2 enable
0 : LED2 turned off
1 : LED2 turned on
D7 : LEDOFF Screen display ON/OFF
0 : Normal operation
1 : All matrix LEDs turned off
No.A1359-13/27
LV5230LG
address : 02h DOTMODE
02h DOTMODE
D7
D6
D5
D4
D3
D2
D1
D0
Register name
DOTEN
DOTMODE
-
-
DOTSP [3]
DOTSP [2]
DOTSP [1]
DOTSP [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D3-D0 : DOTSP Flashing/brightness inversion speed
D3
D2
D1
D0
0
0
0
0
ON : 0.05s
OFF : 0.05s
0
0
0
1
ON : 0.10s
OFF : 0.10s
0
0
1
0
ON : 0.15s
OFF : 0.15s
0
0
1
1
ON : 0.20s
OFF : 0.20s
0
1
0
0
ON : 0.25s
OFF : 0.25s
0
1
0
1
ON : 0.30s
OFF : 0.30s
0
1
1
0
ON : 0.35s
OFF : 0.35s
0
1
1
1
ON : 0.40s
OFF : 0.40s
1
0
0
0
ON : 0.45s
OFF : 0.45s
1
0
0
1
ON : 0.50s
OFF : 0.50s
1
0
1
0
ON : 0.55s
OFF : 0.55s
1
0
1
1
ON : 0.60s
OFF : 0.60s
1
1
0
0
ON : 0.65s
OFF : 0.65s
1
1
0
1
ON : 0.70s
OFF : 0.70s
1
1
1
0
ON : 0.75s
OFF : 0.75s
1
1
1
1
ON : 0.80s
OFF : 0.80s
D6 : DOTMODE Flashing/brightness inversion display switching
0 : Flashing
1 : Brightness inversion
D7 : DOTEN Flashing/brightness inversion display enable
0 : Disable
1 : Enable
No.A1359-14/27
LV5230LG
address : 03h AUTOPAGE
03h AUTOPAGE
D7
D6
D5
D4
D3
D2
D1
D0
Register name
PGEN
-
-
-
PGSP [3]
PGSP [2]
PGSP [1]
PGSP [0]
R/W
W
W
W
W
W
Default
0
0
0
0
0
D3 top D0 : PGSP Page switching speed
D3
D2
D1
D0
0
0
0
0
Page1 : 0.05s
Page2 : 0.05s
0
0
0
1
Page1 : 0.10s
Page2 : 0.10s
0
0
1
0
Page1 : 0.15s
Page2 : 0.15s
0
0
1
1
Page1 : 0.20s
Page2 : 0.20s
0
1
0
0
Page1 : 0.25s
Page2 : 0.25s
0
1
0
1
Page1 : 0.30s
Page2 : 0.30s
0
1
1
0
Page1 : 0.35s
Page2 : 0.35s
0
1
1
1
Page1 : 0.40s
Page2 : 0.40s
1
0
0
0
Page1 : 0.45s
Page2 : 0.45s
1
0
0
1
Page1 : 0.50s
Page2 : 0.50s
1
0
1
0
Page1 : 0.55s
Page2 : 0.55s
1
0
1
1
Page1 : 0.60s
Page2 : 0.60s
1
1
0
0
Page1 : 0.65s
Page2 : 0.65s
1
1
0
1
Page1 : 0.70s
Page2 : 0.70s
1
1
1
0
Page1 : 0.75s
Page2 : 0.75s
1
1
1
1
Page1 : 0.80s
Page2 : 0.80s
D7 : PGEN Automatic page switching enable
0 : Disable
1 : Enable
No.A1359-15/27
LV5230LG
address : 04h SCCON1
04h SCCON1
D7
D6
D5
D4
D3
D2
D1
D0
Register name
SCEN
SCDIR [1]
SCDIR [0]
SCMODE
SCSP [3]
SCSP [2]
SCSP [1]
SCSP [0]
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D3 to D0 : SCSP Scroll speed per dot
D3
D2
D1
D0
0
0
0
0
50ms
0
0
0
1
100ms
0
0
1
0
150ms
0
0
1
1
200ms
0
1
0
0
250ms
0
1
0
1
300ms
0
1
1
0
350ms
0
1
1
1
400ms
1
0
0
0
450ms
1
0
0
1
500ms
1
0
1
0
550ms
1
0
1
1
600ms
1
1
0
0
650ms
1
1
0
1
700ms
1
1
1
0
750ms
1
1
1
1
800ms
D4 : SCMODE Page mode when scrolling
0 : Scrolls and displays the current page repeatedly.
1 : Scrolls and displays the current and other pages alternately.
D6 to D5 : SCDIR Scroll direction
D6
D5
0
0
Right
0
1
Left
1
0
Up
1
1
Down
D7 : SCEN Scroll enable
0 : Disable
1 : Enable
No.A1359-16/27
LV5230LG
address : 05h SCCON2
05h SCCON2
D7
D6
D5
D4
D3
D2
D1
D0
Register name
SCGO
-
SCCNT [5]
SCCNT [4]
SCCNT [3]
SCCNT [2]
SCCNT [1]
SCCNT [0]
R/W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
D0 to D5 : SCCNT Scroll increment
17 × 7 mode
When SCCON1.SCDIR = 0 or 1 : 1 to 34
When SCCON1.SCDIR = 2 or 3 : 1 to 14
15 × 5 mode
When SCCON1.SCDIR = 0 or 1 : 1 to 30
When SCCON1.SCDIR = 2 or 3 : 1 to 10
* Scrolls one page when SCCNT = 0.
D7 : SCGO Scroll start
0 : Standby
1 : Scroll start
* The scrolled state is maintained until SCCON1 and SCEN are set low.
No.A1359-17/27
LV5230LG
address : 06h FADECON
06h FADECON
D7
D6
D5
D4
D3
D2
D1
D0
Register name
FADEEN
FADEGO
FADEIO
FADEMOD
FDSP [3]
FDSP [2]
FDSP [1]
FDSP [0]
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D3 to D0 : FDSP Fade speed per 1 grayscale level (It takes (following set value × 64) seconds to complete fading)
D3
D2
D1
D0
0
0
0
0
2ms
0
0
0
1
4ms
0
0
1
0
6ms
0
0
1
1
8ms
0
1
0
0
10ms
0
1
0
1
12ms
0
1
1
0
14ms
0
1
1
1
16ms
1
0
0
0
18ms
1
0
0
1
20ms
1
0
1
0
22ms
1
0
1
1
24ms
1
1
0
0
26ms
1
1
0
1
28ms
1
1
1
0
30ms
1
1
1
1
32ms
D4 : FADEMOD Single/continuous switching
0 : Single fade-in/fade-out operation
1 : Fade-in/fade-out operation repeated
D5 : FADEIO Fade-in/fade-out switching
0 : Fade in
1 : Fade out
D6 : FADEGO Fade-in/fade-out start
0 : Standby
1 : Fade-in/fade-out operation start
D7 : FADEEN Fade-in/fade-out enable
0 : Disable
1 : Enable
* The interrupt flag is set high after a fade operation has completed. Manual clearing is required.
* All LEDs are turned off if FADEEN is set to 1 when FADEO is set to 0.
If GO is set to 1 in that state, fade-in operation starts and LEDs are turned on.
No.A1359-18/27
LV5230LG
address : 07h ROWSW
07h ROWSW
D7
D6
D5
D4
D3
D2
D1
D0
Register name
ROWSWEN
ROWSW7
ROWSW6
ROWSW5
ROWSW4
ROWSW3
ROWSW2
ROWSW1
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D0 : ROWSW1 Row 1 display ON/OFF
0 : ON
1 : OFF
D1 : ROWSW2 Row 2 display ON/OFF
0 : ON
1 : OFF
D2 : ROWSW3 Row 3 display ON/OFF
0 : ON
1 : OFF
D3 : ROWSW4 Row 4 display ON/OFF
0 : ON
1 : OFF
D4 : ROWSW5 Row 5 display ON/OFF
0 : ON
1 : OFF
D5 : ROWSW6 Row 6 display ON/OFF
0 : ON
1 : OFF
D6 : ROWSW7 Row 7 display ON/OFF
0 : ON
1 : OFF
D7 : ROWSWEN Each row ON/OFF enable
0 : Disable
1 : Enable
No.A1359-19/27
LV5230LG
address : 08h COLSW1
08h COLSW1
D7
D6
D5
D4
D3
D2
D1
D0
Register name
COLSWEN
-
-
-
-
-
-
COLSW17
R/W
W
W
Default
0
0
D0 : COLSW17 Row 17 display ON/OFF
0 : ON
1 : OFF
D7 : COLSWEN Column ON/OFF enable
0 : Disable
1 : Enable
address : 09h COLSW2
09h COLSW2
D7
D6
D5
D4
D3
D2
D1
D0
Register name
COLSW16
COLSW15
COLSW14
COLSW13
COLSW12
COLSW11
COLSW10
COLSW9
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D0 : COLSW9 Column 9 display ON/OFF
0 : ON
1 : OFF
D1 : COLSW10 Column 10 display ON/OFF
0 : ON
1 : OFF
D2 : COLSW11 Column 11 display ON/OFF
0 : ON
1 : OFF
D3 : COLSW12 Column 12 display ON/OFF
0 : ON
1 : OFF
D4 : COLSW13 Column 13 display ON/OFF
0 : ON
1 : OFF
D5 : COLSW14 Column 14 display ON/OFF
0 : ON
1 : OFF
D6 : COLSW15 Column 15 display ON/OFF
0 : ON
1 : OFF
D7 : COLSW16 Column 16 display ON/OFF
0 : ON
1 : OFF
No.A1359-20/27
LV5230LG
address : 0Ah COLSW3
0Ah COLSW3
D7
D6
D5
D4
D3
D2
D1
D0
Register name
COLSW8
COLSW7
COLSW6
COLSW5
COLSW4
COLSW3
COLSW2
COLSW1
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D0 : COLSW1 Column 1 display ON/OFF
0 : ON
1 : OFF
D1 : COLSW2 Column 2 display ON/OFF
0 : ON
1 : OFF
D2 : COLSW3 Column 3 display ON/OFF
0 : ON
1 : OFF
D3 : COLSW4 Column 4 display ON/OFF
0 : ON
1 : OFF
D4 : COLSW5 Column 5 display ON/OFF
0 : ON
1 : OFF
D5 : COLSW6 Column 6 display ON/OFF
0 : ON
1 : OFF
D6 : COLSW7 Column 7 display ON/OFF
0 : ON
1 : OFF
D7 : COLSW8 Column 8 display ON/OFF
0 : ON
1 : OFF
No.A1359-21/27
LV5230LG
address : 0Bh DFCON1
0Bh DFCON1
D7
D6
D5
D4
D3
D2
D1
D0
Register name
DFEN
DFGO
-
-
DFDIR
DFNUM [2]
DFNUM [1]
DFNUM [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D2 to D0 : DFNUM Number of palette to be faded to
0 : Invalid
1 to 7 : Correspond to PWMDUTY1 to PWMDUTY7.
D3 : DFDIR Fading direction
0 : Fade in
1 : Fade out
D6 : DFGO Fade start
0 : Standby
1 : Start
D7 : DFEN Fade enable
0 : Disable
1 : Enable
* The interrupt flag is set high after a fade operation has completed. Manual clearing is required.
address : 0Ch DFCON2
0Ch DFCON2
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
-
-
DFSP [3]
DFSP [2]
DFSP [1]
DFSP [0]
R/W
W
W
W
W
Default
0
0
0
0
D3 to D0 : DFSP Fading speed per grayscale
D3
D2
D1
D0
0
0
0
0
2ms
0
0
0
1
4ms
0
0
1
0
6ms
0
0
1
1
8ms
0
1
0
0
10ms
0
1
0
1
12ms
0
1
1
0
14ms
0
1
1
1
16ms
1
0
0
0
18ms
1
0
0
1
20ms
1
0
1
0
22ms
1
0
1
1
24ms
1
1
0
0
26ms
1
1
0
1
28ms
1
1
1
0
30ms
1
1
1
1
32ms
No.A1359-22/27
LV5230LG
address : 0Dh MAXDUTY
0Dh MAXDUTY
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
MXDTY [5]
MXDTY [4]
MXDTY [3]
MXDTY [2]
MXDTY [1]
MXDTY [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : MXDTY Maximum DUTY value
n : 0 to 63 Maximum DUTY value (n/64) × 100[%]
* 100[%] when n = 63.
address : 10h PWMDUTY1
10h PWMDUTY1
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY1 [5]
DUTY1 [4]
DUTY1 [3]
DUTY1 [2]
DUTY1 [1]
DUTY1 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY1 DUTY value for brightness 1 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 11h PWMDUTY2
11h PWMDUTY2
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY2 [5]
DUTY2 [4]
DUTY2 [3]
DUTY2 [2]
DUTY2 [1]
DUTY2 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY2 DUTY value for brightness 2 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 12h PWMDUTY3
12h PWMDUTY3
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY3 [5]
DUTY3 [4]
DUTY3 [3]
DUTY3 [2]
DUTY3 [1]
DUTY3 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY3 DUTY value for brightness 3 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 13h PWMDUTY4
13h PWMDUTY4
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY4 [5]
DUTY4 [4]
DUTY4 [3]
DUTY4 [2]
DUTY4 [1]
DUTY4 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY4 DUTY value for brightness 4 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
No.A1359-23/27
LV5230LG
address : 14h PWMDUTY5
14h PWMDUTY5
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY5 [5]
DUTY5 [4]
DUTY5 [3]
DUTY5 [2]
DUTY5 [1]
DUTY5 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY5 DUTY factor value for brightness 5 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 15h PWMDUTY6
15h PWMDUTY6
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY6 [5]
DUTY6 [4]
DUTY6 [3]
DUTY6 [2]
DUTY6 [1]
DUTY6 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY6 DUTY factor value for brightness 6 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 16h PWMDUTY7
16h PWMDUTY7
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
DUTY7 [5]
DUTY7 [4]
DUTY7 [3]
DUTY7 [2]
DUTY7 [1]
DUTY7 [0]
R/W
W
W
W
W
W
W
Default
0
0
0
0
0
0
D5 to D0 : DUTY7 DUTY factor value for brightness 7 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
No.A1359-24/27
LV5230LG
address : 20h to 9Dh FRAMEDATA
20h to 9Dh FRAMEDATA
D7
D6
D5
D4
D3
D2
D1
D0
Register name
BRn
LMn [2]
LMn [1]
LMn [0]
BRm
LMm [2]
LMm [1]
LMm [0]
R/W
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
D2 to D0 : LM11m Frame 1 : vertical 1st : horizontal (n + 1) th LED brightness
D2
D1
0
0
D0
0
Off
0
0
1
On at brightness set by PWMDUTY1 register
0
1
0
On at brightness set by PWMDUTY2 register
0
1
1
On at brightness set by PWMDUTY3 register
1
0
0
On at brightness set by PWMDUTY4 register
1
0
1
On at brightness set by PWMDUTY5 register
1
1
0
On at brightness set by PWMDUTY6 register
1
1
1
On at brightness set by PWMDUTY7 register
D3 : BR11m Frame 1 : vertical 1: horizontal (n + 1) th LED flashing/brightness inversion enable
0 : Flashing/brightness inversion disabled
1 : Flashing/brightness inversion enabled
D6 to D4 : LM11n Frame 1 : vertical 1 : horizontal (n) th LED brightness
D2
D1
0
0
D0
0
Off
0
0
1
On at brightness set by PWMDUTY1 register
0
1
0
On at brightness set by PWMDUTY2 register
0
1
1
On at brightness set by PWMDUTY3 register
1
0
0
On at brightness set by PWMDUTY4 register
1
0
1
On at brightness set by PWMDUTY5 register
1
1
0
On at brightness set by PWMDUTY6 register
1
1
1
On at brightness set by PWMDUTY7 register
D7 : BR11n Frame 1 : vertical 1 : horizontal (n) th LED flashing/brightness inversion enable
0 : Flashing/brightness inversion disabled
1 : Flashing/brightness inversion enabled
* These are used for each LED data. One register is loaded with two LEDs data.
See the table on the following page for the storage address of each dot.
No.A1359-25/27
LV5230LG
Frame Data Register Tables xxH : higher-order 4 bits of register xx xxL : lower-order 4 bits of register xx
17 × 7 mode
Frame 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
20H
20L
21H
21L
22H
22L
23H
23L
24H
24L
25H
25L
26H
26L
27H
27L
28H
2
29H
29L
2AH
2AL
2BH
2BL
2CH
2CL
2DH
2DL
2EH
2EL
2FH
2FL
30H
30L
31H
3AH
3
32H
32L
33H
33L
34H
34L
35H
35L
36H
36L
37H
37L
38H
38L
39H
39L
4
3BH
3BL
3CH
3CL
3DH
3DL
3EH
3EL
3FH
3FL
40H
40L
41H
41L
42H
42L
43H
5
44H
44L
45H
45L
46H
46L
47H
47L
48H
48L
49H
49L
4AH
4AL
4BH
4BL
4CH
6
4DH
4DL
4EH
4EL
4FH
4FL
50H
50L
51H
51L
52H
52L
53H
53L
54H
54L
55H
7
56H
56L
57H
57L
58H
58L
59H
59L
5AH
5AL
5BH
5BL
5CH
5CL
5DH
5DL
5EH
Frame 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
5FH
5FL
60H
60L
61H
61L
62H
62L
63H
63L
64H
64L
65H
65L
66H
66L
67H
2
68H
68L
69H
69L
6AH
6AL
6BH
6BL
6CH
6CL
6DH
6DL
6EH
6EL
6FH
6FL
70H
3
71H
71L
72H
72L
73H
73L
74H
74L
75H
75L
76H
76L
77H
77L
78H
78L
79H
4
7AH
7AL
7BH
7BL
7CH
7CL
7DH
7DL
7EH
7EL
7FH
7FL
80H
80L
81H
81L
82H
5
83H
83L
84H
84L
85H
85L
86H
86L
87H
87L
88H
88L
89H
89L
8AH
8AL
8BH
6
8CH
8CL
8DH
8DL
8EH
8EL
8FH
8FL
90H
90L
91H
91L
92H
92L
93H
93L
94H
7
95H
95L
96H
96L
97H
97L
98H
98L
99H
99L
9AH
9AL
9BH
9BL
9CH
9CL
9DH
15 × 5 mode
Frame 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
20H
20L
21H
21L
22H
22L
23H
23L
24H
24L
25H
25L
26H
26L
27H
2
29H
29L
2AH
2AL
2BH
2BL
2CH
2CL
2DH
2DL
2EH
2EL
2FH
2FL
30H
3
32H
32L
33H
33L
34H
34L
35H
35L
36H
36L
37H
37L
38H
38L
39H
4
3BH
3BL
3CH
3CL
3DH
3DL
3EH
3EL
3FH
3FL
40H
40L
41H
41L
42H
5
44H
44L
45H
45L
46H
46L
47H
47L
48H
48L
49H
49L
4AH
4AL
4BH
Frame 2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4DH
4DL
4EH
4EL
4FH
4FL
50H
50L
51H
51L
52H
52L
53H
53L
54H
5DH
2
56H
56L
57H
57L
58H
58L
59H
59L
5AH
5AL
5BH
5BL
5CH
5CL
3
5FH
5FL
60H
60L
61H
61L
62H
62L
63H
63L
64H
64L
65H
65L
66H
4
68H
68L
69H
69L
6AH
6AL
6BH
6BL
6CH
6CL
6DH
6DL
6EH
6EL
6FH
5
71H
71L
72H
72L
73H
73L
74H
74L
75H
75L
76H
76L
77H
77L
78H
No.A1359-26/27
LV5230LG
address : FFh STATUS
FFh STATUS
D7
D6
D5
D4
D3
D2
D1
D0
Register name
-
-
-
-
-
DFIF
FEDIF
SCRIF
R
R
R
X
X
X
X
X
R/W
Default
D0 : SCRIF End of scroll interrupt occurrence flag
0 : No end of scroll interrupt has occurred.
1 : An end of scroll interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.SCRLCLR).
D1 : FEDIF End of fade interrupt occurrence flag
0 : No end of fade interrupt has occurred.
1 : An end of fade interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.FADECLR).
D2 : DFIF End of palette fade interrupt occurrence flag
0 : No end of palette fade interrupt has occurred.
1 : An end of palette fade interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.DFCLR).
The OR of SCRIF, FEDIF and DFIF appear at the interrupt pin.
* The addresses used here are all dummy and not used in actual communications.
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A1359-27/27
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