LV25500PQA Bi-CMOS LSI FM Multiplex Broadcasting Receive Tuner http://onsemi.com Overview LV25500PQA is in-vehicle FM multiplex broadcasting receive only tuner IC that makes FM tuner, PLL, and the RDS demodulator single-chip. ON Semiconductor’s unique technology enables to reduce a large number of external components for high frequency like coils, ceramic filters and varicaps which were required for conventional tuner IC. Small FM multiple tuner that can be installed also in PND etc. including AVN can be composed. WQFN56 7x7, 0.4P Features No need for adjustment work. The AF search processing on the main tuner side is unnecessary according to using with the main tuner together. The high sensitivity reception and the high strong input tolerance are united by LNA built into equipped with the WIDE-AGC function. The third and fifth high harmonic rejection type mixers of a local oscillation are adopted. The switch of UPPER/LOWER of a local oscillation and IF-BPF of injection is possible when the image signal is detected. The complex BPF of the image attenuation type is built into. IF-BPF is made built-in by LOW-IF frequency (IF = 575 kHz) adoption. Dynamic range of S meter is wide. S meter tuning-system is adopted. The DLL demodulation method is adopted for FM demodulation circuit. LPF for the carrier removal is built into. S meter level, the adjacent obstruction level, and the multipath can be detected and read by way of I2C BUS. BPF (57 kHz) for the BPSK detection is built into. It becomes easy to miniaturize the tuner set with built-in the RDS demodulator. 36.8MHz is adopted for the crystal oscillation frequency. The number of external parts is little. Functions FM tuner function Antenna dumping control function Local oscillation of PLL control type WIDE/NARROW/IF-AGC function DLL demodulator 57kHz carrier recovery and re-clock regeneration BPSK decode / differential decode ID reset function I2C BUS control I2C reset function Standby function * I2C Bus is a trademark of Philips Corporation. ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2014 September 2014 - Rev. 2 1 Publication Order Number : LV25500PQA/D LV25500PQA Specification Absolute Maximum Ratings at Ta = 25ºC Parameter Maximum supply voltage Symbol VCC max Conditions Ta = 25ºC Ratings unit 6.0 V VIN1max LNA_P, LNA_N 0.3 to 6.0 V VIN2max TEST, RST, XSTBY, XRST 0.3 to 3.45 V VIN3max SDA, SCL 0.3 to 3.45 V VO1max LPFO, BPSK, SMETER 0.3 to 6.0 V VO2max RDS-ID, RDDA, RDCL, INT, SD 0.3 to 3.45 V VO3max SDA 0.3 to 3.45 V Allowable power dissipation Pd max Ta≤85ºC (*)Specified board 1.38 W Operating temperature Topr 40 to +85 ºC Storage temperature Tstg 50 to +150 ºC Maximum input voltage Maximum output voltage (*) Specified board is attached：80.0mm×80.0mm×1.0mm, glass epoxy board Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Note : Machine model ESD voltage level of the pin 18 is less than 200V, because their high frequency characteristics are extremely important. Handle pins 18 with care to prevent electrostatic breakdown. Operating Conditions at Ta = 25ºC Parameter Symbol Conditions Ratings Recommended supply voltage VCC Operating supply voltage range VCC op Input High level voltage VINH1 TEST, RST, XSTBY, XRST VINH2 SDA, SCL 2.3 to 3.45V VINL1 TEST, RST, XSTBY, XRST 0.5V or less VINL2 SDA, SCL 0.9V or less fSCL SCL Input Low level voltage SCL clock frequency 5.0V 4.5 to 5.5V 3 to 3.45V 400kHz or less Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Range of Reception Frequency Parameter FM input frequency1 Symbol FM_EU Ratings unit FM EU Conditions 87.5 to 108.0 MHz FM input frequency2 FM_US FM US 87.9 to 108.1 MHz FM input frequency3 FM_JP FM JP 76 to 90 MHz The constant in application circuit is different in FM_EU, FM_US and FM_JP. http://www.onsemi.com 2 LV25500PQA Electric Characteristics at Ta = 25ºC, VCC = 5.0V fc = 98.1MHz, Vin = 60dBuVEMF, fm = 1kHz, Audio filter: HPF = 100Hz, LPF = 15kHz Parameter Usable sensitivity 1 (S/N30dB) Usable sensitivity 2 (S/N10dB) Symbol SN30 SN10 Conditions 22.5kHz dev, fm = 1kHz, S/N = 30dB input level 7.5kHz dev, fm = 76kHz, S/N = 10dB input level [1] min typ max unit - 12 20 dBuVEMF - 27 - dBuVEMF 34 46 - dB - 23 - dB 34 45 - dB - 46 - dB SN ratio 1 SN1 22.5kHz dev, fm = 1kHz SN ratio 2 SN2 7.5kHz dev, fm = 76kHz [1] AM suppression ratio AMR AM 30% mod Image removal ratio IMR 22.5kHz dev, fm = 1kHz Audio output level 1 ADO1 7.5kHz dev, fm = 1kHz [1] 12 30 45 mVrms Audio output level 2 ADO2 7.5kHz dev, fm = 76kHz [1] 12 23 45 mVrms SD sensitivity SDS LNA input level when SD terminal is on. 13 20 27 dBuVEMF Center frequency f0 57kHz BPF peak frequency VOL1 RDDA, RDCL, INT, SD IOL=0.5mA - - 0.5 V VOL2 RDS-ID,IOL=0.5mA - - 0.5 V VOL3 SDA (when VDD pull up) RDDA, RDCL, INT, SD IOH=0.5mA - - 0.5 V 2.3 - - V - V Output (L) level voltage VOH1 Output (H) level voltage VOH2 Current consumption 1 ICC1 Current consumption 2 ICC2 SDA (when VDD pull up) When no signal input RDS mode When no signal input VICS mode 57 0.7*VDD [2] kHz 125 165 205 mA 120 155 190 mA [1] Audio filter : HPF = 100Hz, LPF = OFF [2] VDD : μ-COM Supply Voltage Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://www.onsemi.com 3 LV25500PQA RDS input/output Format RST Pin Normal operation Reset of RDS-ID and demodulator circuit RST= 0 RST= 1 RDS-ID RDS-IDoutput Active-Low RDCL/RDDA Output timing 421μs 421μs Tp RDCL output RDDA Output 17μs Tp 17μs RDS-ID Output timing RDS-ID High/Low High/Low High/Low High/Low High/Low High/Low High/Low RDCL RDDA Note : RDS-ID is High : data with Low RDS reliability, Low: data with High RDS reliability RST operation Tp3 250ns RST RDS detection circuit output RDCL RDDA Note : RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is detected. Note : When the reception channel is changed, a memory reset must be applied using RST input. http://www.onsemi.com 4 LV25500PQA Package Dimensions WQFN56 (7.0mm x 7.0mm) unit : mm WQFN56 7x7, 0.4P CASE 510BD ISSUE O D L A B NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 PIN 1 INDICATOR DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E 2X EXPOSED Cu 0.15 C 0.15 C 2X 0.10 C TOP VIEW DIM A A1 A3 b D D2 E E2 e L L1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION (A3) DETAIL B MILLIMETERS MIN MAX 0.80 0.00 0.05 0.20 REF 0.15 0.25 7.00 BSC 5.10 5.30 7.00 BSC 5.10 5.30 0.40 BSC 0.30 0.50 0.00 0.15 A 0.08 C GENERIC MARKING DIAGRAM* A1 NOTE 4 0.10 DETAIL A SEATING PLANE C SIDE VIEW M 1 XXXXXXXXX XXXXXXXXX AWLYYWWG C A B D2 15 0.10 29 M C A B A WL YY WW G E2 *This information is generic. Please refer to device data sheet for actual part marking. 1 56 56X L 43 e e/2 BOTTOM VIEW = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 56X b 0.10 M C A B 0.05 M C RECOMMENDED SOLDERING FOOTPRINT* NOTE 3 2X 5.40 1 2X 7.30 56X 0.63 56X 0.26 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://www.onsemi.com 5 LV25500PQA Block Diagram http://www.onsemi.com 6 LV25500PQA C23 0.1µF XTALI REG_XO REG_PLL VCC_PLL C15 0.022µF GND_LOG C14 0.1µF VDD_PLL C26 0.1µF REG_LOG VDDA VDD_LOG CPRDS CP GND_PLL C13 R1 3300pF 18k NC C12 270pF NC SD/TEST1 NC LO_2 C11 0.022µF L4 2.7nH GND_LO INT/TEST2 RDS-ID LO_1 C10 0.022µF L3 2.7nH VCC_LO RDDA VEE SCL C9 0.022µF VCC_FE SDA RDCL R5 560 C27 0.01µF C28 0.47µF R6 1kΩ R7 1kΩ R8 1kΩ R9 3.3kΩ R10 3.3kΩ Example of application circuit (FM_US) [1] [2] [3] [4] [5] Used Components(FM_US) Component L1 L2 L3/L4 X1 Parameter RF BPF coil RF BPF coil Local OSC coil Crystal Value 270nH 220nH 2.7nH 36.8MHz Supplier SAGAMI SAGAMI SAGAMI KDS Type C2012C-R27G-RC C2012C-R22G-RC C2012H-2N7D-RD DSX321G [1] The external parts for crystal oscillation circuit terminal (pin42 and pin43) need to match the quartz vibrator. R3, R4, C24, C25 are the tentative arrangement parts. [2] Caution is required for layout of the board because the parasitic capacitance between pin42, pin43 and Power, GND, etc causes the decrease of the margin of the crystal oscillation and the deviation of the crystal frequency, etc. [3] This IC uses the signal of FM band frequency (VCO divided into 1/4) which leaks into ANT pin. If the VCO leakage affects the performance of the system, make sure to connect an isolator on ANT pin path. [4] REG (pin27, pin44, pin46) is only used for LV25500. [5] This example of application circuit, the power-supply voltage becomes the circuit using 3.3V μ-COM. The bi-directional level shifter circuit is connecting two different voltage sections in I2C-Bus system. http://www.onsemi.com 7 LV25500PQA Example of level shift circuit VDD2=5V VDD1=3.3V g s SDA1 d SDA2 g s SCL1 d SCL2 g s RDS-ID1 RST1 XRST1 XSTBY1 3.3V DEVICE d 5V DEVICE LV25500 http://www.onsemi.com 8 RDS-ID2 RST2 XRST2 XSTBY2 LV25500PQA Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name XSTBY XRST RST TEST3 GND_IFBPF VCC_IFBPF VCC_MIX WAGC NC GND_MIX LNA_P GND_FE LNA_N ANTD VCC_FE VEE VCC_LO LO_1 GND_LO LO_2 NC NC CP GND_PLL VDDA VDD_PLL REG_PLL VCC_PLL IFAGC DEMOC LPFDCC SMETER LPFO VCC_IF BPFC GND_IF BPSK SLC DEVAR VCC_LOG NC XTALO XTALI REG_XO I/O I I I P P P O NC P I P I O P P P O P O NC NC O P P P O P O O O O O P O P O I I P NC O I 45 46 47 48 49 50 51 52 GND_LOG REG_LOG VDD_LOG CPRDS NC SD/TEST1 INT/TEST2 RDS-ID Ｏ P O P O NC O O O 53 54 55 56 RDCL RDDA SCL SDA O O I I/O Explanation Standby pin(0:stanby, 1:standby release) Tuner reset pin (0:reset, 1:reset release) RDS–ID reset pin(Positive polarity) Test pin GND pin for IF BPF VCC pin for IF BPF VCC pin for MIXER Capacity pin for WAGC No connection GND pin for MIXER Input pin for LNA+ GND pin for LNA Input pin for LNAANT dumping control pin Power-supply pin for LNA GND pin for ESD VCC pin for local oscillation Inductor connection pin for local oscillation GND pin for local oscillation Inductor connection pin for local oscillation No connection No connection Capacity pin for PLL charge pump GND pin for PLL logic Power-supply pin for logic Power-supply pin for PLL logic Regulator capacity pin for PLL logic Power-supply pin for Regulator Capacity pin for IFAGC Capacity pin for demodulation/detection Capacity pin for LPF DC cancel S-meter output pin FM demodulation output pin (After band limitation) VCC pin IF Capacity pin for BPF GND pin for IF Bi-phase data career output pin Data slicer input pin Device address setting pin VCC pin for Regulator No connection Crystal resonance element connection pin Crystal resonance element connection pin Regulator pin for crystal GND pin for control logic Regulator pin for control logic Power-supply pin for control logic PLL charge pump pin for RDS clock generation No connection Station detector pin/Test pin Interrupt flag pin/Test pin RDS reliability data output pin (0:high reliability, 1:low reliability) RDS clock output pin RDS data output pin Serial data clock input pin Serial data input/output pin http://www.onsemi.com 9 LV25500PQA 2 I C Bus Communication Format Device address (in case of 39pin, DEVAR, pull down) Normal MSB LSB A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 Device address (in case of 39pin, DEVAR, pull up) MSB A7 A6 A5 A4 A3 A2 A1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 LSB A0 0 1 Register Address: Reg 0 ~ Reg 2Fh MSB A7 A6 A5 A4 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 LSB A0 0 1 0 : 1 0 1 A2 0 0 0 : 1 1 1 A1 0 0 1 : 0 1 1 Function WRITE mode (C0h) READ mode (C1h) Function WRITE mode (C2h) READ mode (C3h) Function Reg0 : 00h Reg1 : 01h Reg2 : 02h : Reg29 : 2Dh Reg30 : 2Eh Reg31 : 2Fh Bus transmission format description Format conforms to the I2C standard (see below). Start condition Repeated start condition Stop condition Write byte Read byte Start, Repeated start, and stop conditions are defined under the conditions shown below. Start Repeated Start Stop SCL SCL SCL SDA SDA SDA The I2C start, repeated start and stop conditions. For detailed information such as timing, refer to the I2C specifications. http://www.onsemi.com 10 LV25500PQA 8Bit Write 8Bit data is sent from the master microcomputer to LV25500. For data bit, MSB first, LSB last. Data transmission is synchronized with the SCL clock generated by the master IC. It is latched on the rising edge of SCL. Data should not be changed while SCL is HIGH. LV25500 outputs an ACK bit during the 8th and 9th of the falling edge of SCL. SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Signal pattern of the I2C byte write 8Bit Read Read is similar with Write format but data direction is opposite. 8Bit data is sent from LV25500 to the master, and ACK is sent from the master to the LV25500. SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Signal pattern of the I2C byte read Serial clock SCL will be provided by the master side. Data bits which are out from the LV25500 are synchronized with the falling edge. And the master side should latch the data bits on the rising edge. LV25500 latches the ACK on the rising edge. The following is the sequence that writes data D to the LV25500 register A. (In case of PULL DOWN) http://www.onsemi.com 11 LV25500PQA Write Sequence Start condition confirmation Write device address(C0h) Write address information A Write Data D Stop condition write device address start SCL DA7 SDA Ack DA6 ... 1 write register address A7 A6 ... 0 write data byte Ack D7 D6 ... 0 stop Ack Register write through I2C If more than one data was written, only the first data will be written. Read Sequence Start condition confirmation Write device address (C0h) Write address information A Repeated start condition (Or, stop + start sequence by the master) Write device address +1 (C1h) Read Register information D and send NACK (no more data to be read) Stop condition start write device address write register address rep. SCL DA7 SDA start Ack DA6 ... 1 write device address + 1 DA7 DA6 ... 1 A7 A6 ... 1 read data byte with NACK Ack D7 D6 ... 0 Register read through I2C http://www.onsemi.com 12 Ack stop LV25500PQA ORDERING INFORMATION Device LV25500PQA-NH Package WQFN56 7x7, 0.4P (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2500 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. http://www.onsemi.com 13