1/2 Duty General Purpose LCD Driver IC

Ordering number : ENA1578
LC75841PE
CMOS IC
Static Drive, 1/2-Duty Drive
General-Purpose LCD
Display Driver
http://onsemi.com
Overview
The LC75841PE is static drive or 1/2-duty drive, microcontroller-controlled general-purpose LCD driver that can be
used in applications such as frequency display in products with electronic tuning. In addition to being capable to drive
up to 54 segments directly, it can control up to 4 general-purpose output ports.
Features
• Serial data control of switching between static drive mode and 1/2 duty drive mode.
When 1/1-duty: Capable of driving up to 27 segments
When 1/2-duty: Capable of driving up to 54 segments
• Serial data input supports CCB format communication with the system controller.
• Serial data control of the power-saving mode based backup function and the all segments forced off function.
• Serial data control of switching between the segment output port and general-purpose output port functions
(up to 4 general-purpose output ports).
• Serial data control of the frame frequency of the common and segment output waveforms.
• Either RC oscillator operating or external clock operating mode can be selected with the serial control data.
• High generality, since display data is displayed directly without the intervention of a decoder circuit.
• The INH pin allows the display to be forced to the off state.
• Allows compatible operation with the LC75842 (842 mode transfer function).
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
•
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
N1809HKIM 20091006-S00001 No.A1578-1/18
LC75841PE
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Symbol
Conditions
VDD max
Input voltage
Ratings
VDD
Unit
-0.3 to +7.0
V
VIN1
CE, CL, DI, INH
VIN2
OSC
-0.3 to VDD+0.3
Output voltage
VOUT
S1 to S27, COM1, COM2, P1 to P4, OSC
-0.3 to VDD+0.3
V
Output current
IOUT1
S1 to S27
300
μA
IOUT2
COM1, COM2
3
IOUT3
P1 to P4
5
Pd max
Ta=105°C
Allowable power dissipation
-0.3 to +7.0
V
mA
50
mW
Operating temperature
Topr
-40 to +105
°C
Storage temperature
Tstg
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +105°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
unit
max
Supply voltage
VDD
VDD
4.0
6.0
Input high-level voltage
VIH1
CE, CL, DI, INH
0.45VDD
6.0
VIH2
OSC External clock operating mode
0.45VDD
VDD
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSC External clock operating mode
0
0.2VDD
Rosc
OSC RC oscillator operating mode
Cosc
OSC RC oscillator operating mode
fosc
OSC RC oscillator operating mode
External clock operating frequency
fCK
OSC External clock operating mode [Figure 3]
External clock duty cycle
DCK
OSC External clock operating mode [Figure 3]
Input low-level voltage
Recommended external resistor
for RC oscillation
Recommended external capacitor
for RC oscillation
Guaranteed range of RC
oscillation
Data setup time
tds
Data hold time
tdh
CE wait time
tcp
CE setup time
tcs
CE hold time
tch
High-level clock pulse width
Low-level clock pulse width
CL, DI
V
V
V
39
kΩ
1000
pF
19
38
76
kHz
19
38
76
kHz
30
50
70
%
[Figure 1][Figure 2]
160
ns
CL, DI
[Figure 1][Figure 2]
160
ns
CE, CL
[Figure 1][Figure 2]
160
ns
CE, CL
[Figure 1][Figure 2]
160
ns
CE, CL
[Figure 1][Figure 2]
160
ns
tφH
CL
[Figure 1][Figure 2]
160
ns
tφL
CL
[Figure 1][Figure 2]
160
ns
Rise time
tr
CE, CL, DI
[Figure 1][Figure 2]
160
ns
Fall time
tf
CE, CL, DI
[Figure 1][Figure 2]
160
ns
INH switching time
tc
INH, CE
[Figure 4][Figure 5][Figure 6]
10
μs
No.A1578-2/18
LC75841PE
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Ratings
Conditions
min
typ
unit
max
Hysteresis
VH
CE, CL, DI, INH
Input high-level current
IIH1
CE, CL, DI, INH
VI=6.0V
5.0
IIH2
OSC
VI=VDD External clock operating mode
5.0
IIL1
CE, CL, DI, INH
VI=0V
-5.0
IIL2
OSC
VI=0V External clock operating mode
-5.0
Input low-level current
Output high-level voltage
Output low-level voltage
Output middle-level
0.03VDD
VOH1
S1 to S27
IO=-20μA
VDD-0.9
VOH2
COM1, COM2
IO=-100μA
VDD-0.9
VOH3
P1 to P4
IO=-1mA
VDD-0.9
S1 to S27
IO=20μA
COM1, COM2
IO=100μA
0.9
VOL3
P1 to P4
IO=1mA
0.9
VMID
COM1, COM2
1/2 bias IO=±100μA
OSC
RC oscillator operating mode,
Rosc=39kΩ, Cosc=1000pF
Current drain
V
VOL2
fosc
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD=6.0V, Output open,
RC oscillator operating mode,
μA
μA
VOL1
voltage
Oscillator frequency
V
0.9
1/2VDD
1/2VDD
-0.9
+0.9
30.4
38
45.6
V
V
kHz
15
350
700
1500
3000
450
900
1600
3200
fosc=38kHz, Static
IDD3
VDD
VDD=6.0V, Output open,
RC oscillator operating mode,
fosc=38kHz, 1/2 duty
IDD4
VDD
VDD=6.0V, Output open,
External clock operating mode,
fCK=38kHz,
VIH2=0.5VDD,
VIL2=0.1VDD,
μA
Static
IDD5
VDD
VDD=6.0V, Output open,
External clock operating mode,
fCK=38kHz,
VIH2=0.5VDD,
VIL2=0.1VDD,
1/2 duty
No.A1578-3/18
LC75841PE
1. When CL is stopped at the low level
tφL
tcp
≈ ≈
DI
tf
VIH1
VIL1
tds
≈ ≈ ≈
VIH1
50%
VIL1
tr
VIL1
≈ ≈
tφH
CL
≈
VIH1
CE
tcs
tch
tdh
[Figure 1]
2. When CL is stopped at the high level
≈
VIH1
CE
≈
VIL1
tφH
≈
tφL
VIH1
50%
VIL1
CL
tr
tcp
tcs
≈ ≈
≈ ≈ ≈
tf
VIH1
DI
VIL1
tds
tch
tdh
[Figure 2]
3. OSC pin clock timing in external clock operating mode
tCKH
OSC
VIH2
50%
VIL2
tCKL
fCK=
1
tCKH+ tCKL
[kHz]
tCKH
×100[%]
DCK=
tCKH+ tCKL
[Figure 3]
No.A1578-4/18
LC75841PE
Package Dimensions
unit:mm (typ)
3162C
27
0.5
9.0
7.0
19
28
7.0
9.0
18
36
10
1
9
0.65
0.15
0.3
(1.5)
0.1
1.7max
(0.9)
SANYO : QFP36(7X7)
S27
S26
S25
S24
S23
S22
S21
S20
S19
27
26
25
24
23
22
21
20
19
Pin Assignment
OSC
28
18
S18
VDD
29
17
S17
INH
30
16
S16
VSS
31
15
S15
CE
32
14
S14
CL
33
13
S13
DI
34
12
S12
COM2
35
11
S11
COM1
36
10
S10
9
S9
8
S8
7
S7
6
S6
5
S5
4
P4/S4
3
P3/S3
2
P2/S2
P1/S1
1
LC75841PE
Top view
No.A1578-5/18
LC75841PE
COMMON
DRIVER
S1/P1
S2/P2
S3/P3
S4/P4
S5
S26
S27
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
CONTROL
REGISTER
CLOCK
GENERATOR
OSC
SHIFT REGISTER
CCB INTERFACE
VDD
CE
CL
DI
VSS
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1/P1 to S4/P4
1 to 4
S5 to S27
5 to 27
COM1
36
COM2
35
OSC
28
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports when so set
-
O
OPEN
-
O
OPEN
-
I/O
VDD
H
I
up by the control data.
Common driver outputs. The frame frequency is fo [Hz].
Oscillator connection. An oscillator circuit is formed by connecting an external
resistor and capacitor to this pin. This pin can be used as the external clock input
pin if external clock operating mode is selected with the control data.
Serial data transfer inputs. Must be connected to the controller.
CE
32
CE: Chip enable
CL
33
CL: Synchronization clock
DI
34
DI: Transfer data
I
-
I
L
I
GND
Display off control input
• INH = low (VSS) ...Display forced off
S1/P1 to S4/P4 = low (VSS)
(These pins are forcibly set to the segment output port function
and held at the VSS level.)
INH
30
S5 to S27 = low (VSS)
COM1, COM2 = low (VSS)
OSC = Z (high impedance)
GND
RC oscillation stopped
Inhibits external clock input.
• INH = high (VDD)...Display on
RC oscillation enabled (RC oscillator operating mode)
Enables external clock input (external clock operating mode)
However, serial data transfer is possible when the display is forced off.
VDD
29
Power supply. Provide a voltage in the range 4.0 to 6.0V.
-
-
-
VSS
31
Ground pin. Must be connected to ground.
-
-
-
No.A1578-6/18
LC75841PE
Serial Data Transfer Formats
(1) Static drive mode
1. When CL is stopped at the low level
CE
CL
DI
0 0 1 0 0 0 1 0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
27 bits
Control data
12 bits
DD
1 bit
2. When CL is stopped at the high level
CE
CL
DI
0 0 1 0 0 0 1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
27 bits
Control data
12 bits
DD
1 bit
Note: DD is the direction data.
• CCB address ....... "44H"
• D1 to D27 ......... Display data
• P0 to P2 .............. Segment output port/general-purpose output port switching control data
• DT ...................... Static drive or 1/2 duty drive switching control data
• FC0 to FC2 ......... Common/segment output waveform frame frequency control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A1578-7/18
LC75841PE
(2) 1/2 duty drive mode
1. When CL is stopped at the low level
CL
DI
0 0 1 0 0 0 1 0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
∼ ∼ ∼
∼
CE
B0 B1 B2 B3 A0 A1 A2 A3
Display data
28 bits
Control data
11 bits
DD
1 bit
∼ ∼ ∼
∼
CCB address
8 bits
0 0 1 0 0 0 1 0 D29 D30
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 0 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
26 bits
Fixed data
13 bits
DD
1 bit
2. When CL is stopped at the high level
∼ ∼
CE
0 0 1 0 0 0 1
DI
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
∼ ∼
CL
B0 B1 B2 B3 A0 A1 A2 A3
Display data
28 bits
Control data
11 bits
DD
1 bit
∼ ∼
∼ ∼
CCB address
8 bits
0 0 1 0 0 0 1 0 D29 D30
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Display data
26 bits
Fixed data
13 bits
DD
1 bit
Note: DD is the direction data.
• CCB address ....... "44H"
• D1 to D54 ......... Display data
• P0 to P2 .............. Segment output port/general-purpose output port switching control data
• DT ...................... Static drive or 1/2 duty drive switching control data
• FC0 to FC2 ......... Common/segment output waveform frame frequency control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A1578-8/18
LC75841PE
Serial Data Transfer Formats (When in 842 mode data transfer)
(1) 1/2 duty drive mode (When in 842 mode data transfer)
1. When CL is stopped at the low level
CL
DI
0 0 1 0 0 0 1 0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
28 bits
Control
data DD
3 bits 1bit
∼ ∼ ∼
∼
CCB address
8 bits
∼ ∼ ∼
∼
CE
0 0 1 0 0 0 1 0 D29 D30
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
26 bits
Fixed data
5 bits
DD
1bit
2. When CL is stopped at the high level
∼ ∼
CE
0 0 1 0 0 0 1
DI
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 0
∼ ∼
CL
B0 B1 B2 B3 A0 A1 A2 A3
Display data
28 bits
Control
DD
data
1 bit
3 bits
∼ ∼
∼ ∼
CCB address
8 bits
0 0 1 0 0 0 1 0 D29 D30
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 1
Display data
26 bits
Fixed data
5 bits
DD
1 bit
Note: DD is the direction data.
• CCB address ....... "44H"
• D1 to D54 ......... Display data
• BU ...................... Normal mode/power-saving mode control data
• SC ...................... Segments on/off control data
No.A1578-9/18
LC75841PE
Serial Data Transfer Examples
(1) Static drive mode
The serial data shown in the figure below must be sent.
8 bits
0
0
1
0
0
40 bits
0
1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0
0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
(2) 1/2 duty drive mode
• When 29 or more segments are used
96 bits of serial data (including CCB address bits) must be sent.
8 bits
0
0
1
0
0
40 bits
0
1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
D29 D30
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 29 segments are used
The serial data shown below (the D1 to D28 display data and the control data) must always be sent.
8 bits
0
0
1
0
0
40 bits
0
1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
Serial Data Transfer Examples (When in 842 mode data transfer)
(1) 1/2 duty drive mode (When in 842 mode data transfer)
• When 29 or more segments are used
80 bits of serial data (including CCB address bits) must be sent.
8 bits
0
0
1
0
0
32 bits
0
1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0
0
D29 D30
D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0
1
B0 B1 B2 B3 A0 A1 A2 A3
0
0
1
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 29 segments are used
The serial data shown in the figure below (the D1 to D28 display data, and the control data) must be sent.
8 bits
0
0
1
0
0
32 bits
0
1
0
D1 D2
D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0
0
B0 B1 B2 B3 A0 A1 A2 A3
No.A1578-10/18
LC75841PE
Control Data Functions
1. P0 to P2: Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4
output pins.
However, segment output port is forcibly selected when in 842 mode data transfer.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn (n = 1 to 4): Segment output ports
Pn (n = 1 to 4): General-purpose output ports
Note that when the general-purpose output port function is selected, the correspondence between the output pins and
the display data will be that shown in the table.
Corresponding display data
Output pin
Static drive mode
1/2 duty drive mode
S1/P1
D1
D1
S2/P2
D2
D3
S3/P3
D3
D5
S4/P4
D4
D7
For example, if the general-purpose output port function is selected for the S4/P4 output pin in 1/2 duty drive mode,
it will output a high level (VDD) when display data D7 is 1, and a low level (VSS) when D7 is 0.
2. DT: Static drive mode or 1/2 duty drive mode switching control data
This control data bit selects either static drive mode or 1/2 duty drive mode.
However, 1/2 duty drive mode is forcibly selected when in 842 mode data transfer.
DT
Duty drive mode
Output pin state (COM2)
0
Static drive mode
VSS level
1
1/2 duty drive mode
COM2
Note: COM2…Common output
3. FC0 to FC2: Common/segment output waveform frame frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
However, fo=fosc/384 is forcibly selected when in 842 mode data transfer.
Control data
Frame frequency fo [Hz]
FC0
FC1
FC2
1
1
0
fosc/768, fCK/768
1
1
1
fosc/576, fCK/576
0
0
0
fosc/384, fCK/384
0
0
1
fosc/288, fCK/288
0
1
0
fosc/192, fCK/192
No.A1578-11/18
LC75841PE
4. OC: RC oscillator operating mode/external clock operating mode switching control data
This control data bit switches the OSC pin function
(either RC oscillator operating mode or external clock operating mode).
However RC oscillator operating mode is forcibly selected when in 842 mode data transfer.
OC
OSC pin function
0
RC oscillator operating mode
1
External clock operating mode
Note: An external resistor, Rosc, and an external capacitor, Cosc, must be connected to the OSC pin if RC oscillator
operating mode is selected.
5. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
6. BU: Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power-saving mode.
In RC oscillator operating mode (OC = 0), the OSC pin oscillator is stopped, and in external clock operating mode
1
(OC = 1), acceptance of the external clock is stopped. In this mode the common and segment output pins go to the
VSS levels. However, S1/P1 to S4/P4 output pins that are set to be general-purpose output ports by the control data
P0 to P2 can be used as general-purpose output ports.
No.A1578-12/18
LC75841PE
Display Data and Output Pin Correspondence
(1) Static drive mode
Output pin
COM1
Output pin
COM1
Output pin
COM1
S1/P1
D1
S11
D11
S21
D21
S2/P2
D2
S12
D12
S22
D22
S3/P3
D3
S13
D13
S23
D23
S4/P4
D4
S14
D14
S24
D24
S5
D5
S15
D15
S25
D25
S6
D6
S16
D16
S26
D26
S27
D27
S7
D7
S17
D17
S8
D8
S18
D18
S9
D9
S19
D19
S10
D10
S20
D20
Notes: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports.
The static drive mode cannot be selected when in 842 mode data transfer.
For example, the table below lists the output states for the S11 output pin.
Display data
Output pin (S11) state
D11
0
The LCD segment corresponding to COM1 is off
1
The LCD segment corresponding to COM1 is on
(2) 1/2 duty drive mode
Output pin
COM1
COM2
Output pin
COM1
COM2
Output pin
COM1
COM2
S1/P1
D1
D2
S11
D21
D22
S21
D41
D42
S2/P2
D3
D4
S12
D23
D24
S22
D43
D44
S3/P3
D5
D6
S13
D25
D26
S23
D45
D46
S4/P4
D7
D8
S14
D27
D28
S24
D47
D48
S5
D9
D10
S15
D29
D30
S25
D49
D50
S6
D11
D12
S16
D31
D32
S26
D51
D52
S7
D13
D14
S17
D33
D34
S27
D53
D54
S8
D15
D16
S18
D35
D36
S9
D17
D18
S19
D37
D38
S10
D19
D20
S20
D39
D40
Note: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports.
For example, the table below lists the output states for the S11 output pin.
Display data
Output pin (S11) state
D21
D22
0
0
The LCD segments corresponding to COM1 and COM2 are off.
0
1
The LCD segment corresponding to COM2 is on.
1
0
The LCD segment corresponding to COM1 is on.
1
1
The LCD segments corresponding to COM1 and COM2 are on.
No.A1578-13/18
LC75841PE
Output Waveforms (Static drive mode)
fo[Hz]
VDD
COM1
0V
VDD
LCD driver output when off
0V
VDD
LCD driver output when on
0V
Output Waveforms (1/2 duty, 1/2 bias drive mode)
fo[Hz]
VDD
1/2VDD
COM1
0V
VDD
1/2VDD
COM2
0V
VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are off.
0V
VDD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
VDD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are on.
0V
Control data
Frame frequency fo [Hz]
FC0
FC1
FC2
1
1
0
fosc/768, fCK/768
1
1
1
fosc/576, fCK/576
0
0
0
fosc/384, fCK/384
0
0
1
fosc/288, fCK/288
0
1
0
fosc/192, fCK/192
No.A1578-14/18
LC75841PE
Display Control and the INH Pin
Since the IC’s internal data (the display data D1 to D27 and the control data when in static drive mode, and the display
data D1 to D54 and the control data when in 1/2 duty drive mode) is undefined when power is first applied, applications
should set the INH pin low at the same time as power is applied to turn off the display (setting S1/P1 to S4/P4 and S5 to
S27, COM1, and COM2 to the VSS level) and during this period send serial data from the controller. The controller
should then set the INH pin high after the data transfer has completed. This procedure prevents unnecessary display at
power on. (See figure 4, figure 5 and figure 6)
• Static drive mode
≈
t1
≈
VDD
INH
VIL1
CE
Internal
data
D1 to D27, P0 to P2,
DT, FC0 to FC2,
OC, SC, BU
VIL1
Display data and control data transferred
Undefined
≈ ≈ ≈
tc
Defined
Undefined
Notes: t1>0
tc ⋅⋅⋅ 10μs min
[Figure 4]
• 1/2 duty drive mode
≈
t1
≈
VDD
INH
VIL1
Internal
data
D1 to D28, P0 to P2,
DT, FC0 to FC2,
OC, SC, BU
Internal data (D29 to D54)
VIL1
Display data and control data transferred
Undefined
Defined
Undefined
≈ ≈ ≈ ≈ ≈
tc
CE
Undefined
Defined
Undefined
Notes: t1>0
tc ⋅⋅⋅ 10μs min
[Figure 5]
• 1/2 duty drive mode (when in 842 mode data transfer)
≈
t1
≈
VDD
INH
VIL1
VIL1
Display data and control data transferred
Internal data (D1 to D28, BU, SC)
Internal data (D29 to D54)
Undefined
Defined
Undefined
≈ ≈ ≈ ≈ ≈
tc
CE
Defined
Undefined
Undefined
Notes: t1>0
tc ⋅⋅⋅ 10μs min
[Figure 6]
No.A1578-15/18
LC75841PE
Notes on Controller Transfer of Display Data
Since the LC75841PE transfer the display data (D1 to D54) in two separate transfer operations in 1/2 duty drive mode,
we recommend that applications make a point of completing all of the display data transfer within a period of less than
30ms to prevent observable degradation of display quality.
OSC Pin Peripheral Circuit
(1) RC oscillator operating mode (control data OC = 0)
An external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and GND if
RC oscillator operating mode is selected.
OSC
Rosc
Cosc
(2) External clock operating mode (control data OC = 1)
When the external clock operating mode is selected, insert a current protection resistor Rg (4.7 to 47kΩ) between
the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to
the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
OSC
Rg
External oscillator
Note: Allowable current value at external clock output pin >
VDD
Rg
No.A1578-16/18
LC75841PE
Sample Application Circuit 1
Static drive mode
(P1)
(P2)
(P3)
*3
(P4)
+5.0V
OSC
*2
VDD
General-purpose
Output ports
Used for functions
such as backlight
control
COM1
VSS
LCD panel (up to 27 segments)
P1/S1
P2/S2
P3/S3
P4/S4
S5
INH
From the controller
CE
CL
DI
*4
S26
S27
COM2
OPEN
*2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected
between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor,
Rg (4.7 to 47kΩ), must be inserted between the external clock output pin (on the external oscillator) and the OSC
pin. (See the “OSC Pin Peripheral Circuit” section.)
*3: When a capacitor except the recommended external capacitance (Cosc = 1000pF) is connected to the OSC pin, it
should be in the range 220 to 2200pF.
*4: The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5.0V.
No.A1578-17/18
LC75841PE
Sample Application Circuit 2
1/2 duty drive mode
(P1)
(P2)
(P3)
*3
(P4)
+5.0V
OSC
*2
VDD
General-purpose
Output ports
Used for functions
such as backlight
control
COM1
COM2
P1/S1
P2/S2
P3/S3
P4/S4
S5
INH
From the controller
CE
CL
DI
*4
LCD panel (up to 54 segments)
VSS
S25
S26
S27
*2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected
between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor,
Rg (4.7 to 47kΩ), must be inserted between the external clock output pin (on the external oscillator) and the OSC
pin. (See the “OSC Pin Peripheral Circuit” section.)
*3: When a capacitor except the recommended external capacitance (Cosc = 1000pF) is connected to the OSC pin, it
should be in the range 220 to 2200pF.
*4: The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5.0V.
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PS No.A1578-18/18
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